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https://github.com/AsahiLinux/u-boot
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ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux
Import the R8A77990 and Ebisu DTS from linux-next to get the latest version. This makes AVB ethernet work in U-Boot since the ethernet node is now present in DT, as well as GPIOs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
63e22517a3
commit
0bb5d24852
2 changed files with 231 additions and 53 deletions
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include "r8a77990.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Renesas Ebisu board based on r8a77990";
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@ -14,6 +15,7 @@
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aliases {
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serial0 = &scif2;
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ethernet0 = &avb;
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};
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chosen {
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@ -28,10 +30,36 @@
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-txid";
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
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};
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};
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&extal_clk {
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clock-frequency = <48000000>;
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};
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&pfc {
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avb_pins: avb {
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mux {
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groups = "avb_link", "avb_mii";
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function = "avb";
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};
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};
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};
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&scif2 {
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status = "okay";
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};
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@ -27,9 +27,8 @@
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enable-method = "psci";
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};
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L2_CA53: cache-controller@0 {
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L2_CA53: cache-controller-0 {
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compatible = "cache";
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reg = <0>;
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power-domains = <&sysc 21>;
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cache-unified;
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cache-level = <2>;
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@ -43,8 +42,14 @@
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clock-frequency = <0>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>;
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};
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psci {
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compatible = "arm,psci-0.2";
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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@ -55,6 +60,194 @@
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#size-cells = <2>;
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ranges;
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 18>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc 32>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 23>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc 32>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc 32>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc 32>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 11>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc 32>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 20>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc 32>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a77990",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 18>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&sysc 32>;
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resets = <&cpg 906>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77990";
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reg = <0 0xe6060000 0 0x508>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77990-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77990-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77990-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77990",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc 32>;
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resets = <&cpg 812>;
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phy-mode = "rgmii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a77990",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@ -72,60 +265,17 @@
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resets = <&cpg 408>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77990-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77990-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77990-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a77990",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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