mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
imx: imximage: add new CHECK/CLR BIT command
* Extend imximage DCD version 2 to support DCD commands
CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:
while ((*address & ~mask) != 0);
CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
while ((*address & mask) != mask);
CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
*address = *address & ~mask;
* Add set_dcd_param_v2 helper function to set DCD
command parameters
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This commit is contained in:
Adrian Alonso
Stefano Babic
parent
452308c02b
commit
0b7f7c339c
2 changed files with 91 additions and 25 deletions
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@ -21,7 +21,10 @@
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static table_entry_t imximage_cmds[] = {
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{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
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{CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
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{CMD_DATA, "DATA", "Reg Write Data", },
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{CMD_WRITE_DATA, "DATA", "Reg Write Data", },
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{CMD_WRITE_CLR_BIT, "CLR_BIT", "Reg clear bit", },
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{CMD_CHECK_BITS_SET, "CHECK_BITS_SET", "Reg Check bits set", },
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{CMD_CHECK_BITS_CLR, "CHECK_BITS_CLR", "Reg Check bits clr", },
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{CMD_CSF, "CSF", "Command Sequence File", },
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{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
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{-1, "", "", },
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@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = {
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*/
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static table_entry_t imximage_versions[] = {
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{IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", },
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{IMXIMAGE_V2, "", " (i.MX53/6 compatible)", },
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{IMXIMAGE_V2, "", " (i.MX53/6/7 compatible)", },
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{-1, "", " (Invalid)", },
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};
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@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED;
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static uint32_t imximage_init_loadsize;
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static set_dcd_val_t set_dcd_val;
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static set_dcd_param_t set_dcd_param;
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static set_dcd_rst_t set_dcd_rst;
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static set_imx_hdr_t set_imx_hdr;
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static uint32_t max_dcd_entries;
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@ -156,6 +160,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
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}
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}
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static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
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int32_t cmd)
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{
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dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
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switch (cmd) {
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case CMD_WRITE_DATA:
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dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
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dcd_v2->write_dcd_command.length = cpu_to_be16(
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dcd_len * sizeof(dcd_addr_data_t) + 4);
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dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
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break;
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case CMD_WRITE_CLR_BIT:
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dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
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dcd_v2->write_dcd_command.length = cpu_to_be16(
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dcd_len * sizeof(dcd_addr_data_t) + 4);
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dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
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break;
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/*
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* Check data command only supports one entry,
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* so use 0xC = size(address + value + command).
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*/
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case CMD_CHECK_BITS_SET:
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dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
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dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
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dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
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break;
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case CMD_CHECK_BITS_CLR:
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dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
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dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
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dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
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break;
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default:
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break;
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}
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}
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static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
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int fld, uint32_t value, uint32_t off)
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{
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@ -200,10 +241,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
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dcd_v2->header.length = cpu_to_be16(
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dcd_len * sizeof(dcd_addr_data_t) + 8);
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dcd_v2->header.version = DCD_VERSION;
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dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
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dcd_v2->write_dcd_command.length = cpu_to_be16(
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dcd_len * sizeof(dcd_addr_data_t) + 4);
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dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
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set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA);
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}
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static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
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@ -266,12 +304,14 @@ static void set_hdr_func(void)
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switch (imximage_version) {
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case IMXIMAGE_V1:
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set_dcd_val = set_dcd_val_v1;
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set_dcd_param = NULL;
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set_dcd_rst = set_dcd_rst_v1;
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set_imx_hdr = set_imx_hdr_v1;
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max_dcd_entries = MAX_HW_CFG_SIZE_V1;
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break;
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case IMXIMAGE_V2:
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set_dcd_val = set_dcd_val_v2;
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set_dcd_param = set_dcd_param_v2;
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set_dcd_rst = set_dcd_rst_v2;
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set_imx_hdr = set_imx_hdr_v2;
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max_dcd_entries = MAX_HW_CFG_SIZE_V2;
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@ -396,8 +436,13 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
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if (unlikely(cmd_ver_first != 1))
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cmd_ver_first = 0;
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break;
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case CMD_DATA:
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case CMD_WRITE_DATA:
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case CMD_WRITE_CLR_BIT:
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case CMD_CHECK_BITS_SET:
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case CMD_CHECK_BITS_CLR:
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value = get_cfg_value(token, name, lineno);
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if (set_dcd_param)
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(*set_dcd_param)(imxhdr, dcd_len, cmd);
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(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
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if (unlikely(cmd_ver_first != 1))
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cmd_ver_first = 0;
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@ -436,20 +481,30 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
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break;
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case CFG_REG_ADDRESS:
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case CFG_REG_VALUE:
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if (*cmd != CMD_DATA)
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return;
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switch(*cmd) {
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case CMD_WRITE_DATA:
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case CMD_WRITE_CLR_BIT:
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case CMD_CHECK_BITS_SET:
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case CMD_CHECK_BITS_CLR:
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value = get_cfg_value(token, name, lineno);
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(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
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value = get_cfg_value(token, name, lineno);
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if (set_dcd_param)
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(*set_dcd_param)(imxhdr, *dcd_len, *cmd);
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(*set_dcd_val)(imxhdr, name, lineno, fld, value,
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*dcd_len);
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if (fld == CFG_REG_VALUE) {
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(*dcd_len)++;
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if (*dcd_len > max_dcd_entries) {
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fprintf(stderr, "Error: %s[%d] -"
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"DCD table exceeds maximum size(%d)\n",
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name, lineno, max_dcd_entries);
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exit(EXIT_FAILURE);
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if (fld == CFG_REG_VALUE) {
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(*dcd_len)++;
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if (*dcd_len > max_dcd_entries) {
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fprintf(stderr, "Error: %s[%d] -"
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"DCD table exceeds maximum size(%d)\n",
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name, lineno, max_dcd_entries);
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exit(EXIT_FAILURE);
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}
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}
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break;
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default:
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break;
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}
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break;
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default:
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@ -42,19 +42,27 @@
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#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
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#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
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#define IVT_HEADER_TAG 0xD1
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#define IVT_VERSION 0x40
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#define DCD_HEADER_TAG 0xD2
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#define DCD_COMMAND_TAG 0xCC
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#define DCD_VERSION 0x40
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#define DCD_COMMAND_PARAM 0x4
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/* Command tags and parameters */
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#define IVT_HEADER_TAG 0xD1
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#define IVT_VERSION 0x40
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#define DCD_HEADER_TAG 0xD2
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#define DCD_VERSION 0x40
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#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
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#define DCD_WRITE_DATA_PARAM 0x4
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#define DCD_WRITE_CLR_BIT_PARAM 0xC
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#define DCD_CHECK_DATA_COMMAND_TAG 0xCF
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#define DCD_CHECK_BITS_SET_PARAM 0x14
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#define DCD_CHECK_BITS_CLR_PARAM 0x04
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enum imximage_cmd {
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CMD_INVALID,
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CMD_IMAGE_VERSION,
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CMD_BOOT_FROM,
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CMD_BOOT_OFFSET,
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CMD_DATA,
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CMD_WRITE_DATA,
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CMD_WRITE_CLR_BIT,
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CMD_CHECK_BITS_SET,
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CMD_CHECK_BITS_CLR,
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CMD_CSF,
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};
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@ -168,6 +176,9 @@ typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
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int fld, uint32_t value,
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uint32_t off);
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typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
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int32_t cmd);
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typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
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uint32_t dcd_len,
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char *name, int lineno);
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