mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-mips
This commit is contained in:
Wolfgang Denk
commit
0b20335015
14 changed files with 132 additions and 134 deletions
1
MAKEALL
1
MAKEALL
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@ -554,6 +554,7 @@ LIST_mips5kc_el=""
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LIST_au1xx0_el=" \
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dbau1550_el \
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pb1000 \
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"
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LIST_mips_el=" \
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|
|
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@ -54,10 +54,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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|
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@ -54,9 +54,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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|
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@ -54,10 +54,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o
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SOBJS = memsetup.o
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SOBJS = lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -15,8 +15,8 @@
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.set noreorder
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.set mips32
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.globl memsetup
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memsetup:
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Step 1) Establish CPU endian mode.
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* NOTE: A fair amount of code is necessary on the Pb1000 to
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@ -54,9 +54,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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|
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@ -64,10 +64,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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|
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@ -54,10 +54,11 @@ SECTIONS
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.sdata : { *(.sdata) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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.u_boot_cmd : {
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__u_boot_cmd_start = .;
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*(.u_boot_cmd)
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__u_boot_cmd_end = .;
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}
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS];
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#define MAX_WAIT 1000
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#if defined(CONFIG_CMD_MII)
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int au1x00_miiphy_read(char *devname, unsigned char addr,
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unsigned char reg, unsigned short * value)
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{
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
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*mii_control_reg = mii_control;
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timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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*value = *mii_data_reg;
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return 0;
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}
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int au1x00_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_write busy timeout!!\n");
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return -1;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
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*mii_data_reg = value;
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*mii_control_reg = mii_control;
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return 0;
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}
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#endif
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static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
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volatile mac_fifo_t *fifo_tx =
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(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
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@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
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return 1;
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}
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#if defined(CONFIG_CMD_MII)
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int au1x00_miiphy_read(char *devname, unsigned char addr,
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unsigned char reg, unsigned short * value)
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{
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
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*mii_control_reg = mii_control;
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timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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*value = *mii_data_reg;
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return 0;
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}
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int au1x00_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_write busy timeout!!\n");
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return;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
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*mii_data_reg = value;
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*mii_control_reg = mii_control;
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return 0;
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}
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#endif
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#endif /* CONFIG_AU1X00 */
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@ -22,7 +22,6 @@
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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@ -30,13 +29,11 @@
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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/* 16KB is the maximum size of instruction and data caches on
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* MIPS 4K.
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*/
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#define MIPS_MAX_CACHE_SIZE 0x4000
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/*
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* cacheop macro to automate cache operations
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* first some helpers...
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@ -131,7 +128,6 @@ mips_cache_reset:
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li t4, CFG_CACHELINE_SIZE
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move t5, t4
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li v0, MIPS_MAX_CACHE_SIZE
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/* Now clear that much memory starting from zero.
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@ -139,8 +135,8 @@ mips_cache_reset:
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li a0, KSEG1
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addu a1, a0, v0
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2: sw zero, 0(a0)
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2:
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sw zero, 0(a0)
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sw zero, 4(a0)
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sw zero, 8(a0)
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sw zero, 12(a0)
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@ -156,11 +152,11 @@ mips_cache_reset:
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mtc0 zero, CP0_TAGLO
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
|
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* invalidate, load/fill, invalidate for each line.
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*/
|
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/*
|
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* The caches are probably in an indeterminate state,
|
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* so we force good parity into them by doing an
|
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* invalidate, load/fill, invalidate for each line.
|
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*/
|
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/* Assume bottom of RAM will generate good parity for the cache.
|
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*/
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|
@ -201,9 +197,9 @@ mips_cache_reset:
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move a1, a2
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icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
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|
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j ra
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.end mips_cache_reset
|
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j ra
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|
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.end mips_cache_reset
|
||||
|
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/*******************************************************************************
|
||||
*
|
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|
|
@ -220,7 +216,7 @@ dcache_status:
|
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andi v0, v0, 1
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j ra
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|
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.end dcache_status
|
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.end dcache_status
|
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|
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/*******************************************************************************
|
||||
*
|
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|
|
@ -237,11 +233,10 @@ dcache_disable:
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li t1, -8
|
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and t0, t0, t1
|
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ori t0, t0, CONF_CM_UNCACHED
|
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mtc0 t0, CP0_CONFIG
|
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mtc0 t0, CP0_CONFIG
|
||||
j ra
|
||||
|
||||
.end dcache_disable
|
||||
|
||||
.end dcache_disable
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
|
|
@ -266,4 +261,5 @@ mips_cache_lock:
|
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icacheop(a0,a1,a2,a3,0x1d)
|
||||
|
||||
j ra
|
||||
|
||||
.end mips_cache_lock
|
||||
|
|
|
|||
|
|
@ -20,8 +20,7 @@
|
|||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
v=$(shell \
|
||||
$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
|
||||
v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
|
||||
MIPSFLAGS=$(shell \
|
||||
if [ "$v" -lt "14" ]; then \
|
||||
echo "-mcpu=4kc"; \
|
||||
|
|
|
|||
|
|
@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
return 0;
|
||||
}
|
||||
|
||||
void flush_cache (ulong start_addr, ulong size)
|
||||
void flush_cache(ulong start_addr, ulong size)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
|
||||
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
|
||||
{
|
||||
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
|
||||
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
|
||||
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
|
||||
|
|
|
|||
|
|
@ -22,13 +22,11 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
|
||||
#define RVECENT(f,n) \
|
||||
b f; nop
|
||||
#define XVECENT(f,bev) \
|
||||
|
|
@ -192,7 +190,7 @@ _start:
|
|||
.word 0x00000000
|
||||
.word 0x03e00008
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
/* 0xbfc00428 */
|
||||
.word 0xdc870000
|
||||
.word 0xfca70000
|
||||
|
|
@ -203,7 +201,7 @@ _start:
|
|||
.word 0x00000000
|
||||
.word 0x03e00008
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
#endif /* CONFIG_PURPLE */
|
||||
.align 4
|
||||
reset:
|
||||
|
|
@ -235,33 +233,31 @@ reset:
|
|||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
/* Initialize $gp.
|
||||
*/
|
||||
bal 1f
|
||||
*/
|
||||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
move gp, ra
|
||||
lw t1, 0(ra)
|
||||
move gp, t1
|
||||
1:
|
||||
lw gp, 0(ra)
|
||||
|
||||
#ifdef CONFIG_INCA_IP
|
||||
/* Disable INCA-IP Watchdog.
|
||||
*/
|
||||
la t9, disable_incaip_wdt
|
||||
jalr t9
|
||||
la t9, disable_incaip_wdt
|
||||
jalr t9
|
||||
nop
|
||||
#endif
|
||||
|
||||
/* Initialize any external memory.
|
||||
*/
|
||||
la t9, lowlevel_init
|
||||
jalr t9
|
||||
la t9, lowlevel_init
|
||||
jalr t9
|
||||
nop
|
||||
|
||||
/* Initialize caches...
|
||||
*/
|
||||
la t9, mips_cache_reset
|
||||
jalr t9
|
||||
la t9, mips_cache_reset
|
||||
jalr t9
|
||||
nop
|
||||
|
||||
/* ... and enable them.
|
||||
|
|
@ -269,12 +265,11 @@ reset:
|
|||
li t0, CONF_CM_CACHABLE_NONCOHERENT
|
||||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
|
||||
/* Set up temporary stack.
|
||||
*/
|
||||
li a0, CFG_INIT_SP_OFFSET
|
||||
la t9, mips_cache_lock
|
||||
jalr t9
|
||||
la t9, mips_cache_lock
|
||||
jalr t9
|
||||
nop
|
||||
|
||||
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
|
||||
|
|
@ -284,7 +279,6 @@ reset:
|
|||
j t9
|
||||
nop
|
||||
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
|
|
@ -298,7 +292,7 @@ reset:
|
|||
.globl relocate_code
|
||||
.ent relocate_code
|
||||
relocate_code:
|
||||
move sp, a0 /* Set new stack pointer */
|
||||
move sp, a0 /* Set new stack pointer */
|
||||
|
||||
li t0, CFG_MONITOR_BASE
|
||||
la t3, in_ram
|
||||
|
|
@ -312,8 +306,8 @@ relocate_code:
|
|||
*/
|
||||
move t6, gp
|
||||
sub gp, CFG_MONITOR_BASE
|
||||
add gp, a2 /* gp now adjusted */
|
||||
sub t6, gp, t6 /* t6 <-- relocation offset */
|
||||
add gp, a2 /* gp now adjusted */
|
||||
sub t6, gp, t6 /* t6 <-- relocation offset */
|
||||
|
||||
/*
|
||||
* t0 = source address
|
||||
|
|
@ -329,7 +323,7 @@ relocate_code:
|
|||
sw t3, 0(t1)
|
||||
addu t0, 4
|
||||
ble t0, t2, 1b
|
||||
addu t1, 4 /* delay slot */
|
||||
addu t1, 4 /* delay slot */
|
||||
#endif
|
||||
|
||||
/* If caches were enabled, we would have to flush them here.
|
||||
|
|
@ -376,7 +370,8 @@ in_ram:
|
|||
add t2, t6
|
||||
|
||||
sub t1, 4
|
||||
1: addi t1, 4
|
||||
1:
|
||||
addi t1, 4
|
||||
bltl t1, t2, 1b
|
||||
sw zero, 0(t1) /* delay slot */
|
||||
|
||||
|
|
@ -387,11 +382,10 @@ in_ram:
|
|||
|
||||
.end relocate_code
|
||||
|
||||
|
||||
/* Exception handlers.
|
||||
*/
|
||||
romReserved:
|
||||
b romReserved
|
||||
b romReserved
|
||||
|
||||
romExcHandle:
|
||||
b romExcHandle
|
||||
b romExcHandle
|
||||
|
|
|
|||
Loading…
Reference in a new issue