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clk: clk_stm32h7: Fix prescaler for Domain 3

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d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2018-02-07 10:44:48 +01:00 committed by Tom Rini
parent b43679482b
commit 09b335a675
1 changed files with 4 additions and 3 deletions
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7
drivers/clk/clk_stm32h7.c
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@ -635,7 +635,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
struct stm32_rcc_regs *regs = priv->rcc_base;
ulong sysclk = 0;
u32 gate_offset;
u32 d1cfgr;
u32 d1cfgr, d3cfgr;
/* prescaler table lookups for clock computation */
u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
u8 source, idx;
@ -712,9 +712,10 @@ static ulong stm32_clk_get_rate(struct clk *clk)
break;
case RCC_APB4ENR:
if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
d3cfgr = readl(&regs->d3cfgr);
if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
/* get D3 domain APB4 prescaler */
idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
RCC_D3CFGR_D3PPRE_SHIFT;
sysclk = sysclk / prescaler_table[idx];
}