Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 23:24:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

Browse source
This commit is contained in:
Wolfgang Denk 2008-03-02 21:46:20 +01:00
commit 093e14c522
4 changed files with 19 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
board/sbc8548/sbc8548.c
View file

@ -56,9 +56,10 @@ int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
volatile u_char *rev= (void *)CFG_BD_REV;
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
(volatile)(*(u_char *)CFG_BD_REV) >> 4);
(*rev) >> 4);
/*
* Initialize local bus.
@ -533,12 +534,12 @@ void
ft_pci_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
const char *path;
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
@ -546,6 +547,7 @@ ft_pci_setup(void *blob, bd_t *bd)
}
#endif
#ifdef CONFIG_PCIE1
const char *path;
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;

2
cpu/mpc85xx/interrupts.c
View file

@ -91,7 +91,7 @@ int interrupt_init (void)
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */

18
cpu/mpc85xx/start.S
View file

@ -992,7 +992,6 @@ trap_reloc:
blr
#ifdef CFG_INIT_RAM_LOCK
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
@ -1002,11 +1001,20 @@ unlock_ram_in_cache:
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: icbi r0,r3
dcbi r0,r3
1: dcbi r0,r3
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
sync /* Wait for all icbi to complete on bus */
sync
/* Invalidate the TLB entries for the cache */
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
isync
blr
#endif

2
include/configs/sbc8548.h
View file

@ -168,7 +168,7 @@
#define CFG_OR0_PRELIM 0xff806e65
#define CFG_OR6_PRELIM 0xfc006e65
#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM