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arm: Remove snapper9260 board

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This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-08-02 07:33:29 -04:00
parent 7751f54f91
commit 08f80184a9
8 changed files with 0 additions and 387 deletions
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10
arch/arm/mach-at91/Kconfig
View file

@ -79,15 +79,6 @@ config TARGET_ETHERNUT5
bool "Ethernut5 board"
select AT91SAM9XE
config TARGET_SNAPPER9260
bool "Support snapper9260"
select AT91SAM9260
select AT91_WANTS_COMMON_PHY
select DM
select DM_GPIO
select DM_SERIAL
imply CMD_DM
config TARGET_GURNARD
bool "Support gurnard"
select AT91SAM9G45
@ -364,7 +355,6 @@ source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bluewater/gurnard/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"

12
board/bluewater/snapper9260/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_SNAPPER9260
config SYS_BOARD
default "snapper9260"
config SYS_VENDOR
default "bluewater"
config SYS_CONFIG_NAME
default "snapper9260"
endif

7
board/bluewater/snapper9260/MAINTAINERS
View file

@ -1,7 +0,0 @@
SNAPPER9260 BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/bluewater/snapper9260/
F: include/configs/snapper9260.h
F: configs/snapper9260_defconfig
F: configs/snapper9g20_defconfig

9
board/bluewater/snapper9260/Makefile
View file

@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2011 Bluewater Systems
# Ryan Mallon <ryan@bluewatersys.com>
obj-y += snapper9260.o

154
board/bluewater/snapper9260/snapper9260.c
View file

@ -1,154 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Bluewater Systems Snapper 9260/9G20 modules
*
* (C) Copyright 2011 Bluewater Systems
* Author: Andre Renaud <andre@bluewatersys.com>
* Author: Ryan Mallon <ryan@bluewatersys.com>
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/atmel_serial.h>
#include <net.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
/* IO Expander pins */
#define IO_EXP_ETH_RESET (0 << 1)
#define IO_EXP_ETH_POWER (1 << 1)
static void macb_hw_init(void)
{
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
at91_periph_clk_enable(ATMEL_ID_EMAC0);
/* Disable pull-ups to prevent PHY going into test mode */
writel(pin_to_mask(AT91_PIN_PA14) |
pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA18),
&pioa->pudr);
/* Power down ethernet */
pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
/* Hold ethernet in reset */
pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
/* Enable ethernet power */
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
at91_phy_reset();
/* Bring the ethernet out of reset */
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
/* The phy internal reset take 21ms */
udelay(21 * 1000);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |
pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA18),
&pioa->puer);
at91_macb_hw_init();
}
static void nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Enable CS3 as NAND/SmartMedia */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
/* Configure RDY/BSY */
gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
int board_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* The mach-type is the same for both Snapper 9260 and 9G20 */
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Initialise peripherals */
at91_seriald_hw_init();
i2c_set_bus_num(0);
nand_hw_init();
macb_hw_init();
return 0;
}
int board_eth_init(struct bd_info *bis)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
void reset_phy(void)
{
}
static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DRVINFO(at91sam9260_serial) = {
.name = "serial_atmel",
.plat = &at91sam9260_serial_plat,
};

58
configs/snapper9260_defconfig
View file

@ -1,58 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_TARGET_SNAPPER9260=y
CONFIG_AT91_GPIO_PULLUP=y
CONFIG_ATMEL_LEGACY=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Snapper> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RETRY_COUNT=20
CONFIG_TFTP_PORT=y
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_MACB=y
CONFIG_RMII=y
CONFIG_ATMEL_USART=y

57
configs/snapper9g20_defconfig
View file

@ -1,57 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_TARGET_SNAPPER9260=y
CONFIG_AT91_GPIO_PULLUP=y
CONFIG_ATMEL_LEGACY=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RETRY_COUNT=20
CONFIG_TFTP_PORT=y
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_MACB=y
CONFIG_RMII=y
CONFIG_ATMEL_USART=y

80
include/configs/snapper9260.h
View file

@ -1,80 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Bluewater Systems Snapper 9260 and 9G20 modules
*
* (C) Copyright 2011 Bluewater Systems
* Author: Andre Renaud <andre@bluewatersys.com>
* Author: Ryan Mallon <ryan@bluewatersys.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
#include <linux/sizes.h>
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Mem test settings */
/* NAND Flash */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* GPIOs and IO expander */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
/* UARTs/Serial console */
#ifndef CONFIG_DM_SERIAL
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#endif
/* I2C - Bit-bashed */
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define I2C_INIT do { \
at91_set_gpio_output(AT91_PIN_PA23, 1); \
at91_set_gpio_output(AT91_PIN_PA24, 1); \
at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
} while (0)
#define I2C_SOFT_DECLARATIONS
#define I2C_ACTIVE
#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
#define I2C_SDA(bit) do { \
if (bit) { \
at91_set_gpio_input(AT91_PIN_PA23, 1); \
} else { \
at91_set_gpio_output(AT91_PIN_PA23, 1); \
at91_set_gpio_value(AT91_PIN_PA23, bit); \
} \
} while (0)
#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_DELAY udelay(2)
/* Boot options */
/* Environment settings */
/* Console settings */
#endif /* __CONFIG_H */