Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-02-18 15:08:59 +00:00
Code Issues Projects Releases Packages Wiki Activity

mx5 clocks: Fix get_uart_clk()

Browse source 
This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.

This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:23:23 +00:00 • committed by Tom Rini
parent f124e718f4
commit 08028b113e
1 changed files with 26 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -331,27 +331,39 @@ static u32 get_ipg_per_clk(void)
return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
} }
/* Get the output clock rate of a standard PLL MUX for peripherals. */
static u32 get_standard_pll_sel_clk(u32 clk_sel)
{
u32 freq;
switch (clk_sel & 0x3) {
case 0:
freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
break;
case 1:
freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
break;
case 2:
freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
break;
case 3:
freq = get_lp_apm();
break;
}
return freq;
}
/* /*
* Get the rate of uart clk. * Get the rate of uart clk.
*/ */
static u32 get_uart_clk(void) static u32 get_uart_clk(void)
{ {
unsigned int freq, reg, pred, podf; unsigned int clk_sel, freq, reg, pred, podf;
reg = readl(&mxc_ccm->cscmr1); reg = readl(&mxc_ccm->cscmr1);
switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) { clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
case 0x0: freq = get_standard_pll_sel_clk(clk_sel);
freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
break;
default:
return 66500000;
}
reg = readl(&mxc_ccm->cscdr1); reg = readl(&mxc_ccm->cscdr1);
pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg); pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);