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https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
pci: Refactor the pciinfo() function
This function uses macros to output data. It seems better to use a table of registers rather than macro-based code generation. It also reduces the code/data size by 2KB on ARM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
parent
ca7de76d8c
commit
07a588704c
1 changed files with 148 additions and 89 deletions
237
common/cmd_pci.c
237
common/cmd_pci.c
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@ -131,6 +131,145 @@ void pci_header_show_brief(pci_dev_t dev)
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pci_class_str(class), subclass);
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}
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struct pci_reg_info {
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const char *name;
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enum pci_size_t size;
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u8 offset;
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};
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static int pci_field_width(enum pci_size_t size)
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{
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switch (size) {
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case PCI_SIZE_8:
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return 2;
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case PCI_SIZE_16:
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return 4;
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case PCI_SIZE_32:
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default:
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return 8;
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}
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}
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static unsigned long pci_read_config(pci_dev_t dev, int offset,
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enum pci_size_t size)
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{
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u32 val32;
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u16 val16;
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u8 val8;
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switch (size) {
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case PCI_SIZE_8:
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pci_read_config_byte(dev, offset, &val8);
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return val8;
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case PCI_SIZE_16:
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pci_read_config_word(dev, offset, &val16);
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return val16;
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case PCI_SIZE_32:
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default:
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pci_read_config_dword(dev, offset, &val32);
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return val32;
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}
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}
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static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
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{
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for (; regs->name; regs++) {
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printf(" %s =%*s%#.*lx\n", regs->name,
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(int)(28 - strlen(regs->name)), "",
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pci_field_width(regs->size),
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pci_read_config(dev, regs->offset, regs->size));
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}
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}
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static struct pci_reg_info regs_start[] = {
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{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
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{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
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{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
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{ "status register", PCI_SIZE_16, PCI_STATUS },
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{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
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{},
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};
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static struct pci_reg_info regs_rest[] = {
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{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
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{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
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{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
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{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
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{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
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{ "BIST", PCI_SIZE_8, PCI_BIST },
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{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
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{},
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};
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static struct pci_reg_info regs_normal[] = {
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{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
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{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
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{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
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{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
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{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
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{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
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{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
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{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
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{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
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{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
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{},
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};
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static struct pci_reg_info regs_bridge[] = {
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{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
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{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
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{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
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{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
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{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
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{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
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{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
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{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
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{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
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{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
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{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
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{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
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{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
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{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
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{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
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{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
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{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
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{},
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};
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static struct pci_reg_info regs_cardbus[] = {
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{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
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{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
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{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
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{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
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{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
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{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
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{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
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{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
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{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
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{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
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{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
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{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
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{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
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{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
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{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
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{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
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{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
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{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
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{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
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{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
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{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
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{},
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};
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/*
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* Subroutine: PCI_Header_Show
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*
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@ -143,111 +282,31 @@ void pci_header_show_brief(pci_dev_t dev)
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*/
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void pci_header_show(pci_dev_t dev)
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{
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u8 _byte, header_type;
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u16 _word;
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u32 _dword;
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#define PRINT(msg, type, reg) \
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pci_read_config_##type(dev, reg, &_##type); \
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printf(msg, _##type)
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#define PRINT2(msg, type, reg, func) \
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pci_read_config_##type(dev, reg, &_##type); \
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printf(msg, _##type, func(_##type))
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u8 class, header_type;
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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pci_show_regs(dev, regs_start);
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PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
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PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
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PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
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PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
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PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
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PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
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pci_class_str);
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PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
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PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
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PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
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PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
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PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
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PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
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PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
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pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
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printf(" class code = 0x%.2x (%s)\n", class,
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pci_class_str(class));
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pci_show_regs(dev, regs_rest);
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switch (header_type & 0x03) {
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case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
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PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
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PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
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PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
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PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
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PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
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PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
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PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
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PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
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PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
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PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
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pci_show_regs(dev, regs_normal);
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
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PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
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PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
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PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
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PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
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PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
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PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
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PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
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PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
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PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
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PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
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PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
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PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
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PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
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PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
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PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
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PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
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PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
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pci_show_regs(dev, regs_bridge);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
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PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
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PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
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PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
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PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
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PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
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PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
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PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
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PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
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PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
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PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
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PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
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PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
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PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
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PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
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PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
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PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
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PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
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PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
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PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
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PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
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PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
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pci_show_regs(dev, regs_cardbus);
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break;
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default:
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printf("unknown header\n");
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break;
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}
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#undef PRINT
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#undef PRINT2
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}
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/* Convert the "bus.device.function" identifier into a number.
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