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https://github.com/AsahiLinux/u-boot
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ARC: Switch to generic accessors
First of all U-Boot is not that performance oriented as real run-time software like OS or user bare-metal app so we may afford being not super fast as we only being executed once. That in return allows us to be more universal and support wider variety of devices. And looking forward that will significantly reduce maintenance and simplify support of newer architectures. And while at it we add quad-word accessors like readq(), writeq() etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
Alexey Brodkin
parent
c77bbc2215
commit
07906b3dad
1 changed files with 79 additions and 133 deletions
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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* Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
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*/
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#ifndef __ASM_ARC_IO_H
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@ -54,134 +54,97 @@ static inline void sync(void)
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/* Not yet implemented */
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}
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 b;
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#define __arch_getb(a) (*(unsigned char *)(a))
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#define __arch_getw(a) (*(unsigned short *)(a))
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#define __arch_getl(a) (*(unsigned int *)(a))
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#define __arch_getq(a) (*(unsigned long long *)(a))
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__asm__ __volatile__("ldb%U1 %0, %1\n"
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: "=r" (b)
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: "m" (*(volatile u8 __force *)addr)
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: "memory");
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return b;
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#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
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#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
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#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
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#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
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#define __raw_writeb(v, a) __arch_putb(v, a)
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#define __raw_writew(v, a) __arch_putw(v, a)
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#define __raw_writel(v, a) __arch_putl(v, a)
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#define __raw_writeq(v, a) __arch_putq(v, a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readq(a) __arch_getq(a)
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static inline void __raw_writesb(unsigned long addr, const void *data,
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int bytelen)
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{
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u8 *buf = (uint8_t *)data;
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while (bytelen--)
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__arch_putb(*buf++, addr);
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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static inline void __raw_writesw(unsigned long addr, const void *data,
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int wordlen)
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{
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u16 s;
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u16 *buf = (uint16_t *)data;
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__asm__ __volatile__("ldw%U1 %0, %1\n"
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: "=r" (s)
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: "m" (*(volatile u16 __force *)addr)
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: "memory");
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return s;
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while (wordlen--)
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__arch_putw(*buf++, addr);
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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static inline void __raw_writesl(unsigned long addr, const void *data,
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int longlen)
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{
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u32 w;
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u32 *buf = (uint32_t *)data;
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__asm__ __volatile__("ld%U1 %0, %1\n"
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: "=r" (w)
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: "m" (*(volatile u32 __force *)addr)
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: "memory");
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return w;
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while (longlen--)
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__arch_putl(*buf++, addr);
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}
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
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{
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__asm__ __volatile__("stb%U1 %0, %1\n"
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:
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: "r" (b), "m" (*(volatile u8 __force *)addr)
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: "memory");
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u8 *buf = (uint8_t *)data;
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while (bytelen--)
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*buf++ = __arch_getb(addr);
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}
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static inline void __raw_writew(u16 s, volatile void __iomem *addr)
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static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
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{
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__asm__ __volatile__("stw%U1 %0, %1\n"
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:
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: "r" (s), "m" (*(volatile u16 __force *)addr)
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: "memory");
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u16 *buf = (uint16_t *)data;
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while (wordlen--)
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*buf++ = __arch_getw(addr);
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}
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static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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{
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__asm__ __volatile__("st%U1 %0, %1\n"
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:
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: "r" (w), "m" (*(volatile u32 __force *)addr)
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: "memory");
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u32 *buf = (uint32_t *)data;
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while (longlen--)
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*buf++ = __arch_getl(addr);
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}
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static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stb.ab r8, [r1, 1]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
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__raw_readq(c)); __r; })
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static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stw.ab r8, [r1, 2]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab r8, [r1, 4]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
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cpu_to_le16(v), (c)))
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#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v), (c)))
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#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
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cpu_to_le64(v), (c)))
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/*
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* MMIO can also get buffered/optimized in micro-arch, so barriers needed
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@ -195,32 +158,15 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
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*
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* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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/*
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* Relaxed API for drivers which can handle barrier ordering themselves
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*
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* Also these are defined to perform little endian accesses.
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* To provide the typical device register semantics of fixed endian,
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* swap the byte order for Big Endian
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*
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* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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#define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); })
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#define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); })
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#define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); })
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#define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); })
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#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
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#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
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