diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e935c60bd7..d692139199 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1801,7 +1801,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if SPL_OPTEE + select BINMAN if SPL_OPTEE || (SPL && !ARM64) select DM select DM_GPIO select DM_I2C diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index b6c79e7ed3..aaa8ae2235 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -960,6 +960,18 @@ status = "disabled"; }; + sfc: sfc@ff3a0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-names = "default"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + gpu: gpu@ff400000 { compatible = "rockchip,px30-mali", "arm,mali-bifrost"; reg = <0x0 0xff400000 0x0 0x4000>; @@ -1926,6 +1938,32 @@ }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>, + <1 RK_PA2 3 &pcfg_pull_none>, + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs: sfc-cs { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + }; + lcdc { lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { rockchip,pins = diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 204bb3a90e..9c9016de1b 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -5,12 +5,36 @@ #include "rk3188-u-boot.dtsi" +/ { + chosen { +/* stdout-path = &uart2; */ + stdout-path = "serial2:115200n8"; + }; + + config { + u-boot,boot-led = "rock:red:power"; + u-boot,dm-pre-reloc; + }; +}; + &cru { u-boot,dm-spl; }; -&pinctrl { - u-boot,dm-spl; +&dmc { + rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 + 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 + 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 + 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 + 0x4 0x0>; + rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 + 0x220 0x40 0x0 0x0>; + rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; +}; + +&emmc { + fifo-mode; + max-frequency = <16000000>; }; &mmc0 { @@ -23,18 +47,16 @@ max-frequency = <16000000>; }; -&emmc { - fifo-mode; - max-frequency = <16000000>; -}; - -&uart2 { - status = "okay"; +&pinctrl { u-boot,dm-spl; }; &timer3 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; - u-boot,dm-spl; clock-frequency = <24000000>; + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 61367126ba..e7138a4ae0 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 Heiko Stuebner */ @@ -12,17 +12,11 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188"; - chosen { -/* stdout-path = &uart2; */ - stdout-path = "serial2:115200n8"; + aliases { + mmc0 = &mmc0; }; - config { - u-boot,dm-pre-reloc; - u-boot,boot-led = "rock:red:power"; - }; - - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; @@ -32,7 +26,7 @@ autorepeat; power { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; @@ -44,21 +38,21 @@ gpio-leds { compatible = "gpio-leds"; - green { + green_led: led-0 { label = "rock:green:user1"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blue { + blue_led: led-1 { label = "rock:blue:user2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sleep { + sleep_led: led-2 { label = "rock:red:power"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; @@ -80,7 +74,7 @@ ir_recv: gpio-ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio0 10 1>; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_recv_pin>; }; @@ -88,7 +82,7 @@ vcc_otg: usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&otg_vbus_drv>; regulator-name = "otg-vbus"; @@ -103,7 +97,7 @@ regulator-name = "sdmmc-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_pwr>; startup-delay-us = <100000>; @@ -113,7 +107,7 @@ vcc_host: usb-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "host-pwr"; @@ -132,17 +126,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 - 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 - 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 - 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 - 0x4 0x0>; - rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 - 0x220 0x40 0x0 0x0>; - rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; -}; - &emac { status = "okay"; @@ -155,12 +138,28 @@ phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + status = "okay"; }; &i2c1 { @@ -171,7 +170,7 @@ compatible = "haoyu,hym8563"; reg = <0x51>; interrupt-parent = <&gpio0>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&rtc_int>; #clock-cells = <0>; @@ -283,7 +282,6 @@ }; &mmc0 { - num-slots = <1>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; @@ -314,40 +312,40 @@ act8846 { act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = ; + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; }; }; hym8563 { rtc_int: rtc-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; lan8720a { phy_int: phy-int { - rockchip,pins = ; + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; ir-receiver { ir_recv_pin: ir-recv-pin { - rockchip,pins = ; + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sd0 { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -364,6 +362,10 @@ status = "okay"; }; +&uart2 { + status = "okay"; +}; + &uart3 { status = "okay"; }; diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 41ac054b81..43f05b9876 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -4,3 +4,16 @@ */ #include "rockchip-u-boot.dtsi" + +&global_timer { + status = "okay"; +}; + +&gpio0 { + compatible = "rockchip,gpio-bank"; +}; + +&pmu { + compatible = "rockchip,rk3188-pmu", "syscon", "simple-mfd"; +}; + diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 7bcca6a02d..6c1c2ff533 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner @@ -7,7 +7,9 @@ #include #include #include +#include #include "rk3xxx.dtsi" +#include "rk3xxx-u-boot.dtsi" / { compatible = "rockchip,rk3188"; @@ -22,40 +24,82 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - operating-points = < - /* kHz uV */ - 1608000 1350000 - 1416000 1250000 - 1200000 1150000 - 1008000 1075000 - 816000 975000 - 600000 950000 - 504000 925000 - 312000 875000 - >; clock-latency = <40000>; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x1>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x2>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x3>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE3>; }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <875000>; + clock-latency-ns = <40000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <925000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + opp-suspend; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1075000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; @@ -69,20 +113,69 @@ }; }; + vop0: vop@1010c000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010c000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010e000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; + clock-names = "pclk", "timer"; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; + clock-names = "pclk", "timer"; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 6>, <&dmac1_s 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -90,8 +183,8 @@ compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; reg = <0x1011e000 0x2000>; #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; dmas = <&dmac1_s 8>; dma-names = "tx"; interrupts = ; @@ -110,7 +203,7 @@ }; efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3188-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; @@ -122,36 +215,6 @@ }; }; - timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = ; - }; - - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -162,7 +225,7 @@ ranges; gpio0: gpio0@2000a000 { - compatible = "rockchip,gpio-bank"; + compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO0>; @@ -227,15 +290,15 @@ emmc { emmc_clk: emmc-clk { - rockchip,pins = ; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = ; + rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; }; emmc_rst: emmc-rst { - rockchip,pins = ; + rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; }; /* @@ -248,246 +311,291 @@ emac { emac_xfer: emac-xfer { - rockchip,pins = , /* tx_en */ - , /* txd1 */ - , /* txd0 */ - , /* rxd0 */ - , /* rxd1 */ - , /* mac_clk */ - , /* rx_err */ - ; /* crs_dvalid */ + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ + <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ + <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ + <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ + <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ + <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ + <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ + <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ }; emac_mdio: emac-mdio { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = , - ; + rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, + <3 RK_PB7 2 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + lcdc1 { + lcdc1_dclk: lcdc1-dclk { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; + }; + + lcdc1_den: lcdc1-den { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; + }; + + lcdc1_hsync: lcdc1-hsync { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; + }; + + lcdc1_vsync: lcdc1-vsync { + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; + }; + + lcdc1_rgb24: ldcd1-rgb24 { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_none>, + <2 RK_PA2 1 &pcfg_pull_none>, + <2 RK_PA3 1 &pcfg_pull_none>, + <2 RK_PA4 1 &pcfg_pull_none>, + <2 RK_PA5 1 &pcfg_pull_none>, + <2 RK_PA6 1 &pcfg_pull_none>, + <2 RK_PA7 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB1 1 &pcfg_pull_none>, + <2 RK_PB2 1 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_out: pwm0-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_out: pwm1-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_out: pwm2-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; }; }; pwm3 { pwm3_out: pwm3-out { - rockchip,pins = ; + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = ; + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = ; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = ; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = ; + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = ; + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = ; + rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = ; + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, + <1 RK_PA1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, + <1 RK_PA5 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, + <1 RK_PB1 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, + <1 RK_PB3 1 &pcfg_pull_none>; }; uart3_cts: uart3-cts { - rockchip,pins = ; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; }; uart3_rts: uart3-rts { - rockchip,pins = ; + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; }; }; sd0 { sd0_clk: sd0-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; }; sd0_cmd: sd0-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; sd0_cd: sd0-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; }; sd0_wp: sd0-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; }; sd0_pwr: sd0-pwr { - rockchip,pins = ; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; }; sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; }; sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>; }; }; sd1 { sd1_clk: sd1-clk { - rockchip,pins = ; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; sd1_cmd: sd1-cmd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; }; sd1_cd: sd1-cd { - rockchip,pins = ; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; }; sd1_wp: sd1-wp { - rockchip,pins = ; + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; }; sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; }; sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = , - , - , - , - , - ; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>, + <1 RK_PC2 1 &pcfg_pull_none>, + <1 RK_PC3 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>, + <1 RK_PC5 1 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx { - rockchip,pins = ; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; }; }; }; @@ -498,15 +606,65 @@ }; &global_timer { - interrupts = ; -}; - -&grf { - compatible = "rockchip,rk3188-grf", "syscon"; + interrupts = ; + status = "disabled"; }; &local_timer { - interrupts = ; + interrupts = ; +}; + +&gpu { + compatible = "rockchip,rk3188-mali", "arm,mali-400"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3188_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3188-usb-phy", + "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@11c { + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; }; &i2c0 { @@ -540,7 +698,52 @@ }; &pmu { - compatible = "rockchip,rk3188-pmu", "syscon"; + power: power-controller { + compatible = "rockchip,rk3188-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3188_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; }; &pwm0 { @@ -599,6 +802,11 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 00767d2abd..741e8dd935 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -7,6 +7,15 @@ chosen { u-boot,spl-boot-order = &sdmmc; }; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdmmc; + serial1 = &uart1; + serial2 = &uart2; + spi0 = &sfc; + }; }; &cru { @@ -57,6 +66,14 @@ u-boot,spl-fifo-mode; }; +&sfc { + u-boot,dm-pre-reloc; +}; + +&spi_flash { + u-boot,dm-pre-reloc; +}; + &uart1 { clock-frequency = <24000000>; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts index 8cd4688c49..6f91f5040b 100644 --- a/arch/arm/dts/rk3326-odroid-go2.dts +++ b/arch/arm/dts/rk3326-odroid-go2.dts @@ -617,6 +617,22 @@ status = "okay"; }; +&sfc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; + status = "okay"; + + spi_flash: xt25f128b@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &tsadc { status = "okay"; }; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 6abc6f4a86..ff6b466e0e 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -10,6 +10,12 @@ model = "Rockchip RK3328 EVB"; compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -41,7 +47,7 @@ compatible = "regulator-fixed"; gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-0 = <&sdmmc0m1_pin>; regulator-name = "vcc_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -70,6 +76,18 @@ cpu-supply = <&vdd_arm>; }; +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -82,11 +100,10 @@ &gmac2phy { phy-supply = <&vcc_phy>; clock_in_out = "output"; - assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; assigned-clock-rate = <50000000>; assigned-clocks = <&cru SCLK_MAC2PHY>; assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - + status = "okay"; }; &i2c1 { diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 9e2ced1541..8db5e55af6 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -20,7 +20,7 @@ u-boot,dm-spl; }; -&sdmmc0m1_gpio { +&sdmmc0m1_pin { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts index 5445c5cb3d..3857d487ab 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -13,6 +13,11 @@ model = "FriendlyElec NanoPi R2S"; compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -50,6 +55,7 @@ sys_led: led-1 { gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; label = "nanopi-r2s:red:sys"; + default-state = "on"; }; wan_led: led-2 { @@ -71,15 +77,15 @@ regulator-settling-time-us = <5000>; regulator-type = "voltage"; startup-delay-us = <2000>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; vin-supply = <&vcc_io_33>; }; vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-0 = <&sdmmc0m1_pin>; pinctrl-names = "default"; regulator-name = "vcc_sd"; regulator-boot-on; @@ -96,6 +102,18 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_5v_lan: vdd-5v-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; }; &cpu0 { @@ -114,6 +132,10 @@ cpu-supply = <&vdd_arm>; }; +&display_subsystem { + status = "disabled"; +}; + &gmac2io { assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; @@ -134,8 +156,6 @@ #size-cells = <0>; rtl8211e: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c915", - "ethernet-phy-ieee802.3-c22"; reg = <1>; pinctrl-0 = <ð_phy_reset_pin>; pinctrl-names = "default"; @@ -282,7 +302,7 @@ }; }; - ethernet-phy { + gmac2io { eth_phy_reset_pin: eth-phy-reset-pin { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; }; @@ -302,6 +322,12 @@ }; }; + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; @@ -361,6 +387,19 @@ dr_mode = "host"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + }; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 08806dfc0f..20a62134a0 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -40,7 +40,7 @@ u-boot,dm-spl; }; -&sdmmc0m1_gpio { +&sdmmc0m1_pin { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts index 8d553c9218..aa22a0c222 100644 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -10,6 +10,11 @@ model = "Firefly roc-rk3328-cc"; compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -34,7 +39,7 @@ compatible = "regulator-fixed"; gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-0 = <&sdmmc0m1_pin>; regulator-boot-on; regulator-name = "vcc_sd"; regulator-min-microvolt = <3300000>; @@ -45,8 +50,8 @@ vcc_sdio: sdmmcio-regulator { compatible = "regulator-gpio"; gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; regulator-name = "vcc_sdio"; regulator-type = "voltage"; regulator-min-microvolt = <1800000>; @@ -86,7 +91,7 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { label = "firefly:blue:power"; linux,default-trigger = "heartbeat"; gpios = <&rk805 1 GPIO_ACTIVE_LOW>; @@ -94,7 +99,7 @@ mode = <0x23>; }; - user { + user_led: led-1 { label = "firefly:yellow:user"; linux,default-trigger = "mmc1"; gpios = <&rk805 0 GPIO_ACTIVE_LOW>; @@ -104,6 +109,14 @@ }; }; +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -161,6 +174,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -270,6 +287,14 @@ }; }; +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + &io_domains { status = "okay"; @@ -334,6 +359,12 @@ }; &usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd3 { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 4fc055eacb..9d557eb988 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -37,7 +37,7 @@ u-boot,dm-spl; }; -&sdmmc0m1_gpio { +&sdmmc0m1_pin { u-boot,dm-spl; }; @@ -46,7 +46,7 @@ }; &usb_host0_xhci { - vbus-supply = <&vcc5v0_host_xhci>; + vbus-supply = <&vcc_host_5v>; status = "okay"; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts index 4b9f9a8248..018a3a5075 100644 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ b/arch/arm/dts/rk3328-rock-pi-e.dts @@ -1,56 +1,116 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2020 Radxa + * (C) Copyright 2020 Chen-Yu Tsai + * + * Based on ./rk3328-rock64.dts, which is + * + * Copyright (c) 2017 PINE64 */ /dts-v1/; + +#include +#include +#include +#include + #include "rk3328.dtsi" / { - model = "Radxa Rockpi E"; - compatible = "radxa,rock-pi-e", "rockchip,rk3328"; + model = "Radxa ROCK Pi E"; + compatible = "radxa,rockpi-e", "rockchip,rk3328"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; chosen { - stdout-path = "serial2:1500000n8"; + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + + /* This button is unpopulated out of the factory. */ + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; }; gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pin>; + pinctrl-names = "default"; + + led-0 { + color = ; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; }; vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-name = "vcc_sd"; + regulator-boot-on; + vin-supply = <&vcc_io>; }; - vcc5v0_host_xhci: vcc5v0-host-xhci-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_host_xhci"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + enable-active-high; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; }; vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; + + vcc_wifi: vcc-wifi-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en>; + regulator-name = "vcc_wifi"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; +}; + +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; }; &cpu0 { @@ -72,13 +132,11 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; mmc-hs200-1_8v; - supports-emmc; - disable-wp; non-removable; - num-slots = <1>; pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; vmmc-supply = <&vcc_io>; vqmmc-supply = <&vcc18_emmc>; status = "okay"; @@ -88,165 +146,233 @@ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; clock_in_out = "input"; - phy-supply = <&vcc_io>; + phy-handle = <&rtl8211e>; phy-mode = "rgmii"; + phy-supply = <&vcc_io>; pinctrl-names = "default"; pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; + snps,aal; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; tx_delay = <0x26>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac2phy { + status = "okay"; }; &i2c1 { status = "okay"; - rk805: rk805@18 { - compatible = "rockchip,rk805"; - status = "okay"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; }; }; -&io_domains { +&i2s1 { status = "okay"; +}; +&io_domains { + pmuio-supply = <&vcc_io>; vccio1-supply = <&vcc_io>; vccio2-supply = <&vcc18_emmc>; vccio3-supply = <&vcc_io>; vccio4-supply = <&vcc_io>; vccio5-supply = <&vcc_io>; vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; + status = "okay"; }; &pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + ephy { + eth_phy_int_pin: eth-phy-int-pin { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; + + leds { + led_pin: led-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_en: wifi-en { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; &sdmmc { bus-width = <4>; - cap-mmc-highspeed; cap-sd-highspeed; - card-detect-delay = <200>; disable-wp; - max-frequency = <150000000>; - num-slots = <1>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - supports-sd; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; vmmc-supply = <&vcc_sd>; status = "okay"; }; &saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { status = "okay"; }; @@ -254,14 +380,11 @@ status = "okay"; }; -&usb20_otg { +&usbdrd3 { + dr_mode = "host"; status = "okay"; }; &usb_host0_ehci { status = "okay"; }; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 2af32aea05..3c3b1370e3 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -40,7 +40,7 @@ u-boot,dm-spl; }; -&sdmmc0m1_gpio { +&sdmmc0m1_pin { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index ebf3eb222e..1b0f7e4551 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -10,6 +10,11 @@ model = "Pine64 Rock64"; compatible = "pine64,rock64", "rockchip,rk3328"; + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -25,7 +30,7 @@ compatible = "regulator-fixed"; gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-0 = <&sdmmc0m1_pin>; regulator-name = "vcc_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -73,45 +78,43 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&rk805 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; - standby { + standby_led: led-1 { gpios = <&rk805 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; }; - sound { - compatible = "audio-graph-card"; - label = "rockchip,rk3328"; - dais = <&i2s1_p0 - &spdif_p0>; - }; + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; - spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; + simple-audio-card,codec { + sound-dai = <&spdif_dit>; }; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; +}; + +&analog_sound { + status = "okay"; }; &codec { mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; status = "okay"; - - port@0 { - codec_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; }; &cpu0 { @@ -163,6 +166,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &hdmiphy { status = "okay"; }; @@ -278,16 +285,12 @@ }; }; +&i2s0 { + status = "okay"; +}; + &i2s1 { status = "okay"; - - i2s1_p0: port { - i2s1_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&codec_p0_0>; - }; - }; }; &io_domains { @@ -337,12 +340,6 @@ &spdif { pinctrl-0 = <&spdifm0_tx>; status = "okay"; - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; }; &spi0 { @@ -384,6 +381,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 945387e579..27e45d5886 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -142,23 +142,6 @@ }; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac: dmac@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - }; - analog_sound: analog-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -305,7 +288,7 @@ status = "disabled"; }; - grf_gpio: grf-gpio { + grf_gpio: gpio { compatible = "rockchip,rk3328-grf-gpio"; gpio-controller; #gpio-cells = <2>; @@ -317,15 +300,18 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = ; + #power-domain-cells = <0>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = ; + #power-domain-cells = <0>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + #power-domain-cells = <0>; }; }; @@ -452,7 +438,7 @@ }; wdt: watchdog@ff1a0000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; reg = <0x0 0xff1a0000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_WDT>; @@ -503,6 +489,17 @@ status = "disabled"; }; + dmac: dmac@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + thermal-zones { soc_thermal: soc-thermal { polling-delay-passive = <20>; @@ -552,9 +549,9 @@ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; rockchip,grf = <&grf>; @@ -822,7 +819,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rk3328-usb2phy"; reg = <0x100 0x10>; clocks = <&xin24m>; @@ -922,11 +919,12 @@ "mac_clk_tx", "clk_mac_ref", "aclk_mac", "pclk_mac", "clk_macphy"; - resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; - reset-names = "stmmaceth", "mac-phy"; + resets = <&cru SRST_GMAC2PHY_A>; + reset-names = "stmmaceth"; phy-mode = "rmii"; phy-handle = <&phy>; snps,txpbl = <0x4>; + clock_in_out = "output"; status = "disabled"; mdio { @@ -934,7 +932,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; reg = <0>; clocks = <&cru SCLK_MAC2PHY_OUT>; @@ -966,6 +964,25 @@ status = "disabled"; }; + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "otg"; + phy_type = "utmi_wide"; + snps,dis-del-phy-power-chg-quirk; + snps,dis_enblslpm_quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + status = "disabled"; + }; + /* * U-boot Specific Change * @@ -1163,7 +1180,7 @@ rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, <0 RK_PA6 2 &pcfg_pull_none>; }; - i2c3_gpio: i2c3-gpio { + i2c3_pins: i2c3-pins { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -1234,7 +1251,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -1245,8 +1262,8 @@ uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB0 1 &pcfg_pull_up>; }; uart0_cts: uart0-cts { @@ -1257,15 +1274,15 @@ rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; }; - uart0_rts_gpio: uart0-rts-gpio { + uart0_rts_pin: uart0-rts-pin { rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, - <3 RK_PA6 4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, + <3 RK_PA6 4 &pcfg_pull_up>; }; uart1_cts: uart1-cts { @@ -1276,22 +1293,22 @@ rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; }; - uart1_rts_gpio: uart1-rts-gpio { + uart1_rts_pin: uart1-rts-pin { rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart2-0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, - <1 RK_PA1 2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, + <1 RK_PA1 2 &pcfg_pull_up>; }; }; uart2-1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, - <2 RK_PA1 1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_up>; }; }; @@ -1502,7 +1519,7 @@ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; }; - sdmmc0m0_gpio: sdmmc0m0-gpio { + sdmmc0m0_pin: sdmmc0m0-pin { rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; @@ -1512,7 +1529,7 @@ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; }; - sdmmc0m1_gpio: sdmmc0m1-gpio { + sdmmc0m1_pin: sdmmc0m1-pin { rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; @@ -1545,7 +1562,7 @@ <1 RK_PA3 1 &pcfg_pull_up_8ma>; }; - sdmmc0_gpio: sdmmc0-gpio { + sdmmc0_pins: sdmmc0-pins { rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, @@ -1587,7 +1604,7 @@ <3 RK_PA7 3 &pcfg_pull_up_4ma>; }; - sdmmc0ext_gpio: sdmmc0ext-gpio { + sdmmc0ext_pins: sdmmc0ext-pins { rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, @@ -1632,7 +1649,7 @@ <1 RK_PC1 1 &pcfg_pull_up_8ma>; }; - sdmmc1_gpio: sdmmc1-gpio { + sdmmc1_pins: sdmmc1-pins { rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, @@ -1826,7 +1843,7 @@ tsadc_int: tsadc-int { rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; }; - tsadc_gpio: tsadc-gpio { + tsadc_pin: tsadc-pin { rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts index 46cdddfcea..62aa97a0b8 100644 --- a/arch/arm/dts/rk3368-geekbox.dts +++ b/arch/arm/dts/rk3368-geekbox.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -48,6 +11,10 @@ model = "GeekBox"; compatible = "geekbuying,geekbox", "rockchip,rk3368"; + aliases { + mmc0 = &emmc; + }; + chosen { stdout-path = "serial2:115200n8"; }; @@ -66,7 +33,7 @@ ir: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_int>; }; @@ -77,7 +44,7 @@ pinctrl-0 = <&pwr_key>; power { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; wakeup-source; @@ -87,14 +54,14 @@ leds: gpio-leds { compatible = "gpio-leds"; - blue { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + blue_led: led-0 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; label = "geekbox:blue:led"; default-state = "on"; }; - red { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + red_led: led-1 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; label = "geekbox:red:led"; default-state = "off"; }; @@ -115,10 +82,7 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <150000000>; - disable-wp; - keep-power-in-suspend; non-removable; - num-slots = <1>; vmmc-supply = <&vcc_io>; vqmmc-supply = <&vcc18_flash>; pinctrl-names = "default"; @@ -147,7 +111,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pmic_sleep>; interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; rockchip,system-power-controller; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; @@ -258,8 +222,6 @@ }; vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; regulator-name = "vcc_sd"; }; @@ -275,23 +237,23 @@ &pinctrl { ir { ir_int: ir-int { - rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; keys { pwr_key: pwr-key { - rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; pmic_int: pmic-int { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3368-lion-haikou.dts b/arch/arm/dts/rk3368-lion-haikou.dts index 7fcb1eacea..cae01d35b9 100644 --- a/arch/arm/dts/rk3368-lion-haikou.dts +++ b/arch/arm/dts/rk3368-lion-haikou.dts @@ -10,6 +10,10 @@ model = "Theobroma Systems RK3368-uQ7 Baseboard"; compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; + aliases { + mmc1 = &sdmmc; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/rk3368-lion.dtsi b/arch/arm/dts/rk3368-lion.dtsi index 532e6a6828..bcd7977fb0 100644 --- a/arch/arm/dts/rk3368-lion.dtsi +++ b/arch/arm/dts/rk3368-lion.dtsi @@ -7,6 +7,10 @@ #include "rk3368.dtsi" / { + aliases { + mmc0 = &emmc; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -150,7 +154,6 @@ assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; clock_in_out = "input"; - phy-handle = <&phy0>; phy-supply = <&vcc33_io>; phy-mode = "rgmii"; pinctrl-names = "default"; @@ -161,22 +164,6 @@ tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* Microsemi VSC8531-02 */ - phy0: phy@0 { - compatible = "ethernet-phy-id0007.0570"; - reg = <0>; - vsc8531,clk-out-frequency = <125000000>; - vsc8531,edge-slowdown = <7>; - vsc8531,led-0-mode = <1>; - vsc8531,led-1-mode = <2>; - }; - }; }; &i2c0 { diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts index e9c5ebad47..5ccaa5f7a3 100644 --- a/arch/arm/dts/rk3368-px5-evb.dts +++ b/arch/arm/dts/rk3368-px5-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd */ /dts-v1/; @@ -45,30 +8,21 @@ #include / { - model = "PX5 EVB"; + model = "Rockchip PX5 EVB"; compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial4:115200n8"; }; memory@0 { - device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; - }; - - ext_gmac: gmac-clk { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; + device_type = "memory"; }; keys: gpio-keys { @@ -77,29 +31,13 @@ pinctrl-0 = <&pwr_key>; power { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; wakeup-source; }; }; - leds: gpio-leds { - compatible = "gpio-leds"; - - blue { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "geekbox:blue:led"; - default-state = "on"; - }; - - red { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - label = "geekbox:red:led"; - default-state = "off"; - }; - }; - vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -115,27 +53,14 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <150000000>; - disable-wp; - keep-power-in-suspend; + mmc-hs200-1_8v; + no-sdio; + no-sd; non-removable; - num-slots = <1>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_flash>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; -}; - -&gmac { - status = "okay"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; }; &i2c0 { @@ -144,10 +69,10 @@ rk808: pmic@1b { compatible = "rockchip,rk808"; reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pmic_sleep>; - interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; rockchip,system-power-controller; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; @@ -202,12 +127,12 @@ regulator-name = "vcc18_flash"; }; - vcc33_lcd: LDO_REG2 { + vcca_33: LDO_REG2 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_lcd"; + regulator-name = "vcca_33"; }; vdd_10: LDO_REG3 { @@ -218,11 +143,10 @@ regulator-name = "vdd_10"; }; - vcca_18: LDO_REG4 { - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_18"; + avdd_33: LDO_REG4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd_33"; }; vccio_sd: LDO_REG5 { @@ -258,46 +182,76 @@ }; vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; regulator-name = "vcc_sd"; }; - vcc_lan: SWITCH_REG2 { + vcc33_lcd: SWITCH_REG2 { regulator-always-on; regulator-boot-on; - regulator-name = "vcc_lan"; + regulator-name = "vcc33_lcd"; }; }; }; }; -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; +&i2c1 { + status = "okay"; + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = ; + }; +}; + +&i2c2 { + status = "okay"; + + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio3>; + interrupts = ; + power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&pinctrl { keys { pwr_key: pwr-key { - rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; pmic_int: pmic-int { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; -&saradc { +&sdmmc { status = "okay"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + no-sdio; + sd-uhs-sdr12; + sd-uhs-sdr25; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; }; &tsadc { diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index cd2c322071..4c64fbefb4 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -136,37 +136,6 @@ }; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC_PERI>; - clock-names = "apb_pclk"; - }; - - dmac_bus: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC_BUS>; - clock-names = "apb_pclk"; - }; - }; - arm-pmu { compatible = "arm,armv8-pmuv3"; interrupts = , @@ -399,8 +368,20 @@ status = "disabled"; }; + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_PERI>; + clock-names = "apb_pclk"; + }; + thermal-zones { - cpu { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -444,7 +425,7 @@ }; }; - gpu { + gpu_thermal: gpu-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -532,6 +513,18 @@ status = "disabled"; }; + dmac_bus: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_BUS>; + clock-names = "apb_pclk"; + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -565,7 +558,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; status = "disabled"; }; @@ -576,7 +568,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; status = "disabled"; }; @@ -585,7 +576,6 @@ reg = <0x0 0xff680020 0x0 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; status = "disabled"; }; @@ -596,7 +586,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; status = "disabled"; }; @@ -675,6 +664,8 @@ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; }; spdif: spdif@ff880000 { diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 694b0d08d6..7b717ebec8 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -11,6 +11,10 @@ model = "Rockchip RK3399 Evaluation Board"; compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; + aliases { + mmc0 = &sdhci; + }; + backlight: backlight { compatible = "pwm-backlight"; brightness-levels = < diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index ebe2ee77ba..1ce85a5816 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -27,42 +27,43 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; - user_led1 { + user_led1: led-1 { label = "red:user1"; gpios = <&gpio4 25 0>; linux,default-trigger = "heartbeat"; }; - user_led2 { + user_led2: led-2 { label = "red:user2"; gpios = <&gpio4 26 0>; linux,default-trigger = "mmc0"; }; - user_led3 { + user_led3: led-3 { label = "red:user3"; gpios = <&gpio4 30 0>; linux,default-trigger = "mmc1"; }; - user_led4 { + user_led4: led-4 { label = "red:user4"; gpios = <&gpio1 0 0>; panic-indicator; linux,default-trigger = "none"; }; - wlan_active_led { + wlan_active_led: led-5 { label = "red:wlan"; gpios = <&gpio1 1 0>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt_active_led { + bt_active_led: led-6 { label = "red:bt"; gpios = <&gpio1 4 0>; linux,default-trigger = "hci0-power"; @@ -114,32 +115,32 @@ }; leds { - user_led1: user_led1 { + user_led1_pin: user-led1-pin { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led2: user_led2 { + user_led2_pin: user-led2-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led3: user_led3 { + user_led3_pin: user-led3-pin { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led4: user_led4 { + user_led4_pin: user-led4-pin { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; - wlan_led: wlan_led { + wlan_led_pin: wlan-led-pin { rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_led: bt_led { + bt_led_pin: bt-led-pin { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index d63faf38cc..c4dd2a6b48 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include +#include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -13,6 +14,12 @@ model = "Firefly-RK3399 Board"; compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -88,18 +95,25 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; - work-led { + work_led: led-0 { label = "work"; default-state = "on"; gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; }; - diy-led { + diy_led: led-1 { label = "diy"; default-state = "off"; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; @@ -145,6 +159,23 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + sound-dit { + compatible = "audio-graph-card"; + label = "SPDIF"; + dais = <&spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -190,6 +221,17 @@ vin-supply = <&vcc_sys>; }; + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -515,6 +557,53 @@ i2c-scl-falling-time-ns = <20>; status = "okay"; + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + }; + }; + }; + accelerometer@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -572,12 +661,34 @@ }; }; + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + leds { + work_led_pin: work-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -589,30 +700,34 @@ }; pmic { - vsel1_gpio: vsel1-gpio { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - rt5640 { rt5640_hpcon: rt5640-hpcon { rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -627,16 +742,6 @@ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - leds { - work_led_gpio: work_led-gpio { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &pwm0 { @@ -704,10 +809,29 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdif_bus_1>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &tcphy0 { status = "okay"; }; +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -731,6 +855,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; }; &u2phy1 { diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index f9c5bb607b..b80f19066b 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -10,6 +10,11 @@ #include "rk3399-op1-opp.dtsi" / { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + chosen { stdout-path = "serial2:115200n8"; }; @@ -247,8 +252,8 @@ enable-active-high; enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3000000 0x0>; + states = <1800000 0x1>, + <3000000 0x0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; @@ -342,6 +347,7 @@ cpu-supply = <&ppvar_bigcpu>; }; + &cru { assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, @@ -515,7 +521,7 @@ ap_i2c_audio: &i2c8 { * configured as SDMMC and not JTAG. */ pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin &sdmmc_bus4>; bus-width = <4>; @@ -766,7 +772,7 @@ ap_i2c_audio: &i2c8 { }; /* This is where we actually hook up CD; has external pull */ - sdmmc_cd_gpio: sdmmc-cd-gpio { + sdmmc_cd_pin: sdmmc-cd-pin { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi index e87a044774..d5c7648c84 100644 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -11,6 +11,12 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -138,18 +144,26 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-khadas"; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>; + pinctrl-0 = <&sys_led_pin>, <&user_led_pin>; - sys-led { + sys_led: led-0 { label = "sys_led"; linux,default-trigger = "heartbeat"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; }; - user-led { + user_led: led-1 { label = "user_led"; default-state = "off"; gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; @@ -585,12 +599,18 @@ }; }; + ir { + ir_rx: ir-rx { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { - sys_led_gpio: sys_led-gpio { + sys_led_pin: sys-led-pin { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led_gpio: user_led-gpio { + user_led_pin: user-led-pin { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -690,6 +710,16 @@ status = "okay"; }; +&spi1 { + status = "okay"; + + spiflash: flash@0 { + compatible = "winbond,w25q128fw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + &tcphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts index 73be38a537..7c93f840bc 100644 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -13,6 +13,12 @@ model = "Leez RK3399 P710"; compatible = "leez,p710", "rockchip,rk3399"; + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -341,7 +347,7 @@ reg = <0x40>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; + pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -360,7 +366,7 @@ reg = <0x41>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; + pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -447,11 +453,11 @@ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts index e0d75617bb..452728b82e 100644 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -95,6 +95,7 @@ }; &pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; vpcie3v3-supply = <&vcc3v3_sys>; }; diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts index 6f2cf17bf1..cef4d18b59 100644 --- a/arch/arm/dts/rk3399-nanopi-r4s.dts +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -1,13 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * FriendlyElec NanoPC-T4 board device tree source * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. * (http://www.friendlyarm.com) * * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - * Copyright (C) 2020 Xiaobo + * + * Copyright (c) 2020 Jensen Huang + * Copyright (c) 2020 Marty Jones + * Copyright (c) 2021 Tianling Shen */ /dts-v1/; @@ -17,8 +19,41 @@ model = "FriendlyElec NanoPi R4S"; compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - aliases { - ethernet1 = &r8169; + /delete-node/ display-subsystem; + + gpio-leds { + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + + /delete-node/ led-0; + + lan_led: led-lan { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "green:lan"; + }; + + sys_led: led-sys { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "red:power"; + default-state = "on"; + }; + + wan_led: led-wan { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "green:wan"; + }; + }; + + gpio-keys { + pinctrl-0 = <&reset_button_pin>; + + /delete-node/ power; + + reset { + debounce-interval = <50>; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; }; vdd_5v: vdd-5v { @@ -27,84 +62,44 @@ regulator-always-on; regulator-boot-on; }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 12 18 255>; - #cooling-cells = <2>; - fan-supply = <&vdd_5v>; - pwms = <&pwm1 0 50000 0>; - }; -}; - -&cpu_thermal { - trips { - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; }; &emmc_phy { status = "disabled"; }; -&fusb0 { +&i2c4 { status = "disabled"; }; -&leds { - lan_led: led-1 { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "nanopi-r4s:green:lan"; - }; - - wan_led: led-2 { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "nanopi-r4s:green:wan"; - }; -}; - -&leds_gpio { - rockchip,pins = - <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -}; - &pcie0 { max-link-speed = <1>; num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; +}; - pcie@0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; +&pinctrl { + gpio-leds { + /delete-node/ status-led-pin; - r8169: pcie@0,0 { - reg = <0x000000 0 0 0 0>; - local-mac-address = [ 00 00 00 00 00 00 ]; + lan_led_pin: lan-led-pin { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rockchip-key { + /delete-node/ power-key; + + reset_button_pin: reset-button-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; @@ -117,10 +112,6 @@ status = "disabled"; }; -&sdmmc { - host-index-min = <1>; -}; - &u2phy0_host { phy-supply = <&vdd_5v>; }; @@ -129,6 +120,10 @@ status = "disabled"; }; +&uart0 { + status = "disabled"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi index c88018a0ef..8c0ff6c96e 100644 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -17,6 +17,12 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -117,9 +123,9 @@ leds: gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_gpio>; + pinctrl-0 = <&status_led_pin>; - status { + status_led: led-0 { gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; label = "status_led"; linux,default-trigger = "heartbeat"; @@ -182,7 +188,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: phy@1 { + rtl8211e: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpio3>; interrupts = ; @@ -504,8 +510,6 @@ }; &pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <2>; vpcie0v9-supply = <&vcca0v9_s3>; vpcie1v8-supply = <&vcca1v8_s3>; @@ -520,12 +524,12 @@ }; gpio-leds { - leds_gpio: leds-gpio { + status_led_pin: status-led-pin { rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - phy { + gmac { phy_intb: phy-intb { rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index d6f1095abb..da41cd81eb 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -10,28 +10,28 @@ opp00 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1250000>; clock-latency-ns = <40000>; }; opp01 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1250000>; }; opp02 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000>; + opp-microvolt = <850000 850000 1250000>; }; opp03 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000>; + opp-microvolt = <925000 925000 1250000>; }; opp04 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1250000>; }; opp05 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000>; + opp-microvolt = <1125000 1125000 1250000>; }; }; @@ -41,36 +41,36 @@ opp00 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1250000>; clock-latency-ns = <40000>; }; opp01 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1250000>; }; opp02 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1250000>; }; opp03 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000>; + opp-microvolt = <875000 875000 1250000>; }; opp04 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1250000>; }; opp05 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; + opp-microvolt = <1025000 1025000 1250000>; }; opp06 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1250000>; }; opp07 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; + opp-microvolt = <1200000 1200000 1250000>; }; }; @@ -79,27 +79,27 @@ opp00 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1150000>; }; opp01 { opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <800000>; + opp-microvolt = <825000 825000 1150000>; }; opp02 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1150000>; }; opp03 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <875000>; + opp-microvolt = <875000 875000 1150000>; }; opp04 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000>; + opp-microvolt = <925000 925000 1150000>; }; opp05 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1150000>; }; }; }; diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts index f9f7246d4d..04b54abea3 100644 --- a/arch/arm/dts/rk3399-orangepi.dts +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -7,6 +7,7 @@ #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -14,6 +15,12 @@ model = "Orange Pi RK3399 Board"; compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -214,7 +221,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: phy@1 { + rtl8211e: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpio3>; interrupts = ; @@ -531,6 +538,43 @@ pinctrl-names = "default"; pinctrl-0 = <&chg_cc_int_l>; vbus-supply = <&vbus_typec>; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_hs: endpoint { + remote-endpoint = <&u2phy0_typec_hs>; + }; + }; + port@1 { + reg = <1>; + typec_ss: endpoint { + remote-endpoint = <&tcphy0_typec_ss>; + }; + }; + port@2 { + reg = <2>; + typec_dp: endpoint { + remote-endpoint = <&tcphy0_typec_dp>; + }; + }; + }; + }; }; }; @@ -554,7 +598,7 @@ }; }; - phy { + gmac { phy_intb: phy-intb { rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; @@ -717,6 +761,22 @@ status = "okay"; }; +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&typec_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -739,6 +799,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; }; &u2phy1 { @@ -799,7 +865,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts index 294d21bf45..2b5f001ff4 100644 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -18,6 +18,12 @@ model = "Pine64 Pinebook Pro"; compatible = "pine64,pinebook-pro", "rockchip,rk3399"; + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -28,12 +34,19 @@ pwms = <&pwm0 0 740740 0>; }; + bat: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <9800000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + }; + edp_panel: edp-panel { compatible = "boe,nv140fhmn49"; backlight = <&backlight>; enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&panel_en_gpio>; + pinctrl-0 = <&panel_en_pin>; power-supply = <&vcc3v3_panel>; ports { @@ -60,7 +73,7 @@ gpio-key-lid { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&lidbtn_gpio>; + pinctrl-0 = <&lidbtn_pin>; lid { debounce-interval = <20>; @@ -76,7 +89,7 @@ gpio-key-power { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn_gpio>; + pinctrl-0 = <&pwrbtn_pin>; power { debounce-interval = <20>; @@ -90,9 +103,9 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pwrled_gpio &slpled_gpio>; + pinctrl-0 = <&pwr_led_pin &slp_led_pin>; - green-led { + green_led: led-0 { color = ; default-state = "on"; function = LED_FUNCTION_POWER; @@ -100,7 +113,7 @@ label = "green:power"; }; - red-led { + red_led: led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STANDBY; @@ -117,7 +130,7 @@ clocks = <&rk808 1>; clock-names = "ext_clock"; pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h_gpio>; + pinctrl-0 = <&wifi_enable_h_pin>; post-power-on-delay-ms = <100>; power-off-delay-us = <500000>; @@ -129,7 +142,7 @@ es8316-sound { compatible = "simple-audio-card"; pinctrl-names = "default"; - pinctrl-0 = <&hp_det_gpio>; + pinctrl-0 = <&hp_det_pin>; simple-audio-card,name = "rockchip,es8316-codec"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <256>; @@ -213,7 +226,7 @@ enable-active-high; gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pwr_5v_gpio>; + pinctrl-0 = <&pwr_5v_pin>; regulator-name = "vcc5v0_usb"; regulator-always-on; regulator-min-microvolt = <5000000>; @@ -270,7 +283,7 @@ enable-active-high; gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h_gpio>; + pinctrl-0 = <&sdmmc0_pwr_h_pin>; regulator-name = "vcc3v0_sd"; regulator-always-on; regulator-min-microvolt = <3000000>; @@ -288,7 +301,7 @@ enable-active-high; gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&lcdvcc_en_gpio>; + pinctrl-0 = <&lcdvcc_en_pin>; regulator-name = "vcc3v3_panel"; regulator-always-on; regulator-min-microvolt = <3300000>; @@ -317,7 +330,7 @@ enable-active-high; gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en_gpio>; + pinctrl-0 = <&vcc5v0_host_en_pin>; regulator-name = "vcc5v0_otg"; regulator-always-on; regulator-min-microvolt = <5000000>; @@ -336,7 +349,7 @@ enable-active-high; gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en_gpio>; + pinctrl-0 = <&vcc5v0_typec0_en_pin>; regulator-name = "vbus_5vout"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -368,7 +381,7 @@ /* Also triggered by USB charger */ pinctrl-names = "default"; - pinctrl-0 = <&dc_det_gpio>; + pinctrl-0 = <&dc_det_pin>; }; }; @@ -447,7 +460,7 @@ interrupt-parent = <&gpio3>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l_gpio>; + pinctrl-0 = <&pmic_int_l_pin>; rockchip,system-power-controller; wakeup-source; @@ -627,7 +640,7 @@ reg = <0x40>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; + pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-always-on; regulator-boot-on; @@ -646,7 +659,7 @@ reg = <0x41>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; + pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-always-on; regulator-boot-on; @@ -690,9 +703,10 @@ fusb0: fusb30x@22 { compatible = "fcs,fusb302"; reg = <0x22>; - fcs,int_n = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = ; pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int_gpio>; + pinctrl-0 = <&fusb0_int_pin>; vbus-supply = <&vbus_typec>; connector { @@ -740,12 +754,29 @@ }; }; }; + + cw2015@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 < + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 + >; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&bat>; + power-supplies = <&mains_charger>, <&fusb0>; + }; }; &i2s1 { - #sound-dai-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>; + pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; rockchip,capture-channels = <8>; rockchip,playback-channels = <8>; status = "okay"; @@ -765,7 +796,6 @@ &pcie0 { bus-scan-delay-ms = <1000>; ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; @@ -777,116 +807,116 @@ &pinctrl { buttons { - pwrbtn_gpio: pwrbtn-gpio { + pwrbtn_pin: pwrbtn-pin { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; - lidbtn_gpio: lidbtn-gpio { + lidbtn_pin: lidbtn-pin { rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; dc-charger { - dc_det_gpio: dc-det-gpio { + dc_det_pin: dc-det-pin { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; es8316 { - hp_det_gpio: hp-det-gpio { + hp_det_pin: hp-det-pin { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; fusb302x { - fusb0_int_gpio: fusb0-int-gpio { + fusb0_int_pin: fusb0-int-pin { rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; i2s1 { - i2s_8ch_mclk_gpio: i2s-8ch-mclk-gpio { + i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; }; }; lcd-panel { - lcdvcc_en_gpio: lcdvcc-en-gpio { + lcdvcc_en_pin: lcdvcc-en-pin { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; - panel_en_gpio: panel-en-gpio { + panel_en_pin: panel-en-pin { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; - lcd_panel_reset_gpio: lcd-panel-reset-gpio { + lcd_panel_reset_pin: lcd-panel-reset-pin { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; leds { - pwrled_gpio: pwrled_gpio { + pwr_led_pin: pwr-led-pin { rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; - slpled_gpio: slpled_gpio { + slp_led_pin: slp-led-pin { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { - pmic_int_l_gpio: pmic-int-l-gpio { + pmic_int_l_pin: pmic-int-l-pin { rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; sdcard { - sdmmc0_pwr_h_gpio: sdmmc0-pwr-h-gpio { + sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin { rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sdio-pwrseq { - wifi_enable_h_gpio: wifi-enable-h-gpio { + wifi_enable_h_pin: wifi-enable-h-pin { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb-typec { - vcc5v0_typec0_en_gpio: vcc5v0-typec0-en-gpio { + vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; usb2 { - pwr_5v_gpio: pwr-5v-gpio { + pwr_5v_pin: pwr-5v-pin { rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_host_en_gpio: vcc5v0-host-en-gpio { + vcc5v0_host_en_pin: vcc5v0-host-en-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; wireless-bluetooth { - bt_wake_gpio: bt-wake-gpio { + bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_host_wake_gpio: bt-host-wake-gpio { + bt_host_wake_pin: bt-host-wake-pin { rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_reset_gpio: bt-reset-gpio { + bt_reset_pin: bt-reset-pin { rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -1034,7 +1064,7 @@ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; max-speed = <1500000>; pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_gpio &bt_wake_gpio &bt_reset_gpio>; + pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; vbat-supply = <&wifi_bat>; vddio-supply = <&vcc_wl>; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index d80d6b7268..292bb7e80c 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -10,14 +10,18 @@ model = "Theobroma Systems RK3399-Q7 SoM"; compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; + aliases { + mmc1 = &sdmmc; + }; + chosen { stdout-path = "serial0:115200n8"; }; leds { - pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>; + pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; - sd-card-led { + sd_card_led: led-1 { label = "sd_card_led"; gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; @@ -179,7 +183,7 @@ }; leds { - led_sd_haikou: led-sd-gpio { + sd_card_led_pin: sd-card-led-pin { rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 72c06abd27..fb67db4619 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -8,12 +8,16 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdhci; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&led_pin_module>; + pinctrl-0 = <&module_led_pin>; - module-led { + module_led: led-0 { label = "module_led"; gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -21,57 +25,6 @@ }; }; - /* - * Overwrite the opp-table for CPUB as this board uses a different - * regulator (FAN53555) that only allows 10mV steps and therefore - * can't reach the operation point target voltages from rk3399-opp.dtsi - */ - /delete-node/ opp-table1; - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <830000>; - opp-suspend; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <880000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1030000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; - }; - opp08 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1230000>; - turbo-mode; - }; - }; - clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -450,7 +403,7 @@ }; leds { - led_pin_module: led-module-gpio { + module_led_pin: module-led-pin { rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts index 2acb3d500f..9447c8724b 100644 --- a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts +++ b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts @@ -11,6 +11,20 @@ model = "Firefly ROC-RK3399-PC Mezzanine Board"; compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + aliases { + mmc2 = &sdio0; + }; + + /* MP8009 PoE PD */ + poe_12v: poe-12v { + compatible = "regulator-fixed"; + regulator-name = "poe_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + vcc3v3_ngff: vcc3v3-ngff { compatible = "regulator-fixed"; regulator-name = "vcc3v3_ngff"; @@ -22,7 +36,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vcc3v3_pcie: vcc3v3-pcie { @@ -34,10 +48,14 @@ pinctrl-0 = <&vcc3v3_pcie_en>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; }; +&sys_12v { + vin-supply = <&poe_12v>; +}; + &pcie_phy { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi index 9f225e9c3d..d1aaf8e833 100644 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -13,6 +13,11 @@ model = "Firefly ROC-RK3399-PC Board"; compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -58,30 +63,37 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>; - work-led { + work_led: led-0 { label = "green:work"; gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; default-state = "on"; linux,default-trigger = "heartbeat"; }; - diy-led { + diy_led: led-1 { label = "red:diy"; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; default-state = "off"; - linux,default-trigger = "mmc1"; + linux,default-trigger = "mmc2"; }; - yellow-led { + yellow_led: led-2 { label = "yellow:yellow-led"; gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; default-state = "off"; - linux,default-trigger = "mmc0"; + linux,default-trigger = "mmc1"; }; }; @@ -110,6 +122,14 @@ regulator-max-microvolt = <5000000>; }; + sys_12v: sys-12v { + compatible = "regulator-fixed"; + regulator-name = "sys_12v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -141,7 +161,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vcca_0v9: vcca-0v9 { @@ -186,7 +206,7 @@ regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vdd_log: vdd-log { @@ -376,6 +396,7 @@ vcc_sdio: LDO_REG4 { regulator-name = "vcc_sdio"; + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; @@ -456,7 +477,7 @@ reg = <0x40>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; + pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -475,11 +496,13 @@ reg = <0x41>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; + pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc3v3_sys>; regulator-state-mem { @@ -588,6 +611,12 @@ }; }; + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -595,25 +624,25 @@ }; leds { - diy_led_gpio: diy_led-gpio { + diy_led_pin: diy-led-pin { rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led_gpio: work_led-gpio { + work_led_pin: work-led-pin { rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; - yellow_led_gpio: yellow_led-gpio { + yellow_led_pin: yellow-led-pin { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index 1c55a4645b..b28888ea92 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -11,6 +11,11 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -111,10 +116,6 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; }; vdd_log: vdd-log { @@ -362,8 +363,6 @@ regulator-name = "vcc_cam"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -373,8 +372,6 @@ regulator-name = "vcc_mipi"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -387,7 +384,7 @@ reg = <0x40>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; + pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -406,7 +403,7 @@ reg = <0x41>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; + pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -440,8 +437,9 @@ }; &i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,capture-channels = <2>; + rockchip,playback-channels = <2>; status = "okay"; }; @@ -476,7 +474,6 @@ &pcie0 { ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; @@ -529,11 +526,11 @@ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -680,7 +677,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts index d96dd3ebd3..89f2af5e11 100644 --- a/arch/arm/dts/rk3399-rock-pi-4a.dts +++ b/arch/arm/dts/rk3399-rock-pi-4a.dts @@ -9,5 +9,5 @@ / { model = "Radxa ROCK Pi 4A"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; + compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; }; diff --git a/arch/arm/dts/rk3399-rock-pi-4b.dts b/arch/arm/dts/rk3399-rock-pi-4b.dts index 4ca970acac..6c63e61706 100644 --- a/arch/arm/dts/rk3399-rock-pi-4b.dts +++ b/arch/arm/dts/rk3399-rock-pi-4b.dts @@ -9,7 +9,11 @@ / { model = "Radxa ROCK Pi 4B"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; + compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; }; &sdio0 { diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index 9d07ebd1ec..99169bcd51 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -10,7 +10,11 @@ / { model = "Radxa ROCK Pi 4C"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; + compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; }; &sdio0 { diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 437a75f31a..1a23e8f3cd 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -17,42 +17,43 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; - user_led1 { + user_led1: led-1 { label = "green:user1"; gpios = <&gpio4 RK_PC2 0>; linux,default-trigger = "heartbeat"; }; - user_led2 { + user_led2: led-2 { label = "green:user2"; gpios = <&gpio4 RK_PC6 0>; linux,default-trigger = "mmc0"; }; - user_led3 { + user_led3: led-3 { label = "green:user3"; gpios = <&gpio4 RK_PD0 0>; linux,default-trigger = "mmc1"; }; - user_led4 { + user_led4: led-4 { label = "green:user4"; gpios = <&gpio4 RK_PD4 0>; panic-indicator; linux,default-trigger = "none"; }; - wlan_active_led { + wlan_active_led: led-5 { label = "yellow:wlan"; gpios = <&gpio4 RK_PD5 0>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt_active_led { + bt_active_led: led-6 { label = "blue:bt"; gpios = <&gpio4 RK_PD6 0>; linux,default-trigger = "hci0-power"; @@ -62,38 +63,52 @@ }; +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_thermal { + sustainable-power = <1550>; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + }; + }; +}; + &pcie0 { ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; }; &pinctrl { leds { - user_led1: user_led1 { + user_led1_pin: user-led1-pin { rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led2: user_led2 { + user_led2_pin: user-led2-pin { rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led3: user_led3 { + user_led3_pin: user-led3-pin { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led4: user_led4 { + user_led4_pin: user-led4-pin { rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; - wlan_led: wlan_led { + wlan_led_pin: wlan-led-pin { rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_led: bt_led { + bt_led_pin: bt-led-pin { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -124,45 +139,6 @@ status = "okay"; }; -&thermal_zones { - cpu_thermal: cpu { - polling-delay-passive = <100>; - polling-delay = <1000>; - thermal-sensors = <&tsadc 0>; - sustainable-power = <1550>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <65000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - - trip = <&cpu_alert1>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - &usbdrd_dwc3_0 { dr_mode = "otg"; }; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index ba7c75c9f2..25dc61c26a 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -9,6 +9,12 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; @@ -470,12 +476,12 @@ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi index 9bca258012..6bff8db7d3 100644 --- a/arch/arm/dts/rk3399-rockpro64.dtsi +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -10,6 +10,12 @@ #include "rk3399-opp.dtsi" / { + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -36,18 +42,25 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; - work-led { + work_led: led-0 { label = "work"; default-state = "on"; gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; }; - diy-led { + diy_led: led-1 { label = "diy"; default-state = "off"; gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; @@ -72,10 +85,27 @@ sound { compatible = "audio-graph-card"; - label = "rockchip,rk3399"; + label = "Analog"; dais = <&i2s1_p0>; }; + sound-dit { + compatible = "audio-graph-card"; + label = "SPDIF"; + dais = <&spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -96,6 +126,24 @@ vin-supply = <&vcc_1v8>; }; + /* micro SD card power */ + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -427,7 +475,7 @@ reg = <0x40>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; + pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -446,7 +494,7 @@ reg = <0x41>; fcs,suspend-voltage-selector = <1>; pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; + pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -569,12 +617,18 @@ }; }; + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { - work_led_gpio: work_led-gpio { + work_led_pin: work-led-pin { rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; - diy_led_gpio: diy_led-gpio { + diy_led_pin: diy-led-pin { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -594,15 +648,22 @@ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_pin: vsel2-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; + sdcard { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -661,6 +722,8 @@ max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; status = "okay"; }; @@ -671,6 +734,16 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdif_bus_1>; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &spi1 { status = "okay"; @@ -768,7 +841,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 74f2c3d490..3871c7fd83 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -197,38 +197,12 @@ #clock-cells = <0>; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_bus: dma-controller@ff6d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC0_PERILP>; - clock-names = "apb_pclk"; - }; - - dmac_peri: dma-controller@ff6e0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1_PERILP>; - clock-names = "apb_pclk"; - }; - }; - pcie0: pcie@f8000000 { compatible = "rockchip,rk3399-pcie"; reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; reg-names = "axi-base", "apb-base"; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; @@ -247,15 +221,14 @@ <0 0 0 2 &pcie0_intc 1>, <0 0 0 3 &pcie0_intc 2>, <0 0 0 4 &pcie0_intc 3>; - linux,pci-domain = <0>; max-link-speed = <1>; msi-map = <0x0 &its 0x0 0x1000>; phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 - 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, + <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, @@ -326,7 +299,7 @@ status = "disabled"; }; - sdhci: sdhci@fe330000 { + sdhci: mmc@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; @@ -403,7 +376,7 @@ reset-names = "usb3-otg"; status = "disabled"; - usbdrd_dwc3_0: dwc3 { + usbdrd_dwc3_0: usb@fe800000 { compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; @@ -439,7 +412,7 @@ reset-names = "usb3-otg"; status = "disabled"; - usbdrd_dwc3_1: dwc3 { + usbdrd_dwc3_1: usb@fe900000 { compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; @@ -759,7 +732,7 @@ }; thermal_zones: thermal-zones { - cpu_thermal: cpu { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; polling-delay = <1000>; @@ -803,7 +776,7 @@ }; }; - gpu_thermal: gpu { + gpu_thermal: gpu-thermal { polling-delay-passive = <100>; polling-delay = <1000>; @@ -845,135 +818,135 @@ rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; status = "disabled"; }; qos_emmc: qos@ffa58000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa58000 0x0 0x20>; }; qos_gmac: qos@ffa5c000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa5c000 0x0 0x20>; }; qos_pcie: qos@ffa60080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa60080 0x0 0x20>; }; qos_usb_host0: qos@ffa60100 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa60100 0x0 0x20>; }; qos_usb_host1: qos@ffa60180 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa60180 0x0 0x20>; }; qos_usb_otg0: qos@ffa70000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa70000 0x0 0x20>; }; qos_usb_otg1: qos@ffa70080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa70080 0x0 0x20>; }; qos_sd: qos@ffa74000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa74000 0x0 0x20>; }; qos_sdioaudio: qos@ffa76000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa76000 0x0 0x20>; }; qos_hdcp: qos@ffa90000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa90000 0x0 0x20>; }; qos_iep: qos@ffa98000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffa98000 0x0 0x20>; }; qos_isp0_m0: qos@ffaa0000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffaa0000 0x0 0x20>; }; qos_isp0_m1: qos@ffaa0080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffaa0080 0x0 0x20>; }; qos_isp1_m0: qos@ffaa8000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffaa8000 0x0 0x20>; }; qos_isp1_m1: qos@ffaa8080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffaa8080 0x0 0x20>; }; qos_rga_r: qos@ffab0000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffab0000 0x0 0x20>; }; qos_rga_w: qos@ffab0080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffab0080 0x0 0x20>; }; qos_video_m0: qos@ffab8000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffab8000 0x0 0x20>; }; qos_video_m1_r: qos@ffac0000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffac0000 0x0 0x20>; }; qos_video_m1_w: qos@ffac0080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffac0080 0x0 0x20>; }; qos_vop_big_r: qos@ffac8000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffac8000 0x0 0x20>; }; qos_vop_big_w: qos@ffac8080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffac8080 0x0 0x20>; }; qos_vop_little: qos@ffad0000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffad0000 0x0 0x20>; }; qos_perihp: qos@ffad8080 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffad8080 0x0 0x20>; }; qos_gpu: qos@ffae0000 { - compatible = "syscon"; + compatible = "rockchip,rk3399-qos", "syscon"; reg = <0x0 0xffae0000 0x0 0x20>; }; @@ -995,126 +968,146 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; + #power-domain-cells = <0>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = ; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; + #power-domain-cells = <0>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = ; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = ; clocks = <&cru PCLK_EDP_CTRL>; + #power-domain-cells = <0>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = ; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; + #power-domain-cells = <0>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; + #power-domain-cells = <0>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = ; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; + #power-domain-cells = <0>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_TCPD0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_TCPD1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_USB3 { reg = ; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; + #power-domain-cells = <0>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = ; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = ; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = ; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; + #power-domain-cells = <0>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = ; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; + #power-domain-cells = <0>; }; - pd_tcpc0@RK3399_PD_TCPC0 { - reg = ; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - }; - pd_tcpc1@RK3399_PD_TCPC1 { - reg = ; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = ; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = ; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; + #power-domain-cells = <0>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = ; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; pm_qos = <&qos_vop_little>; + #power-domain-cells = <0>; }; }; }; @@ -1124,8 +1117,6 @@ pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; pmu_io_domains: io-domains { compatible = "rockchip,rk3399-pmu-io-voltage-domain"; @@ -1211,7 +1202,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; status = "disabled"; }; @@ -1222,7 +1212,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; status = "disabled"; }; @@ -1233,7 +1222,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; status = "disabled"; }; @@ -1244,7 +1232,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm3a_pin>; clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; status = "disabled"; }; @@ -1271,6 +1258,17 @@ power-domains = <&power RK3399_PD_VCODEC>; }; + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; + }; + vdec_mmu: iommu@ff660480 { compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; @@ -1278,8 +1276,8 @@ interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VDU>; #iommu-cells = <0>; - status = "disabled"; }; iep_mmu: iommu@ff670800 { @@ -1336,6 +1334,28 @@ }; }; + dmac_bus: dma-controller@ff6d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6d0000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0_PERILP>; + clock-names = "apb_pclk"; + }; + + dmac_peri: dma-controller@ff6e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6e0000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1_PERILP>; + clock-names = "apb_pclk"; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; @@ -1387,7 +1407,18 @@ status = "disabled"; }; - u2phy0: usb2-phy@e450 { + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy-rx0"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; @@ -1414,7 +1445,7 @@ }; }; - u2phy1: usb2-phy@e460 { + u2phy1: usb2phy@e460 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe460 0x10>; clocks = <&cru SCLK_USB2PHY1_REF>; @@ -1513,7 +1544,7 @@ }; watchdog@ff848000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = ; @@ -1700,6 +1731,32 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_WRAPPER>; + clock-names = "isp", "aclk", "hclk"; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; @@ -1883,10 +1940,10 @@ gpu: gpu@ff9a0000 { compatible = "rockchip,rk3399-mali", "arm,mali-t860"; reg = <0x0 0xff9a0000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "gpu", "job", "mmu"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; clocks = <&cru ACLK_GPU>; #cooling-cells = <2>; power-domains = <&power RK3399_PD_GPU>; @@ -2317,7 +2374,7 @@ }; }; - sleep { + suspend { ap_pwroff: ap-pwroff { rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; @@ -2475,7 +2532,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi index 5d087be04a..e1cb426f2a 100644 --- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -12,6 +12,11 @@ / { compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + vcc3v3_pcie: vcc-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -324,7 +329,6 @@ &pcie0 { ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; @@ -353,6 +357,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vbus_host { usb1_en_oc: usb1-en-oc { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi new file mode 100644 index 0000000000..581594c35d --- /dev/null +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + noc: syscon@10128000 { + compatible = "rockchip,rk3188-noc", "syscon"; + reg = <0x10128000 0x2000>; + u-boot,dm-spl; + }; + + dmc: dmc@20020000 { + /* unreviewed u-boot-specific binding */ + compatible = "rockchip,rk3188-dmc", "syscon"; + reg = <0x20020000 0x3fc + 0x20040000 0x294>; + clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; + clock-names = "pclk_ddrupctl", "pclk_publ"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,noc = <&noc>; + u-boot,dm-spl; + }; +}; + +&grf { + u-boot,dm-spl; +}; + +&pmu { + u-boot,dm-spl; +}; + +&uart2 { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi index 612ed44bd6..616a828e0c 100644 --- a/arch/arm/dts/rk3xxx.dtsi +++ b/arch/arm/dts/rk3xxx.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner @@ -6,9 +6,12 @@ #include #include -#include "skeleton.dtsi" +#include / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; aliases { @@ -18,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -29,47 +29,6 @@ spi1 = &spi1; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; - }; - xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -77,7 +36,30 @@ clock-output-names = "xin24m"; }; - L2: l2-cache-controller@10138000 { + gpu: gpu@10090000 { + compatible = "arm,mali-400"; + reg = <0x10090000 0x10000>; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; cache-unified; @@ -92,14 +74,14 @@ global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; - interrupts = ; + interrupts = ; clocks = <&cru CORE_PERI>; }; local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; - interrupts = ; + interrupts = ; clocks = <&cru CORE_PERI>; }; @@ -133,10 +115,44 @@ status = "disabled"; }; - noc: syscon@10128000 { - u-boot,dm-spl; - compatible = "rockchip,rk3188-noc", "syscon"; - reg = <0x10128000 0x2000>; + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_lcdc0: qos@1012f000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_cif0: qos@1012f080 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_ipp: qos@1012f100 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc1: qos@1012f180 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_cif1: qos@1012f200 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f200 0x20>; + }; + + qos_rga: qos@1012f280 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f280 0x20>; }; usb_otg: usb@10180000 { @@ -149,7 +165,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -184,60 +199,99 @@ status = "disabled"; }; - mmc0: dwmmc@10214000 { + mmc0: mmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; status = "disabled"; }; - mmc1: dwmmc@10218000 { + mmc1: mmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; + dmas = <&dmac2 3>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; status = "disabled"; }; - emmc: dwmmc@1021c000 { + emmc: mmc@1021c000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x1021c000 0x1000>; interrupts = ; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; + dmas = <&dmac2 4>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC0>; + clock-names = "ahb"; status = "disabled"; }; pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; reg = <0x20004000 0x100>; - u-boot,dm-spl; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; grf: grf@20008000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x20008000 0x200>; - u-boot,dm-spl; }; - dmc: dmc@20020000 { - /* unreviewed u-boot-specific binding */ - compatible = "rockchip,rk3188-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - rockchip,noc = <&noc>; - reg = <0x20020000 0x3fc - 0x20040000 0x294>; - clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; - clock-names = "pclk_ddrupctl", "pclk_publ"; - u-boot,dm-spl; + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; }; i2c0: i2c@2002d000 { @@ -361,7 +415,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <1>; - clock-frequency = <24000000>; clock-names = "baudclk", "apb_pclk"; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; status = "disabled"; @@ -385,6 +438,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -413,4 +468,16 @@ dma-names = "tx", "rx"; status = "disabled"; }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; }; diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 6fcef63c1b..be70d30cc8 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -51,6 +51,57 @@ struct mm_region *mem_map = px30_mem_map; #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) +/* GRF_GPIO1AL_IOMUX */ +enum { + GPIO1A3_SHIFT = 12, + GPIO1A3_MASK = 0xf << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_FLASH_D3, + GPIO1A3_EMMC_D3, + GPIO1A3_SFC_SIO3, + + GPIO1A2_SHIFT = 8, + GPIO1A2_MASK = 0xf << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_FLASH_D2, + GPIO1A2_EMMC_D2, + GPIO1A2_SFC_SIO2, + + GPIO1A1_SHIFT = 4, + GPIO1A1_MASK = 0xf << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_FLASH_D1, + GPIO1A1_EMMC_D1, + GPIO1A1_SFC_SIO1, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 0xf << GPIO1A0_SHIFT, + GPIO1A0_GPIO = 0, + GPIO1A0_FLASH_D0, + GPIO1A0_EMMC_D0, + GPIO1A0_SFC_SIO0, +}; + +/* GRF_GPIO1AH_IOMUX */ +enum { + GPIO1A4_SHIFT = 0, + GPIO1A4_MASK = 0xf << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_FLASH_D4, + GPIO1A4_EMMC_D4, + GPIO1A4_SFC_CSN0, +}; + +/* GRF_GPIO1BL_IOMUX */ +enum { + GPIO1B1_SHIFT = 4, + GPIO1B1_MASK = 0xf << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_FLASH_RDY, + GPIO1B1_EMMC_CLKOUT, + GPIO1B1_SFC_CLK, +}; + /* GRF_GPIO1BH_IOMUX */ enum { GPIO1B7_SHIFT = 12, @@ -193,6 +244,19 @@ int arch_cpu_init(void) GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); #endif +#ifdef CONFIG_ROCKCHIP_SFC + rk_clrsetreg(&grf->gpio1al_iomux, + GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK, + GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT | + GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT | + GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT | + GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT); + rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK, + GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT); + rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK, + GPIO1B1_SFC_CLK << GPIO1B1_SHIFT); +#endif + #endif /* Enable PD_VO (default disable at reset) */ diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 311d7b1364..2bc8e60b99 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", - [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe320000", }; diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 21477719dc..d5eba1d903 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -29,9 +29,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 6b746f4c65..a49b6f19f4 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -581,6 +581,32 @@ static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, return px30_mmc_get_clk(priv, clk_id); } +static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id) +{ + struct px30_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[22]); + div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong px30_sfc_set_clk(struct px30_clk_priv *priv, + ulong clk_id, ulong set_rate) +{ + struct px30_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); + rk_clrsetreg(&cru->clksel_con[22], + SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK, + 0 << SFC_PLL_SEL_SHIFT | + (src_clk_div - 1) << SFC_DIV_CON_SHIFT); + + return px30_sfc_get_clk(priv, clk_id); +} + static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) { struct px30_cru *cru = priv->cru; @@ -1192,6 +1218,9 @@ static ulong px30_clk_get_rate(struct clk *clk) case SCLK_EMMC_SAMPLE: rate = px30_mmc_get_clk(priv, clk->id); break; + case SCLK_SFC: + rate = px30_sfc_get_clk(priv, clk->id); + break; case SCLK_I2C0: case SCLK_I2C1: case SCLK_I2C2: @@ -1271,6 +1300,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) case SCLK_EMMC: ret = px30_mmc_set_clk(priv, clk->id, rate); break; + case SCLK_SFC: + ret = px30_sfc_set_clk(priv, clk->id, rate); + break; case SCLK_I2C0: case SCLK_I2C1: case SCLK_I2C2: diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index d95f8b2a15..1ac00587d4 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -6,90 +6,421 @@ */ #include +#include #include +#include #include +#include #include #include +#include #include #include +#include "mmc_private.h" #include -#include +#include +#include +#include /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 +#define KHz (1000) +#define MHz (1000 * KHz) +#define SDHCI_TUNING_LOOP_COUNT 40 + +#define PHYCTRL_CALDONE_MASK 0x1 +#define PHYCTRL_CALDONE_SHIFT 0x6 +#define PHYCTRL_CALDONE_DONE 0x1 +#define PHYCTRL_DLLRDY_MASK 0x1 +#define PHYCTRL_DLLRDY_SHIFT 0x5 +#define PHYCTRL_DLLRDY_DONE 0x1 +#define PHYCTRL_FREQSEL_200M 0x0 +#define PHYCTRL_FREQSEL_50M 0x1 +#define PHYCTRL_FREQSEL_100M 0x2 +#define PHYCTRL_FREQSEL_150M 0x3 +#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ + ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ + PHYCTRL_DLLRDY_DONE) + +/* Rockchip specific Registers */ +#define DWCMSHC_EMMC_DLL_CTRL 0x800 +#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) +#define DWCMSHC_EMMC_DLL_RXCLK 0x804 +#define DWCMSHC_EMMC_DLL_TXCLK 0x808 +#define DWCMSHC_EMMC_DLL_STRBIN 0x80c +#define DWCMSHC_EMMC_DLL_STATUS0 0x840 +#define DWCMSHC_EMMC_DLL_STATUS1 0x844 +#define DWCMSHC_EMMC_DLL_START BIT(0) +#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 +#define DWCMSHC_EMMC_DLL_START_POINT 16 +#define DWCMSHC_EMMC_DLL_START_DEFAULT 5 +#define DWCMSHC_EMMC_DLL_INC_VALUE 2 +#define DWCMSHC_EMMC_DLL_INC 8 +#define DWCMSHC_EMMC_DLL_DLYENA BIT(27) +#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 +#define DLL_STRBIN_TAPNUM_DEFAULT 0x3 +#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) +#define DWCMSHC_EMMC_DLL_LOCKED BIT(8) +#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) +#define DLL_RXCLK_NO_INVERTER 1 +#define DLL_RXCLK_INVERTER 0 +#define DWCMSHC_ENHANCED_STROBE BIT(8) +#define DLL_LOCK_WO_TMOUT(x) \ + ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ + (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) +#define ROCKCHIP_MAX_CLKS 3 struct rockchip_sdhc_plat { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; -#endif struct mmc_config cfg; struct mmc mmc; }; -struct rockchip_sdhc { - struct sdhci_host host; - void *base; +struct rockchip_emmc_phy { + u32 emmcphy_con[7]; + u32 reserved; + u32 emmcphy_status; }; -static int arasan_sdhci_probe(struct udevice *dev) +struct rockchip_sdhc { + struct sdhci_host host; + struct udevice *dev; + void *base; + struct rockchip_emmc_phy *phy; + struct clk emmc_clk; +}; + +struct sdhci_data { + int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); + int (*emmc_phy_init)(struct udevice *dev); + int (*get_phy)(struct udevice *dev); +}; + +static int rk3399_emmc_phy_init(struct udevice *dev) { + return 0; +} + +static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) +{ + u32 caldone, dllrdy, freqsel; + + writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); + writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); + writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); + + /* + * According to the user manual, calpad calibration + * cycle takes more than 2us without the minimal recommended + * value, so we may need a little margin here + */ + udelay(3); + writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); + + /* + * According to the user manual, it asks driver to + * wait 5us for calpad busy trimming. But it seems that + * 5us of caldone isn't enough for all cases. + */ + udelay(500); + caldone = readl(&phy->emmcphy_status); + caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; + if (caldone != PHYCTRL_CALDONE_DONE) { + printf("%s: caldone timeout.\n", __func__); + return; + } + + /* Set the frequency of the DLL operation */ + if (clock < 75 * MHz) + freqsel = PHYCTRL_FREQSEL_50M; + else if (clock < 125 * MHz) + freqsel = PHYCTRL_FREQSEL_100M; + else if (clock < 175 * MHz) + freqsel = PHYCTRL_FREQSEL_150M; + else + freqsel = PHYCTRL_FREQSEL_200M; + + /* Set the frequency of the DLL operation */ + writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); + writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); + + read_poll_timeout(readl, &phy->emmcphy_status, dllrdy, + PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000); +} + +static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) +{ + writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); + writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); +} + +static int rk3399_emmc_get_phy(struct udevice *dev) +{ + struct rockchip_sdhc *priv = dev_get_priv(dev); + ofnode phy_node; + void *grf_base; + u32 grf_phy_offset, phandle; + + phandle = dev_read_u32_default(dev, "phys", 0); + phy_node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(phy_node)) { + debug("Not found emmc phy device\n"); + return -ENODEV; + } + + grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (grf_base < 0) { + printf("%s Get syscon grf failed", __func__); + return -ENODEV; + } + grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); + + priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); + + return 0; +} + +static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); + int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; + + if (cycle_phy) + rk3399_emmc_phy_power_off(priv->phy); + + sdhci_set_clock(host->mmc, clock); + + if (cycle_phy) + rk3399_emmc_phy_power_on(priv->phy, clock); + + return 0; +} + +static int rk3568_emmc_phy_init(struct udevice *dev) +{ + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + u32 extra; + + extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + + return 0; +} + +static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); + int val, ret; + u32 extra; + + if (clock > host->max_clk) + clock = host->max_clk; + if (clock) + clk_set_rate(&priv->emmc_clk, clock); + + sdhci_set_clock(host->mmc, clock); + + if (clock >= 100 * MHz) { + /* reset DLL */ + sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); + udelay(1); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); + + /* Init DLL settings */ + extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | + DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | + DWCMSHC_EMMC_DLL_START; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); + + ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, + val, DLL_LOCK_WO_TMOUT(val), 1, 500); + if (ret) + return ret; + + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_TXCLK_TAPNUM_DEFAULT | + DLL_TXCLK_TAPNUM_FROM_SW; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); + + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_STRBIN_TAPNUM_DEFAULT; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); + } else { + /* reset the clock phase when the frequency is lower than 100MHz */ + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); + extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + } + + return 0; +} + +static int rk3568_emmc_get_phy(struct udevice *dev) +{ + return 0; +} + +static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); + struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); + struct mmc *mmc = host->mmc; + uint clock = mmc->tran_speed; + u32 reg; + + if (!clock) + clock = mmc->clock; + + if (data->emmc_set_clock) + data->emmc_set_clock(host, clock); + + if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) { + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + reg |= SDHCI_CTRL_HS400; + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + } else { + sdhci_set_uhs_timing(host); + } + + return 0; +} + +static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct sdhci_host *host = dev_get_priv(mmc->dev); + char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + struct mmc_cmd cmd; + u32 ctrl, blk_size; + int ret = 0; + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl |= SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); + + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); + if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8) + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); + sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); + + cmd.cmdidx = opcode; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + do { + if (tuning_loop_counter-- == 0) + break; + + mmc_send_cmd(mmc, &cmd, NULL); + + if (opcode == MMC_CMD_SEND_TUNING_BLOCK) + /* + * For tuning command, do not do busy loop. As tuning + * is happening (CLK-DATA latching for setup/hold time + * requirements), give time to complete + */ + udelay(1); + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + } while (ctrl & SDHCI_CTRL_EXEC_TUNING); + + if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { + printf("%s:Tuning failed\n", __func__); + ret = -EIO; + } + + if (tuning_loop_counter < 0) { + ctrl &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); + } + + /* Enable only interrupts served by the SD controller */ + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); + /* Mask all sdhci interrupt sources */ + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); + + return ret; +} + +static struct sdhci_ops rockchip_sdhci_ops = { + .set_ios_post = rockchip_sdhci_set_ios_post, + .platform_execute_tuning = &rockchip_sdhci_execute_tuning, +}; + +static int rockchip_sdhci_probe(struct udevice *dev) +{ + struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_sdhc_plat *plat = dev_get_plat(dev); struct rockchip_sdhc *prv = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; struct sdhci_host *host = &prv->host; - int max_frequency, ret; struct clk clk; + int ret; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; - - host->name = dev->name; - host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); - max_frequency = dtplat->max_frequency; - ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk); -#else - max_frequency = dev_read_u32_default(dev, "max-frequency", 0); + host->max_clk = cfg->f_max; ret = clk_get_by_index(dev, 0, &clk); -#endif if (!ret) { - ret = clk_set_rate(&clk, max_frequency); + ret = clk_set_rate(&clk, host->max_clk); if (IS_ERR_VALUE(ret)) printf("%s clk set rate fail!\n", __func__); } else { printf("%s fail to get clk\n", __func__); } + prv->emmc_clk = clk; + prv->dev = dev; + + if (data->get_phy) { + ret = data->get_phy(dev); + if (ret) + return ret; + } + + if (data->emmc_phy_init) { + ret = data->emmc_phy_init(dev); + if (ret) + return ret; + } + + host->ops = &rockchip_sdhci_ops; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; - host->max_clk = max_frequency; - /* - * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg - * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't - * check for other bus-width values. - */ - if (host->bus_width == 8) - host->host_caps |= MMC_MODE_8BIT; host->mmc = &plat->mmc; host->mmc->priv = &prv->host; host->mmc->dev = dev; upriv->mmc = host->mmc; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); + ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); if (ret) return ret; return sdhci_probe(dev); } -static int arasan_sdhci_of_to_plat(struct udevice *dev) +static int rockchip_sdhci_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_sdhc_plat *plat = dev_get_plat(dev); struct sdhci_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; + int ret; host->name = dev->name; host->ioaddr = dev_read_addr_ptr(dev); - host->bus_width = dev_read_u32_default(dev, "bus-width", 4); -#endif + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret; return 0; } @@ -101,19 +432,38 @@ static int rockchip_sdhci_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); } -static const struct udevice_id arasan_sdhci_ids[] = { - { .compatible = "arasan,sdhci-5.1" }, +static const struct sdhci_data rk3399_data = { + .emmc_set_clock = rk3399_sdhci_emmc_set_clock, + .get_phy = rk3399_emmc_get_phy, + .emmc_phy_init = rk3399_emmc_phy_init, +}; + +static const struct sdhci_data rk3568_data = { + .emmc_set_clock = rk3568_sdhci_emmc_set_clock, + .get_phy = rk3568_emmc_get_phy, + .emmc_phy_init = rk3568_emmc_phy_init, +}; + +static const struct udevice_id sdhci_ids[] = { + { + .compatible = "arasan,sdhci-5.1", + .data = (ulong)&rk3399_data, + }, + { + .compatible = "rockchip,rk3568-dwcmshc", + .data = (ulong)&rk3568_data, + }, { } }; U_BOOT_DRIVER(arasan_sdhci_drv) = { - .name = "rockchip_rk3399_sdhci_5_1", + .name = "rockchip_sdhci_5_1", .id = UCLASS_MMC, - .of_match = arasan_sdhci_ids, - .of_to_plat = arasan_sdhci_of_to_plat, + .of_match = sdhci_ids, + .of_to_plat = rockchip_sdhci_of_to_plat, .ops = &sdhci_ops, .bind = rockchip_sdhci_bind, - .probe = arasan_sdhci_probe, + .probe = rockchip_sdhci_probe, .priv_auto = sizeof(struct rockchip_sdhc), .plat_auto = sizeof(struct rockchip_sdhc_plat), }; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 1b2ef37e92..b2291f7290 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -204,6 +204,12 @@ config SPI_FLASH_XMC Add support for various XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) SPI flash chips (XM25xxx) +config SPI_FLASH_XTX + bool "XTX SPI flash support" + help + Add support for various XTX (XTX Technology Limited) + SPI flash chips (XT25xxx). + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index cb3a08872d..4aef1ddd6e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -361,6 +361,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif +#ifdef CONFIG_SPI_FLASH_XTX + /* XTX Technology (Shenzhen) Limited */ + { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif { }, }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 5c2a60a214..e12699bec7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI on Renesas RCar Gen3 SoCs. This uses driver model and requires a device tree binding to operate. +config ROCKCHIP_SFC + bool "Rockchip SFC Driver" + help + Enable the Rockchip SFC Driver for SPI NOR flash. This device is + a limited purpose SPI controller for driving NOR flash on certain + Rockchip SoCs. This uses driver model and requires a device tree + binding to operate. + config ROCKCHIP_SPI bool "Rockchip SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 216e72c60f..d2f24bccef 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c new file mode 100644 index 0000000000..4e2b861f22 --- /dev/null +++ b/drivers/spi/rockchip_sfc.c @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Rockchip Serial Flash Controller Driver + * + * Copyright (c) 2017-2021, Rockchip Inc. + * Author: Shawn Lin + * Chris Morgan + * Jon Lin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System control */ +#define SFC_CTRL 0x0 +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) +#define SFC_CTRL_CMD_BITS_SHIFT 8 +#define SFC_CTRL_ADDR_BITS_SHIFT 10 +#define SFC_CTRL_DATA_BITS_SHIFT 12 + +/* Interrupt mask */ +#define SFC_IMR 0x4 +#define SFC_IMR_RX_FULL BIT(0) +#define SFC_IMR_RX_UFLOW BIT(1) +#define SFC_IMR_TX_OFLOW BIT(2) +#define SFC_IMR_TX_EMPTY BIT(3) +#define SFC_IMR_TRAN_FINISH BIT(4) +#define SFC_IMR_BUS_ERR BIT(5) +#define SFC_IMR_NSPI_ERR BIT(6) +#define SFC_IMR_DMA BIT(7) + +/* Interrupt clear */ +#define SFC_ICLR 0x8 +#define SFC_ICLR_RX_FULL BIT(0) +#define SFC_ICLR_RX_UFLOW BIT(1) +#define SFC_ICLR_TX_OFLOW BIT(2) +#define SFC_ICLR_TX_EMPTY BIT(3) +#define SFC_ICLR_TRAN_FINISH BIT(4) +#define SFC_ICLR_BUS_ERR BIT(5) +#define SFC_ICLR_NSPI_ERR BIT(6) +#define SFC_ICLR_DMA BIT(7) + +/* FIFO threshold level */ +#define SFC_FTLR 0xc +#define SFC_FTLR_TX_SHIFT 0 +#define SFC_FTLR_TX_MASK 0x1f +#define SFC_FTLR_RX_SHIFT 8 +#define SFC_FTLR_RX_MASK 0x1f + +/* Reset FSM and FIFO */ +#define SFC_RCVR 0x10 +#define SFC_RCVR_RESET BIT(0) + +/* Enhanced mode */ +#define SFC_AX 0x14 + +/* Address Bit number */ +#define SFC_ABIT 0x18 + +/* Interrupt status */ +#define SFC_ISR 0x1c +#define SFC_ISR_RX_FULL_SHIFT BIT(0) +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) +#define SFC_ISR_TX_FINISH_SHIFT BIT(4) +#define SFC_ISR_BUS_ERR_SHIFT BIT(5) +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) +#define SFC_ISR_DMA_SHIFT BIT(7) + +/* FIFO status */ +#define SFC_FSR 0x20 +#define SFC_FSR_TX_IS_FULL BIT(0) +#define SFC_FSR_TX_IS_EMPTY BIT(1) +#define SFC_FSR_RX_IS_EMPTY BIT(2) +#define SFC_FSR_RX_IS_FULL BIT(3) +#define SFC_FSR_TXLV_MASK GENMASK(12, 8) +#define SFC_FSR_TXLV_SHIFT 8 +#define SFC_FSR_RXLV_MASK GENMASK(20, 16) +#define SFC_FSR_RXLV_SHIFT 16 + +/* FSM status */ +#define SFC_SR 0x24 +#define SFC_SR_IS_IDLE 0x0 +#define SFC_SR_IS_BUSY 0x1 + +/* Raw interrupt status */ +#define SFC_RISR 0x28 +#define SFC_RISR_RX_FULL BIT(0) +#define SFC_RISR_RX_UNDERFLOW BIT(1) +#define SFC_RISR_TX_OVERFLOW BIT(2) +#define SFC_RISR_TX_EMPTY BIT(3) +#define SFC_RISR_TRAN_FINISH BIT(4) +#define SFC_RISR_BUS_ERR BIT(5) +#define SFC_RISR_NSPI_ERR BIT(6) +#define SFC_RISR_DMA BIT(7) + +/* Version */ +#define SFC_VER 0x2C +#define SFC_VER_3 0x3 +#define SFC_VER_4 0x4 +#define SFC_VER_5 0x5 + +/* Delay line controller resiter */ +#define SFC_DLL_CTRL0 0x3C +#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) +#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU +#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU + +/* Master trigger */ +#define SFC_DMA_TRIGGER 0x80 + +/* Src or Dst addr for master */ +#define SFC_DMA_ADDR 0x84 + +/* Length control register extension 32GB */ +#define SFC_LEN_CTRL 0x88 +#define SFC_LEN_CTRL_TRB_SEL 1 +#define SFC_LEN_EXT 0x8C + +/* Command */ +#define SFC_CMD 0x100 +#define SFC_CMD_IDX_SHIFT 0 +#define SFC_CMD_DUMMY_SHIFT 8 +#define SFC_CMD_DIR_SHIFT 12 +#define SFC_CMD_DIR_RD 0 +#define SFC_CMD_DIR_WR 1 +#define SFC_CMD_ADDR_SHIFT 14 +#define SFC_CMD_ADDR_0BITS 0 +#define SFC_CMD_ADDR_24BITS 1 +#define SFC_CMD_ADDR_32BITS 2 +#define SFC_CMD_ADDR_XBITS 3 +#define SFC_CMD_TRAN_BYTES_SHIFT 16 +#define SFC_CMD_CS_SHIFT 30 + +/* Address */ +#define SFC_ADDR 0x104 + +/* Data */ +#define SFC_DATA 0x108 + +/* The controller and documentation reports that it supports up to 4 CS + * devices (0-3), however I have only been able to test a single CS (CS 0) + * due to the configuration of my device. + */ +#define SFC_MAX_CHIPSELECT_NUM 4 + +/* The SFC can transfer max 16KB - 1 at one time + * we set it to 15.5KB here for alignment. + */ +#define SFC_MAX_IOSIZE_VER3 (512 * 31) + +#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) + +/* DMA is only enabled for large data transmission */ +#define SFC_DMA_TRANS_THRETHOLD (0x40) + +/* Maximum clock values from datasheet suggest keeping clock value under + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver + * has a minimum of 10MHz and a default of 80MHz which seems reasonable. + */ +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) + +struct rockchip_sfc { + void __iomem *regbase; + struct clk hclk; + struct clk clk; + u32 max_freq; + u32 speed; + bool use_dma; + u32 max_iosize; + u16 version; +}; + +static int rockchip_sfc_reset(struct rockchip_sfc *sfc) +{ + int err; + u32 status; + + writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); + + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, + !(status & SFC_RCVR_RESET), + 1000000); + if (err) + printf("SFC reset never finished\n"); + + /* Still need to clear the masked interrupt from RISR */ + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); + + debug("reset\n"); + + return err; +} + +static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) +{ + return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); +} + +static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) +{ + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) + return SFC_MAX_IOSIZE_VER4; + + return SFC_MAX_IOSIZE_VER3; +} + +static int rockchip_sfc_init(struct rockchip_sfc *sfc) +{ + writel(0, sfc->regbase + SFC_CTRL); + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) + writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); + + return 0; +} + +static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) +{ + struct rockchip_sfc *sfc = dev_get_plat(bus); + + sfc->regbase = dev_read_addr_ptr(bus); + if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) + sfc->use_dma = false; + else + sfc->use_dma = true; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + ret = clk_get_by_index(bus, 0, &sfc->clk); + if (ret < 0) { + printf("Could not get clock for %s: %d\n", bus->name, ret); + return ret; + } + + ret = clk_get_by_index(bus, 1, &sfc->hclk); + if (ret < 0) { + printf("Could not get ahb clock for %s: %d\n", bus->name, ret); + return ret; + } +#endif + + return 0; +} + +static int rockchip_sfc_probe(struct udevice *bus) +{ + struct rockchip_sfc *sfc = dev_get_plat(bus); + int ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable(&sfc->hclk); + if (ret) + debug("Enable ahb clock fail %s: %d\n", bus->name, ret); + + ret = clk_enable(&sfc->clk); + if (ret) + debug("Enable clock fail for %s: %d\n", bus->name, ret); + + ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ); + if (ret) + debug("Could not set sfc clock for %s: %d\n", bus->name, ret); +#endif + + ret = rockchip_sfc_init(sfc); + if (ret) + goto err_init; + + sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); + sfc->version = rockchip_sfc_get_version(sfc); + sfc->speed = SFC_DEFAULT_SPEED_HZ; + + return 0; + +err_init: +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&sfc->clk); + clk_disable(&sfc->hclk); +#endif + + return ret; +} + +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) +{ + u32 fsr = readl(sfc->regbase + SFC_FSR); + int level; + + if (wr) + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; + else + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; + + return level; +} + +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) +{ + unsigned long tbase = get_timer(0); + int level; + + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { + if (get_timer(tbase) > timeout) { + debug("%s fifo timeout\n", wr ? "write" : "read"); + return -ETIMEDOUT; + } + udelay(1); + } + + return level; +} + +static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) +{ + if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { + /* + * SFC not support output DUMMY cycles right after CMD cycles, so + * treat it as ADDR cycles. + */ + op->addr.nbytes = op->dummy.nbytes; + op->addr.buswidth = op->dummy.buswidth; + op->addr.val = 0xFFFFFFFFF; + + op->dummy.nbytes = 0; + } +} + +static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) +{ + unsigned long tbase; + + /* Wait for the DMA interrupt status */ + tbase = get_timer(0); + while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { + if (get_timer(tbase) > timeout) { + printf("dma timeout\n"); + rockchip_sfc_reset(sfc); + + return -ETIMEDOUT; + } + + udelay(1); + } + + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); + + return 0; +} + +static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, + struct spi_slave *mem, + const struct spi_mem_op *op, + u32 len) +{ + struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev); + u32 ctrl = 0, cmd = 0; + + /* set CMD */ + cmd = op->cmd.opcode; + ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); + + /* set ADDR */ + if (op->addr.nbytes) { + if (op->addr.nbytes == 4) { + cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; + } else if (op->addr.nbytes == 3) { + cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; + } else { + cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; + writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); + } + + ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); + } + + /* set DUMMY */ + if (op->dummy.nbytes) { + if (op->dummy.buswidth == 4) + cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; + else if (op->dummy.buswidth == 2) + cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; + else + cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; + } + + /* set DATA */ + if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ + writel(len, sfc->regbase + SFC_LEN_EXT); + else + cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; + if (len) { + if (op->data.dir == SPI_MEM_DATA_OUT) + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; + + ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); + } + if (!len && op->addr.nbytes) + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; + + /* set the Controller */ + ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; + cmd |= plat->cs << SFC_CMD_CS_SHIFT; + + debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", + op->addr.nbytes, op->addr.buswidth, + op->dummy.nbytes, op->dummy.buswidth); + debug("ctrl=%x cmd=%x addr=%llx len=%x\n", + ctrl, cmd, op->addr.val, len); + + writel(ctrl, sfc->regbase + SFC_CTRL); + writel(cmd, sfc->regbase + SFC_CMD); + if (op->addr.nbytes) + writel(op->addr.val, sfc->regbase + SFC_ADDR); + + return 0; +} + +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + int tx_level; + u32 write_words; + u32 tmp = 0; + + dwords = len >> 2; + while (dwords) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); + if (tx_level < 0) + return tx_level; + write_words = min_t(u32, tx_level, dwords); + writesl(sfc->regbase + SFC_DATA, buf, write_words); + buf += write_words << 2; + dwords -= write_words; + } + + /* write the rest non word aligned bytes */ + if (bytes) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); + if (tx_level < 0) + return tx_level; + memcpy(&tmp, buf, bytes); + writel(tmp, sfc->regbase + SFC_DATA); + } + + return len; +} + +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + u8 read_words; + int rx_level; + int tmp; + + /* word aligned access only */ + dwords = len >> 2; + while (dwords) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); + if (rx_level < 0) + return rx_level; + read_words = min_t(u32, rx_level, dwords); + readsl(sfc->regbase + SFC_DATA, buf, read_words); + buf += read_words << 2; + dwords -= read_words; + } + + /* read the rest non word aligned bytes */ + if (bytes) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); + if (rx_level < 0) + return rx_level; + tmp = readl(sfc->regbase + SFC_DATA); + memcpy(buf, &tmp, bytes); + } + + return len; +} + +static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) +{ + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); + writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); + + return len; +} + +static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, + const struct spi_mem_op *op, u32 len) +{ + debug("xfer_poll len=%x\n", len); + + if (op->data.dir == SPI_MEM_DATA_OUT) + return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); + else + return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); +} + +static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, + const struct spi_mem_op *op, u32 len) +{ + struct bounce_buffer bb; + unsigned int bb_flags; + void *dma_buf; + int ret; + + debug("xfer_dma len=%x\n", len); + + if (op->data.dir == SPI_MEM_DATA_OUT) { + dma_buf = (void *)op->data.buf.out; + bb_flags = GEN_BB_READ; + } else { + dma_buf = (void *)op->data.buf.in; + bb_flags = GEN_BB_WRITE; + } + + ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); + if (ret) + return ret; + + ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); + rockchip_sfc_wait_for_dma_finished(sfc, len * 10); + bounce_buffer_stop(&bb); + + return ret; +} + +static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) +{ + unsigned long tbase = get_timer(0); + int ret = 0; + u32 timeout = timeout_us; + + while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) { + if (get_timer(tbase) > timeout) { + printf("wait sfc idle timeout\n"); + rockchip_sfc_reset(sfc); + + return -ETIMEDOUT; + } + + udelay(1); + } + + return ret; +} + +static int rockchip_sfc_exec_op(struct spi_slave *mem, + const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); + u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); + int ret; + +#if CONFIG_IS_ENABLED(CLK) + if (unlikely(mem->max_hz != sfc->speed)) { + ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ, + (uint)SFC_MAX_SPEED_HZ)); + if (ret < 0) { + printf("set_freq=%dHz fail, check if it's the cru support level\n", + mem->max_hz); + return ret; + } + + sfc->max_freq = mem->max_hz; + sfc->speed = mem->max_hz; + debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed); + } +#endif + + rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); + + rockchip_sfc_xfer_setup(sfc, mem, op, len); + if (len) { + if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD) + ret = rockchip_sfc_xfer_data_dma(sfc, op, len); + else + ret = rockchip_sfc_xfer_data_poll(sfc, op, len); + + if (ret != len) { + printf("xfer data failed ret %d dir %d\n", ret, op->data.dir); + + return -EIO; + } + } + + return rockchip_sfc_xfer_done(sfc, 100000); +} + +static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); + + op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); + return 0; +} + +static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) +{ + /* We set up speed later for each transmission. + */ + return 0; +} + +static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { + .adjust_op_size = rockchip_sfc_adjust_op_size, + .exec_op = rockchip_sfc_exec_op, +}; + +static const struct dm_spi_ops rockchip_sfc_ops = { + .mem_ops = &rockchip_sfc_mem_ops, + .set_speed = rockchip_sfc_set_speed, + .set_mode = rockchip_sfc_set_mode, +}; + +static const struct udevice_id rockchip_sfc_ids[] = { + { .compatible = "rockchip,sfc"}, + {}, +}; + +U_BOOT_DRIVER(rockchip_sfc_driver) = { + .name = "rockchip_sfc", + .id = UCLASS_SPI, + .of_match = rockchip_sfc_ids, + .ops = &rockchip_sfc_ops, + .of_to_plat = rockchip_sfc_ofdata_to_platdata, + .plat_auto = sizeof(struct rockchip_sfc), + .probe = rockchip_sfc_probe, +}; diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 0b9e24d1db..ba7061a287 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -14,11 +14,11 @@ #ifndef CONFIG_SPL_BUILD -/* First try to boot from SD (index 0), then eMMC (index 1) */ +/* First try to boot from SD (index 1), then eMMC (index 0) */ #if CONFIG_IS_ENABLED(CMD_MMC) #define BOOT_TARGET_MMC(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) #else #define BOOT_TARGET_MMC(func) #endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 1e7931da0c..afad90680f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner @@ -59,12 +59,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 @@ -125,8 +127,12 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 0000000000..93d23dfba3 --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__ + +/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3188_PD_RTC 12 + +#endif