Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 15:14:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

Browse source 
- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSBI
- sifive: fu540: Add gpio-restart support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup
This commit is contained in:
Tom Rini 2020-07-03 12:00:36 -04:00
commit 06e1321553
12 changed files with 129 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/riscv/Kconfig
View file

@ -273,4 +273,7 @@ config STACK_SIZE_SHIFT
int
default 14
config OF_BOARD_FIXUP
default y if OF_SEPARATE
endmenu

1
arch/riscv/cpu/fu540/Makefile
View file

@ -8,4 +8,5 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif

53
arch/riscv/cpu/fu540/cache.c Normal file
View file

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node = (-FDT_ERR_NOTFOUND);
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu540-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr(blob, node, "reg");
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}

10
arch/riscv/dts/fu540-c000-u-boot.dtsi
View file

@ -27,7 +27,7 @@
clocks = <&prci PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu2_intc: interrupt-controller {
u-boot,dm-spl;
u-boot,dm-spl;
};
};
cpu3: cpu@3 {
@ -50,7 +50,7 @@
u-boot,dm-spl;
otp: otp@10070000 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x10070000 0x0 0x0FFF>;
reg = <0x0 0x10070000 0x0 0x1000>;
fuse-count = <0x1000>;
};
clint@2000000 {
@ -63,7 +63,7 @@
compatible = "sifive,fu540-c000-ddr";
reg = <0x0 0x100b0000 0x0 0x0800
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x0fff>;
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
u-boot,dm-spl;
@ -87,3 +87,7 @@
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125000000>;
};
&l2cache {
status = "okay";
};

14
arch/riscv/include/asm/arch-fu540/cache.h Normal file
View file

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */

2
arch/riscv/lib/Makefile
View file

@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
obj-y += interrupts.o
ifeq ($(CONFIG_$(SPL_)SYSRESET),)
obj-y += reset.o
endif
obj-y += setjmp.o
obj-$(CONFIG_$(SPL_)SMP) += smp.o
obj-$(CONFIG_SPL_BUILD) += spl.o

46
arch/riscv/lib/fdt_fixup.c
View file

@ -4,6 +4,8 @@
*
*/
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
#include <fdt_support.h>
#include <log.h>
@ -37,18 +39,30 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
offset = fdt_path_offset(src, "/reserved-memory");
if (offset < 0) {
printf("No reserved memory region found in source FDT\n");
log_debug("No reserved memory region found in source FDT\n");
return 0;
}
/*
* Extend the FDT by the following estimated size:
*
* Each PMP memory region entry occupies 64 bytes.
* With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
*/
err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);
if (err < 0) {
printf("Device Tree can't be expanded to accommodate new node");
return err;
}
fdt_for_each_subnode(node, src, offset) {
name = fdt_get_name(src, node, NULL);
addr = fdtdec_get_addr_size_auto_noparent(src, node,
"reg", 0, &size,
false);
addr = fdtdec_get_addr_size_auto_parent(src, offset, node,
"reg", 0, &size,
false);
if (addr == FDT_ADDR_T_NONE) {
debug("failed to read address/size for %s\n", name);
log_debug("failed to read address/size for %s\n", name);
continue;
}
strncpy(basename, name, max_len);
@ -62,8 +76,8 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
pmp_mem.end = addr + size - 1;
err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
&phandle);
if (err < 0) {
printf("failed to add reserved memory: %d\n", err);
if (err < 0 && err != -FDT_ERR_EXISTS) {
log_err("failed to add reserved memory: %d\n", err);
return err;
}
if (!fdt_getprop(src, node, "no-map", NULL))
@ -82,10 +96,9 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
* @fdt: Pointer to the device tree in which reserved memory node needs to be
* added.
*
* In RISC-V, any board compiled with OF_SEPARATE needs to copy the reserved
* memory node from the device tree provided by the firmware to the device tree
* used by U-Boot. This is a common function that individual board fixup
* functions can invoke.
* In RISC-V, any board needs to copy the reserved memory node from the device
* tree provided by the firmware to the device tree used by U-Boot. This is a
* common function that individual board fixup functions can invoke.
*
* Return: 0 on success or error otherwise.
*/
@ -95,6 +108,11 @@ int riscv_board_reserved_mem_fixup(void *fdt)
void *src_fdt_addr;
src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0);
/* avoid the copy if we are using the same device tree */
if (src_fdt_addr == fdt)
return 0;
err = riscv_fdt_copy_resv_mem_node(src_fdt_addr, fdt);
if (err < 0)
return err;
@ -109,7 +127,7 @@ int board_fix_fdt(void *fdt)
err = riscv_board_reserved_mem_fixup(fdt);
if (err < 0) {
printf("failed to fixup DT for reserved memory: %d\n", err);
log_err("failed to fixup DT for reserved memory: %d\n", err);
return err;
}
@ -127,14 +145,14 @@ int arch_fixup_fdt(void *blob)
size = fdt_totalsize(blob);
err = fdt_open_into(blob, blob, size + 32);
if (err < 0) {
printf("Device Tree can't be expanded to accommodate new node");
log_err("Device Tree can't be expanded to accommodate new node");
return err;
}
chosen_offset = fdt_path_offset(blob, "/chosen");
if (chosen_offset < 0) {
err = fdt_add_subnode(blob, 0, "chosen");
if (err < 0) {
printf("chosen node can not be added\n");
log_err("chosen node cannot be added\n");
return err;
}
}

2
board/sifive/fu540/Kconfig
View file

@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SMP
imply MISC
imply SIFIVE_OTP
imply SYSRESET
imply SYSRESET_GPIO
endif

10
board/sifive/fu540/fu540.c
View file

@ -15,6 +15,7 @@
#include <linux/io.h>
#include <misc.h>
#include <spl.h>
#include <asm/arch/cache.h>
/*
* This define is a value used for error/unknown serial.
@ -114,7 +115,14 @@ int misc_init_r(void)
int board_init(void)
{
/* For now nothing to do here. */
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
return 0;
}

2
common/spl/spl_opensbi.c
View file

@ -56,7 +56,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
/* Find U-Boot image in /fit-images */
ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node);
if (ret) {
pr_err("Can't find U-Boot node, %d", ret);
pr_err("Can't find U-Boot node, %d\n", ret);
hang();
}

1
configs/sifive_fu540_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y

10
doc/board/emulation/qemu-riscv.rst
View file

@ -40,11 +40,11 @@ The minimal QEMU command line to get U-Boot up and running is:
- For 32-bit RISC-V::
qemu-system-riscv32 -nographic -machine virt -kernel u-boot
qemu-system-riscv32 -nographic -machine virt -bios u-boot
- For 64-bit RISC-V::
qemu-system-riscv64 -nographic -machine virt -kernel u-boot
qemu-system-riscv64 -nographic -machine virt -bios u-boot
The commands above create targets with 128MiB memory by default.
A freely configurable amount of RAM can be created via the '-m'
@ -56,7 +56,7 @@ For instructions on how to run U-Boot in supervisor mode on QEMU
with OpenSBI, see the documentation available with OpenSBI:
https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
These have been tested in QEMU 4.2.0.
These have been tested in QEMU 5.0.0.
Running U-Boot SPL
------------------
@ -98,10 +98,10 @@ configurations are:
- For 32-bit RISC-V::
qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
qemu-system-riscv32 -nographic -machine virt -bios spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x80200000
- For 64-bit RISC-V::
qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
qemu-system-riscv64 -nographic -machine virt -bios spl/u-boot-spl \
-device loader,file=u-boot.itb,addr=0x80200000