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Merge branch '2023-05-31-code-cleanups' into next

Browse source 
- Correct some header double-inclusion guards and remove some dead (or
  in the case of ti816x, unmaintained) code.
This commit is contained in:
Tom Rini 2023-05-31 12:32:38 -04:00
commit 06af8fcf6c
88 changed files with 12 additions and 8046 deletions
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1
arch/arm/dts/Makefile
View file

@ -449,7 +449,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am4372-generic.dtb \
am437x-cm-t43.dtb
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \

12
arch/arm/dts/dm8168-evm-u-boot.dtsi
View file

@ -1,12 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dm8168-evm U-Boot Additions
*
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
/ {
ocp {
bootph-all;
};
};

171
arch/arm/dts/dm8168-evm.dts
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@ -1,171 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "dm816x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "DM8168 EVM";
compatible = "ti,dm8168-evm", "ti,dm8168";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000 /* 1 GB */
0xc0000000 0x40000000>; /* 1 GB */
};
/* FDC6331L controlled by SD_POW pin */
vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&dm816x_pinmux {
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */
DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */
DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */
DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */
>;
};
mmc_pins: pinmux_mmc_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
>;
};
usb0_pins: pinmux_usb0_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
>;
};
};
&i2c1 {
extgpio0: pcf8575@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c2 {
extgpio1: pcf8575@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&gpmc {
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
linux,mtd-name= "micron,mt29f2g16aadwp";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
partition@0 {
label = "X-Loader";
reg = <0 0x80000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x780000 0xf880000>;
};
};
};
&mcspi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi1_pins>;
flash@0 {
compatible = "w25x32";
spi-max-frequency = <48000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
/* At least dm8168-evm rev c won't support multipoint, later may */
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
mentor,multipoint = <0>;
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
mentor,multipoint = <0>;
};

246
arch/arm/dts/dm816x-clocks.dtsi
View file

@ -1,246 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&scrm {
main_fapll: main_fapll {
#clock-cells = <1>;
compatible = "ti,dm816-fapll-clock";
reg = <0x400 0x40>;
clocks = <&sys_clkin_ck &sys_clkin_ck>;
clock-indices = <1>, <2>, <3>, <4>, <5>,
<6>, <7>;
clock-output-names = "main_pll_clk1",
"main_pll_clk2",
"main_pll_clk3",
"main_pll_clk4",
"main_pll_clk5",
"main_pll_clk6",
"main_pll_clk7";
};
ddr_fapll: ddr_fapll {
#clock-cells = <1>;
compatible = "ti,dm816-fapll-clock";
reg = <0x440 0x30>;
clocks = <&sys_clkin_ck &sys_clkin_ck>;
clock-indices = <1>, <2>, <3>, <4>;
clock-output-names = "ddr_pll_clk1",
"ddr_pll_clk2",
"ddr_pll_clk3",
"ddr_pll_clk4";
};
video_fapll: video_fapll {
#clock-cells = <1>;
compatible = "ti,dm816-fapll-clock";
reg = <0x470 0x30>;
clocks = <&sys_clkin_ck &sys_clkin_ck>;
clock-indices = <1>, <2>, <3>;
clock-output-names = "video_pll_clk1",
"video_pll_clk2",
"video_pll_clk3";
};
audio_fapll: audio_fapll {
#clock-cells = <1>;
compatible = "ti,dm816-fapll-clock";
reg = <0x4a0 0x30>;
clocks = <&main_fapll 7>, < &sys_clkin_ck>;
clock-indices = <1>, <2>, <3>, <4>, <5>;
clock-output-names = "audio_pll_clk1",
"audio_pll_clk2",
"audio_pll_clk3",
"audio_pll_clk4",
"audio_pll_clk5";
};
};
&scrm_clocks {
secure_32k_ck: secure_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
tclkin_ck: tclkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
};
/* 0x48180000 */
&prcm_clocks {
clkout_pre_ck: clkout_pre_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
&audio_fapll 1>;
reg = <0x100>;
};
clkout_div_ck: clkout_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout_pre_ck>;
ti,bit-shift = <3>;
ti,max-div = <8>;
reg = <0x100>;
};
clkout_ck: clkout_ck@100 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout_div_ck>;
ti,bit-shift = <7>;
reg = <0x100>;
};
/* CM_DPLL clocks p1795 */
sysclk1_ck: sysclk1_ck@300 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 1>;
ti,max-div = <7>;
reg = <0x0300>;
};
sysclk2_ck: sysclk2_ck@304 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 2>;
ti,max-div = <7>;
reg = <0x0304>;
};
sysclk3_ck: sysclk3_ck@308 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 3>;
ti,max-div = <7>;
reg = <0x0308>;
};
sysclk4_ck: sysclk4_ck@30c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 4>;
ti,max-div = <1>;
reg = <0x030c>;
};
sysclk5_ck: sysclk5_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sysclk4_ck>;
ti,max-div = <1>;
reg = <0x0310>;
};
sysclk6_ck: sysclk6_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 4>;
ti,dividers = <2>, <4>;
reg = <0x0314>;
};
sysclk10_ck: sysclk10_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&ddr_fapll 2>;
ti,max-div = <7>;
reg = <0x0324>;
};
sysclk24_ck: sysclk24_ck@3b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 5>;
ti,max-div = <7>;
reg = <0x03b4>;
};
mpu_ck: mpu_ck@15dc {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sysclk2_ck>;
ti,bit-shift = <1>;
reg = <0x15dc>;
};
audio_pll_a_ck: audio_pll_a_ck@35c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&audio_fapll 1>;
ti,max-div = <7>;
reg = <0x035c>;
};
sysclk18_ck: sysclk18_ck@378 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
reg = <0x0378>;
};
timer1_fck: timer1_fck@390 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0390>;
};
timer2_fck: timer2_fck@394 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0394>;
};
timer3_fck: timer3_fck@398 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0398>;
};
timer4_fck: timer4_fck@39c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x039c>;
};
timer5_fck: timer5_fck@3a0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x03a0>;
};
timer6_fck: timer6_fck@3a4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x03a4>;
};
timer7_fck: timer7_fck@3a8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x03a8>;
};
};

517
arch/arm/dts/dm816x.dtsi
View file

@ -1,517 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>
/ {
compatible = "ti,dm816";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
ethernet0 = &eth0;
ethernet1 = &eth1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
device_type = "cpu";
reg = <0>;
};
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
};
/*
* XXX: Use a flat representation of the dm816x interconnect.
* The real dm816x interconnect network is quite complex. Since
* it will not bring real advantage to represent that in DT
* for the moment, just use a fake OCP bus entry to represent
* the whole bus hierarchy.
*/
ocp {
compatible = "simple-bus";
reg = <0x44000000 0x10000>;
interrupts = <9 10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
prcm: prcm@48180000 {
compatible = "ti,dm816-prcm", "simple-bus";
reg = <0x48180000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48180000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@48140000 {
compatible = "ti,dm816-scrm", "simple-bus";
reg = <0x48140000 0x21000>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges = <0 0x48140000 0x21000>;
dm816x_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x50a>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xf>;
};
/* Device Configuration Registers */
scm_conf: syscon@600 {
compatible = "syscon", "simple-bus";
reg = <0x600 0x110>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x110>;
usb_phy0: usb-phy@20 {
compatible = "ti,dm8168-usb-phy";
reg = <0x20 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};
usb_phy1: usb-phy@28 {
compatible = "ti,dm8168-usb-phy";
reg = <0x28 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x40>;
interrupts = <12 13 14>;
#dma-cells = <1>;
};
elm: elm@48080000 {
compatible = "ti,816-elm";
ti,hwmods = "elm";
reg = <0x48080000 0x2000>;
interrupts = <4>;
};
gpio1: gpio@48032000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
ti,gpio-always-on;
reg = <0x48032000 0x1000>;
interrupts = <96>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
ti,gpio-always-on;
reg = <0x4804c000 0x1000>;
interrupts = <98>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x2000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <100>;
dmas = <&edma 52>;
dma-names = "rxtx";
gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
i2c1: i2c@48028000 {
compatible = "ti,omap4-i2c";
ti,hwmods = "i2c1";
reg = <0x48028000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
dmas = <&edma 58 &edma 59>;
dma-names = "tx", "rx";
};
i2c2: i2c@4802a000 {
compatible = "ti,omap4-i2c";
ti,hwmods = "i2c2";
reg = <0x4802a000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
dmas = <&edma 60 &edma 61>;
dma-names = "tx", "rx";
};
intc: interrupt-controller@48200000 {
compatible = "ti,dm816-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x48200000 0x1000>;
};
rtc: rtc@480c0000 {
compatible = "ti,am3352-rtc", "ti,da830-rtc";
reg = <0x480c0000 0x1000>;
interrupts = <75 76>;
ti,hwmods = "rtc";
};
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480c8000 0x2000>;
interrupts = <77>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <0 0 0>;
};
};
spinbox: spinbox@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x2000>;
ti,hwmods = "spinbox";
#hwlock-cells = <1>;
};
mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4a100800 0x100>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
eth0: ethernet@4a100000 {
compatible = "ti,dm816-emac";
ti,hwmods = "emac0";
reg = <0x4a100000 0x800
0x4a100900 0x3700>;
clocks = <&sysclk24_ck>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0>;
ti,davinci-ctrl-mod-reg-offset = <0x900>;
ti,davinci-ctrl-ram-offset = <0x2000>;
ti,davinci-ctrl-ram-size = <0x2000>;
interrupts = <40 41 42 43>;
phy-handle = <&phy0>;
};
eth1: ethernet@4a120000 {
compatible = "ti,dm816-emac";
ti,hwmods = "emac1";
reg = <0x4a120000 0x4000>;
clocks = <&sysclk24_ck>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0>;
ti,davinci-ctrl-mod-reg-offset = <0x900>;
ti,davinci-ctrl-ram-offset = <0x2000>;
ti,davinci-ctrl-ram-size = <0x2000>;
interrupts = <44 45 46 47>;
phy-handle = <&phy1>;
};
mcspi1: spi@48030000 {
compatible = "ti,omap4-mcspi";
reg = <0x48030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <65>;
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17
&edma 18 &edma 19
&edma 20 &edma 21
&edma 22 &edma 23>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mmc1: mmc@48060000 {
compatible = "ti,omap4-hsmmc";
reg = <0x48060000 0x11000>;
ti,hwmods = "mmc1";
interrupts = <64>;
dmas = <&edma 24 &edma 25>;
dma-names = "tx", "rx";
};
timer1: timer@4802e000 {
compatible = "ti,dm816-timer";
reg = <0x4802e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
timer2: timer@48040000 {
compatible = "ti,dm816-timer";
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
};
timer3: timer@48042000 {
compatible = "ti,dm816-timer";
reg = <0x48042000 0x2000>;
interrupts = <69>;
ti,hwmods = "timer3";
};
timer4: timer@48044000 {
compatible = "ti,dm816-timer";
reg = <0x48044000 0x2000>;
interrupts = <92>;
ti,hwmods = "timer4";
ti,timer-pwm;
};
timer5: timer@48046000 {
compatible = "ti,dm816-timer";
reg = <0x48046000 0x2000>;
interrupts = <93>;
ti,hwmods = "timer5";
ti,timer-pwm;
};
timer6: timer@48048000 {
compatible = "ti,dm816-timer";
reg = <0x48048000 0x2000>;
interrupts = <94>;
ti,hwmods = "timer6";
ti,timer-pwm;
};
timer7: timer@4804a000 {
compatible = "ti,dm816-timer";
reg = <0x4804a000 0x2000>;
interrupts = <95>;
ti,hwmods = "timer7";
ti,timer-pwm;
};
uart1: serial@48020000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
reg = <0x48020000 0x2000>;
clock-frequency = <48000000>;
interrupts = <72>;
dmas = <&edma 26 &edma 27>;
dma-names = "tx", "rx";
};
uart2: serial@48022000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
reg = <0x48022000 0x2000>;
clock-frequency = <48000000>;
interrupts = <73>;
dmas = <&edma 28 &edma 29>;
dma-names = "tx", "rx";
};
uart3: serial@48024000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
reg = <0x48024000 0x2000>;
clock-frequency = <48000000>;
interrupts = <74>;
dmas = <&edma 30 &edma 31>;
dma-names = "tx", "rx";
};
/* NOTE: USB needs a transceiver driver for phys to work */
usb: usb_otg_hs@47401000 {
compatible = "ti,am33xx-usb";
reg = <0x47401000 0x400000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "usb_otg_hs";
usb0: usb@47401000 {
compatible = "ti,musb-dm816";
reg = <0x47401400 0x400
0x47401000 0x200>;
reg-names = "mc", "control";
interrupts = <18>;
interrupt-names = "mc";
dr_mode = "host";
interface-type = <0>;
phys = <&usb_phy0>;
phy-names = "usb2-phy";
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;
mentor,power = <500>;
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
&cppi41dma 2 0 &cppi41dma 3 0
&cppi41dma 4 0 &cppi41dma 5 0
&cppi41dma 6 0 &cppi41dma 7 0
&cppi41dma 8 0 &cppi41dma 9 0
&cppi41dma 10 0 &cppi41dma 11 0
&cppi41dma 12 0 &cppi41dma 13 0
&cppi41dma 14 0 &cppi41dma 0 1
&cppi41dma 1 1 &cppi41dma 2 1
&cppi41dma 3 1 &cppi41dma 4 1
&cppi41dma 5 1 &cppi41dma 6 1
&cppi41dma 7 1 &cppi41dma 8 1
&cppi41dma 9 1 &cppi41dma 10 1
&cppi41dma 11 1 &cppi41dma 12 1
&cppi41dma 13 1 &cppi41dma 14 1>;
dma-names =
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
"rx14", "rx15",
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
"tx14", "tx15";
};
usb1: usb@47401800 {
compatible = "ti,musb-dm816";
reg = <0x47401c00 0x400
0x47401800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
dr_mode = "host";
interface-type = <0>;
phys = <&usb_phy1>;
phy-names = "usb2-phy";
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;
mentor,power = <500>;
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
&cppi41dma 17 0 &cppi41dma 18 0
&cppi41dma 19 0 &cppi41dma 20 0
&cppi41dma 21 0 &cppi41dma 22 0
&cppi41dma 23 0 &cppi41dma 24 0
&cppi41dma 25 0 &cppi41dma 26 0
&cppi41dma 27 0 &cppi41dma 28 0
&cppi41dma 29 0 &cppi41dma 15 1
&cppi41dma 16 1 &cppi41dma 17 1
&cppi41dma 18 1 &cppi41dma 19 1
&cppi41dma 20 1 &cppi41dma 21 1
&cppi41dma 22 1 &cppi41dma 23 1
&cppi41dma 24 1 &cppi41dma 25 1
&cppi41dma 26 1 &cppi41dma 27 1
&cppi41dma 28 1 &cppi41dma 29 1>;
dma-names =
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
"rx14", "rx15",
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
"tx14", "tx15";
};
cppi41dma: dma-controller@47402000 {
compatible = "ti,am3359-cppi41";
reg = <0x47400000 0x1000
0x47402000 0x1000
0x47403000 0x1000
0x47404000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
};
};
wd_timer2: wd_timer@480c2000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer";
reg = <0x480c2000 0x1000>;
interrupts = <0>;
};
};
};
#include "dm816x-clocks.dtsi"

4
arch/arm/include/asm/arch-am33xx/clock.h
View file

@ -13,10 +13,6 @@
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_TI816X)
#include <asm/arch/clock_ti81xx.h>
#endif
#define LDELAY 1000000
/*CM_<clock_domain>__CLKCTRL */

118
arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
View file

@ -1,118 +0,0 @@
/*
* ti81xx.h
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
*
* This file is released under the terms of GPL v2 and any later version.
* See the file COPYING in the root directory of the source tree for details.
*/
#ifndef _CLOCK_TI81XX_H_
#define _CLOCK_TI81XX_H_
#define PRCM_MOD_EN 0x2
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
struct cm_def {
unsigned int resv0[2];
unsigned int l3fastclkstctrl;
unsigned int resv1[1];
unsigned int pciclkstctrl;
unsigned int resv2[1];
unsigned int ducaticlkstctrl;
unsigned int resv3[1];
unsigned int emif0clkctrl;
unsigned int emif1clkctrl;
unsigned int dmmclkctrl;
unsigned int fwclkctrl;
unsigned int resv4[10];
unsigned int usbclkctrl;
unsigned int resv5[1];
unsigned int sataclkctrl;
unsigned int resv6[4];
unsigned int ducaticlkctrl;
unsigned int pciclkctrl;
};
struct cm_alwon {
unsigned int l3slowclkstctrl;
unsigned int ethclkstctrl;
unsigned int l3medclkstctrl;
unsigned int mmu_clkstctrl;
unsigned int mmucfg_clkstctrl;
unsigned int ocmc0clkstctrl;
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkstctrl;
#endif
unsigned int mpuclkstctrl;
unsigned int sysclk4clkstctrl;
unsigned int sysclk5clkstctrl;
unsigned int sysclk6clkstctrl;
unsigned int rtcclkstctrl;
unsigned int l3fastclkstctrl;
unsigned int resv0[67];
unsigned int mcasp0clkctrl;
unsigned int mcasp1clkctrl;
unsigned int mcasp2clkctrl;
unsigned int mcbspclkctrl;
unsigned int uart0clkctrl;
unsigned int uart1clkctrl;
unsigned int uart2clkctrl;
unsigned int gpio0clkctrl;
unsigned int gpio1clkctrl;
unsigned int i2c0clkctrl;
unsigned int i2c1clkctrl;
#if defined(CONFIG_TI816X)
unsigned int resv1[1];
unsigned int timer1clkctrl;
unsigned int timer2clkctrl;
unsigned int timer3clkctrl;
unsigned int timer4clkctrl;
unsigned int timer5clkctrl;
unsigned int timer6clkctrl;
unsigned int timer7clkctrl;
#endif
unsigned int wdtimerclkctrl;
unsigned int spiclkctrl;
unsigned int mailboxclkctrl;
unsigned int spinboxclkctrl;
unsigned int mmudataclkctrl;
unsigned int resv2[2];
unsigned int mmucfgclkctrl;
#if defined(CONFIG_TI816X)
unsigned int resv3[1];
unsigned int sdioclkctrl;
#endif
unsigned int ocmc0clkctrl;
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkctrl;
#endif
unsigned int resv4[2];
unsigned int controlclkctrl;
unsigned int resv5[2];
unsigned int gpmcclkctrl;
unsigned int ethernet0clkctrl;
unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
#if defined(CONFIG_TI816X)
unsigned int resv6[1];
#endif
unsigned int l3clkctrl;
unsigned int l4hsclkctrl;
unsigned int l4lsclkctrl;
unsigned int rtcclkctrl;
unsigned int tpccclkctrl;
unsigned int tptc0clkctrl;
unsigned int tptc1clkctrl;
unsigned int tptc2clkctrl;
unsigned int tptc3clkctrl;
#if defined(CONFIG_TI816X)
unsigned int sr0clkctrl;
unsigned int sr1clkctrl;
#endif
};
#endif /* _CLOCK_TI81XX_H_ */

6
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -369,15 +369,9 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
#ifdef CONFIG_TI816X
void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs,
const struct dmm_lisa_map_regs *lisa_regs, int nrs);
#else
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr);
#endif
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
#endif /* _DDR_DEFS_H */

37
arch/arm/include/asm/arch-am33xx/emac_defs.h
View file

@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010 Texas Instruments
*
* Based on:
*
* ----------------------------------------------------------------------------
*
* dm644x_emac.h
*
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
*
* Copyright (C) 2005 Texas Instruments.
*
* ----------------------------------------------------------------------------
*
*/
#ifndef _EMAC_DEFS_H_
#define _EMAC_DEFS_H_
#ifdef CONFIG_TI816X
#define EMAC_BASE_ADDR (0x4A100000)
#define EMAC_WRAPPER_BASE_ADDR (0x4A100900)
#define EMAC_WRAPPER_RAM_ADDR (0x4A102000)
#define EMAC_MDIO_BASE_ADDR (0x4A100800)
#define EMAC_MDIO_BUS_FREQ (250000000UL)
#define EMAC_MDIO_CLOCK_FREQ (2000000UL)
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
#define DAVINCI_EMAC_VERSION2
#define DAVINCI_EMAC_GIG_ENABLE
#endif
#endif /* _EMAC_DEFS_H_ */

2
arch/arm/include/asm/arch-am33xx/hardware.h
View file

@ -14,8 +14,6 @@
#include <asm/arch/omap.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/hardware_am33xx.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/hardware_ti816x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/hardware_am43xx.h>
#endif

62
arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
View file

@ -1,62 +0,0 @@
/*
* hardware_ti816x.h
*
* TI816x hardware specific header
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
* Based on TI-PSP-04.00.02.14
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AM33XX_HARDWARE_TI816X_H
#define __AM33XX_HARDWARE_TI816X_H
/* UART */
#define UART0_BASE 0x48020000
#define UART1_BASE 0x48022000
#define UART2_BASE 0x48024000
/* Watchdog Timer */
#define WDT_BASE 0x480C2000
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#define PRM_RSTST (PRM_RSTCTRL + 8)
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x48198358
#define VTP1_CTRL_ADDR 0x4819A358
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x48198000
#define DDR_PHY_DATA_ADDR 0x481980C8
#define DDR_PHY_CMD_ADDR2 0x4819A000
#define DDR_PHY_DATA_ADDR2 0x4819A0C8
#define DDR_DATA_REGS_NR 4
#define DDRPHY_0_CONFIG_BASE 0x48198000
#define DDRPHY_1_CONFIG_BASE 0x4819A000
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
/* RTC base address */
#define RTC_BASE 0x480C0000
#endif /* __AM33XX_HARDWARE_TI816X_H */

5
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
View file

@ -24,9 +24,4 @@
#define OMAP_HSMMC1_BASE 0x48060000
#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI816X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 48 /* MHz */
#endif
#endif /* MMC_HOST_DEF_H */

2
arch/arm/include/asm/arch-am33xx/mux.h
View file

@ -20,8 +20,6 @@
#ifdef CONFIG_AM33XX
#include <asm/arch/mux_am33xx.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/mux_ti816x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/mux_am43xx.h>
#endif

362
arch/arm/include/asm/arch-am33xx/mux_ti816x.h
View file

@ -1,362 +0,0 @@
/*
* mux_ti816x.h
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MUX_TI816X_H_
#define _MUX_TI816X_H_
#include <asm/io.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) (val) /* used for Readability */
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int pincntl1;
int pincntl2;
int pincntl3;
int pincntl4;
int pincntl5;
int pincntl6;
int pincntl7;
int pincntl8;
int pincntl9;
int pincntl10;
int pincntl11;
int pincntl12;
int pincntl13;
int pincntl14;
int pincntl15;
int pincntl16;
int pincntl17;
int pincntl18;
int pincntl19;
int pincntl20;
int pincntl21;
int pincntl22;
int pincntl23;
int pincntl24;
int pincntl25;
int pincntl26;
int pincntl27;
int pincntl28;
int pincntl29;
int pincntl30;
int pincntl31;
int pincntl32;
int pincntl33;
int pincntl34;
int pincntl35;
int pincntl36;
int pincntl37;
int pincntl38;
int pincntl39;
int pincntl40;
int pincntl41;
int pincntl42;
int pincntl43;
int pincntl44;
int pincntl45;
int pincntl46;
int pincntl47;
int pincntl48;
int pincntl49;
int pincntl50;
int pincntl51;
int pincntl52;
int pincntl53;
int pincntl54;
int pincntl55;
int pincntl56;
int pincntl57;
int pincntl58;
int pincntl59;
int pincntl60;
int pincntl61;
int pincntl62;
int pincntl63;
int pincntl64;
int pincntl65;
int pincntl66;
int pincntl67;
int pincntl68;
int pincntl69;
int pincntl70;
int pincntl71;
int pincntl72;
int pincntl73;
int pincntl74;
int pincntl75;
int pincntl76;
int pincntl77;
int pincntl78;
int pincntl79;
int pincntl80;
int pincntl81;
int pincntl82;
int pincntl83;
int pincntl84;
int pincntl85;
int pincntl86;
int pincntl87;
int pincntl88;
int pincntl89;
int pincntl90;
int pincntl91;
int pincntl92;
int pincntl93;
int pincntl94;
int pincntl95;
int pincntl96;
int pincntl97;
int pincntl98;
int pincntl99;
int pincntl100;
int pincntl101;
int pincntl102;
int pincntl103;
int pincntl104;
int pincntl105;
int pincntl106;
int pincntl107;
int pincntl108;
int pincntl109;
int pincntl110;
int pincntl111;
int pincntl112;
int pincntl113;
int pincntl114;
int pincntl115;
int pincntl116;
int pincntl117;
int pincntl118;
int pincntl119;
int pincntl120;
int pincntl121;
int pincntl122;
int pincntl123;
int pincntl124;
int pincntl125;
int pincntl126;
int pincntl127;
int pincntl128;
int pincntl129;
int pincntl130;
int pincntl131;
int pincntl132;
int pincntl133;
int pincntl134;
int pincntl135;
int pincntl136;
int pincntl137;
int pincntl138;
int pincntl139;
int pincntl140;
int pincntl141;
int pincntl142;
int pincntl143;
int pincntl144;
int pincntl145;
int pincntl146;
int pincntl147;
int pincntl148;
int pincntl149;
int pincntl150;
int pincntl151;
int pincntl152;
int pincntl153;
int pincntl154;
int pincntl155;
int pincntl156;
int pincntl157;
int pincntl158;
int pincntl159;
int pincntl160;
int pincntl161;
int pincntl162;
int pincntl163;
int pincntl164;
int pincntl165;
int pincntl166;
int pincntl167;
int pincntl168;
int pincntl169;
int pincntl170;
int pincntl171;
int pincntl172;
int pincntl173;
int pincntl174;
int pincntl175;
int pincntl176;
int pincntl177;
int pincntl178;
int pincntl179;
int pincntl180;
int pincntl181;
int pincntl182;
int pincntl183;
int pincntl184;
int pincntl185;
int pincntl186;
int pincntl187;
int pincntl188;
int pincntl189;
int pincntl190;
int pincntl191;
int pincntl192;
int pincntl193;
int pincntl194;
int pincntl195;
int pincntl196;
int pincntl197;
int pincntl198;
int pincntl199;
int pincntl200;
int pincntl201;
int pincntl202;
int pincntl203;
int pincntl204;
int pincntl205;
int pincntl206;
int pincntl207;
int pincntl208;
int pincntl209;
int pincntl210;
int pincntl211;
int pincntl212;
int pincntl213;
int pincntl214;
int pincntl215;
int pincntl216;
int pincntl217;
int pincntl218;
int pincntl219;
int pincntl220;
int pincntl221;
int pincntl222;
int pincntl223;
int pincntl224;
int pincntl225;
int pincntl226;
int pincntl227;
int pincntl228;
int pincntl229;
int pincntl230;
int pincntl231;
int pincntl232;
int pincntl233;
int pincntl234;
int pincntl235;
int pincntl236;
int pincntl237;
int pincntl238;
int pincntl239;
int pincntl240;
int pincntl241;
int pincntl242;
int pincntl243;
int pincntl244;
int pincntl245;
int pincntl246;
int pincntl247;
int pincntl248;
int pincntl249;
int pincntl250;
int pincntl251;
int pincntl252;
int pincntl253;
int pincntl254;
int pincntl255;
int pincntl256;
int pincntl257;
int pincntl258;
int pincntl259;
int pincntl260;
int pincntl261;
int pincntl262;
int pincntl263;
int pincntl264;
int pincntl265;
int pincntl266;
int pincntl267;
int pincntl268;
int pincntl269;
int pincntl270;
int pincntl271;
int pincntl272;
int pincntl273;
int pincntl274;
int pincntl275;
int pincntl276;
int pincntl277;
int pincntl278;
int pincntl279;
int pincntl280;
int pincntl281;
int pincntl282;
int pincntl283;
int pincntl284;
int pincntl285;
int pincntl286;
int pincntl287;
int pincntl288;
int pincntl289;
int pincntl290;
int pincntl291;
int pincntl292;
int pincntl293;
int pincntl294;
int pincntl295;
int pincntl296;
int pincntl297;
int pincntl298;
int pincntl299;
int pincntl300;
int pincntl301;
int pincntl302;
int pincntl303;
int pincntl304;
int pincntl305;
int pincntl306;
int pincntl307;
int pincntl308;
int pincntl309;
int pincntl310;
int pincntl311;
int pincntl312;
int pincntl313;
int pincntl314;
int pincntl315;
int pincntl316;
int pincntl317;
int pincntl318;
int pincntl319;
int pincntl320;
int pincntl321;
int pincntl322;
int pincntl323;
};
#endif /* endif _MUX_TI816X_H_ */

4
arch/arm/include/asm/arch-am33xx/omap.h
View file

@ -20,10 +20,6 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define NON_SECURE_SRAM_IMG_END 0x4030B800
#elif defined(CONFIG_TI816X)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define NON_SECURE_SRAM_IMG_END 0x4031B800
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40340000

14
arch/arm/include/asm/arch-am33xx/spl.h
View file

@ -9,19 +9,7 @@
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_MMC2_2 0xFF
#if defined(CONFIG_TI816X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x03
#define BOOT_DEVICE_ONENAND 0x04
#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */
#define BOOT_DEVICE_MMC1 0x06
#define BOOT_DEVICE_UART 0x43
#define BOOT_DEVICE_USB 0x45
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#elif defined(CONFIG_AM33XX)
#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x05

18
arch/arm/include/asm/arch-bcmcygnus/configs.h
View file

@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014-2017 Broadcom.
*/
#ifndef __ARCH_CONFIGS_H
#define __ARCH_CONFIGS_H
#include <asm/iproc-common/configs.h>
/* uArchitecture specifics */
/* Serial Info */
#define CFG_SYS_NS16550_CLK 100000000
#define CFG_SYS_NS16550_CLK_DIV 54
#define CFG_SYS_NS16550_COM3 0x18023000
#endif /* __ARCH_CONFIGS_H */

17
arch/arm/include/asm/arch-bcmnsp/configs.h
View file

@ -1,17 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Broadcom Corporation.
*/
#ifndef __ARCH_CONFIGS_H
#define __ARCH_CONFIGS_H
#include <asm/iproc-common/configs.h>
/* uArchitecture specifics */
/* Serial Info */
#define CFG_SYS_NS16550_CLK 0x03b9aca0
#define CFG_SYS_NS16550_COM1 0x18000300
#endif /* __ARCH_CONFIGS_H */

2
arch/arm/include/asm/arch-imx8m/sys_proto.h
View file

@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX8M_SYS_PROTO_H
#define __ARCH_NMX8M_SYS_PROTO_H
#define __ARCH_IMX8M_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/imx-regs.h>

2
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
View file

@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX8ULP_SYS_PROTO_H
#define __ARCH_NMX8ULP_SYS_PROTO_H
#define __ARCH_IMX8ULP_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>

2
arch/arm/include/asm/arch-imx9/sys_proto.h
View file

@ -4,7 +4,7 @@
*/
#ifndef __ARCH_IMX9_SYS_PROTO_H
#define __ARCH_NMX9_SYS_PROTO_H
#define __ARCH_IMX9_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>

10
arch/arm/include/asm/arch-imxrt/imxrt.h
View file

@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef _ASM_ARCH_IMXRT_H
#define _ASM_ARCH_IMXRT_H
#endif /* _ASM_ARCH_IMXRT_H */

39
arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
View file

@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* LPC32xx GPIO interface macro for pin mapping.
*
* (C) Copyright 2015 DENX Software Engineering GmbH
* Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
*/
#ifndef _LPC32XX_GPIO_GRP_H
#define _LPC32XX_GPIO_GRP_H
/*
* Macro to map the pin for the lpc32xx_gpio driver.
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
* P0.0 - P0.7
* P1.0 - P1.23
* P2.0 - P2.12
* P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
* P3 GPO_0 - GPO_23
* P3 GPIO_0 - GPIO_5 (output register only)
*/
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro
* ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
* See the LPC32x0 User's guide for GPIO group numbers
*/
#define LPC32XX_GPIO(x, y) ((x) + (y))
#endif /* _LPC32XX_GPIO_GRP_H */

11
arch/arm/include/asm/arch-mx27/mxcmmc.h
View file

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#ifndef ASM_ARCH_MXCMMC_H
#define ASM_ARCH_MXCMMC_H
int mxc_mmc_init(struct bd_info *bis);
#endif

11
arch/arm/include/asm/arch-mx6/opos6ul.h
View file

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Armadeus Systems
*/
#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
#define __ARCH_ARM_MX6UL_OPOS6UL_H__
int opos6ul_board_late_init(void);
#endif

219
arch/arm/include/asm/arch-mxs/regs-uartapp.h
View file

@ -1,219 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Freescale MXS UARTAPP Register Definitions
*
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __ARCH_ARM___MXS_UARTAPP_H
#define __ARCH_ARM___MXS_UARTAPP_H
#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_uartapp_regs {
mxs_reg_32(hw_uartapp_ctrl0)
mxs_reg_32(hw_uartapp_ctrl1)
mxs_reg_32(hw_uartapp_ctrl2)
mxs_reg_32(hw_uartapp_linectrl)
mxs_reg_32(hw_uartapp_linectrl2)
mxs_reg_32(hw_uartapp_intr)
mxs_reg_32(hw_uartapp_data)
mxs_reg_32(hw_uartapp_stat)
mxs_reg_32(hw_uartapp_debug)
mxs_reg_32(hw_uartapp_version)
mxs_reg_32(hw_uartapp_autobaud)
};
#endif
#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
#define UARTAPP_CTRL2_UARTEN_MASK 0x01
#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
#define UARTAPP_LINECTRL_WLEN_OFFSET 5
#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
#define UARTAPP_LINECTRL_BRK_MASK 1
#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
#define UARTAPP_INTR_OEIS_MASK (1 << 10)
#define UARTAPP_INTR_BEIS_MASK (1 << 9)
#define UARTAPP_INTR_PEIS_MASK (1 << 8)
#define UARTAPP_INTR_FEIS_MASK (1 << 7)
#define UARTAPP_INTR_RTIS_MASK (1 << 6)
#define UARTAPP_INTR_TXIS_MASK (1 << 5)
#define UARTAPP_INTR_RXIS_MASK (1 << 4)
#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
#define UARTAPP_INTR_RIMIS_MASK 0x1
#define UARTAPP_DATA_DATA_OFFSET 0
#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
#define UARTAPP_STAT_BUSY_MASK (1 << 29)
#define UARTAPP_STAT_CTS_MASK (1 << 28)
#define UARTAPP_STAT_TXFE_MASK (1 << 27)
#define UARTAPP_STAT_RXFF_MASK (1 << 26)
#define UARTAPP_STAT_TXFF_MASK (1 << 25)
#define UARTAPP_STAT_RXFE_MASK (1 << 24)
#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
#define UARTAPP_STAT_OERR_MASK (1 << 19)
#define UARTAPP_STAT_BERR_MASK (1 << 18)
#define UARTAPP_STAT_PERR_MASK (1 << 17)
#define UARTAPP_STAT_FERR_MASK (1 << 16)
#define UARTAPP_STAT_RXCOUNT_OFFSET 0
#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
#define UARTAPP_VERSION_MAJOR_OFFSET 24
#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
#define UARTAPP_VERSION_MINOR_OFFSET 16
#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
#define UARTAPP_VERSION_STEP_OFFSET 0
#define UARTAPP_VERSION_STEP_MASK 0xFFFF
#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
#endif /* __ARCH_ARM___UARTAPP_H */

78
arch/arm/include/asm/arch-omap3/omap3-regs.h
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@ -1,78 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
*/
#ifndef _OMAP3_REGS_H
#define _OMAP3_REGS_H
/*
* Register definitions for OMAP3 processors.
*/
/*
* GPMC_CONFIG1 - GPMC_CONFIG7
*/
/* Values for GPMC_CONFIG1 - signal control parameters */
#define WRAPBURST (1 << 31)
#define READMULTIPLE (1 << 30)
#define READTYPE (1 << 29)
#define WRITEMULTIPLE (1 << 28)
#define WRITETYPE (1 << 27)
#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
#define WAITREADMONITORING (1 << 22)
#define WAITWRITEMONITORING (1 << 21)
#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
#define WAITPINSELECT(x) (((x) & 3) << 16)
#define DEVICESIZE(x) (((x) & 3) << 12)
#define DEVICESIZE_8BIT DEVICESIZE(0)
#define DEVICESIZE_16BIT DEVICESIZE(1)
#define DEVICETYPE(x) (((x) & 3) << 10)
#define DEVICETYPE_NOR DEVICETYPE(0)
#define DEVICETYPE_NAND DEVICETYPE(2)
#define MUXADDDATA (1 << 9)
#define TIMEPARAGRANULARITY (1 << 4)
#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
/* Values for GPMC_CONFIG2 - CS timing */
#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
#define CSEXTRADELAY (1 << 7)
#define CSONTIME(x) (((x) & 0xf) << 0)
/* Values for GPMC_CONFIG3 - nADV timing */
#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
#define ADVEXTRADELAY (1 << 7)
#define ADVONTIME(x) (((x) & 0xf) << 0)
/* Values for GPMC_CONFIG4 - nWE and nOE timing */
#define WEOFFTIME(x) (((x) & 0x1f) << 24)
#define WEEXTRADELAY (1 << 23)
#define WEONTIME(x) (((x) & 0xf) << 16)
#define OEOFFTIME(x) (((x) & 0x1f) << 8)
#define OEEXTRADELAY (1 << 7)
#define OEONTIME(x) (((x) & 0xf) << 0)
/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
/* Values for GPMC_CONFIG6 - misc timings */
#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
#define CYCLE2CYCLESAMECSEN (1 << 7)
#define CYCLE2CYCLEDIFFCSEN (1 << 6)
#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
/* Values for GPMC_CONFIG7 - CS address mapping configuration */
#define MASKADDRESS(x) (((x) & 0xf) << 8)
#define CSVALID (1 << 6)
#define BASEADDRESS(x) (((x) & 0x3f) << 0)
#endif /* _OMAP3_REGS_H */

317
arch/arm/include/asm/arch-omap5/mux_omap5.h
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@ -1,317 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2004-2009
* Texas Instruments Incorporated
* Richard Woodruff <r-woodruff2@ti.com>
* Aneesh V <aneesh@ti.com>
* Balaji Krishnamoorthy <balajitk@ti.com>
*/
#ifndef _MUX_OMAP5_H_
#define _MUX_OMAP5_H_
#include <asm/types.h>
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (2 << 10)
#define OFF_IN (1 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (1 << 9)
#else
#define OFF_PD (0 << 12)
#define OFF_PU (0 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (0 << 10)
#define OFF_IN (0 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (0 << 9)
#endif
#define IEN (1 << 8)
#define IDIS (0 << 8)
#define PTU (3 << 3)
#define PTD (1 << 3)
#define EN (1 << 3)
#define DIS (0 << 3)
#define M0 0
#define M1 1
#define M2 2
#define M3 3
#define M4 4
#define M5 5
#define M6 6
#define M7 7
#define SAFE_MODE M7
#ifdef CONFIG_OFF_PADCONF
#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
#else
#define OFF_IN_PD 0
#define OFF_IN_PU 0
#define OFF_OUT_PD 0
#define OFF_OUT_PU 0
#endif
#define CORE_REVISION 0x0000
#define CORE_HWINFO 0x0004
#define CORE_SYSCONFIG 0x0010
#define EMMC_CLK 0x0040
#define EMMC_CMD 0x0042
#define EMMC_DATA0 0x0044
#define EMMC_DATA1 0x0046
#define EMMC_DATA2 0x0048
#define EMMC_DATA3 0x004a
#define EMMC_DATA4 0x004c
#define EMMC_DATA5 0x004e
#define EMMC_DATA6 0x0050
#define EMMC_DATA7 0x0052
#define C2C_CLKOUT0 0x0054
#define C2C_CLKOUT1 0x0056
#define C2C_CLKIN0 0x0058
#define C2C_CLKIN1 0x005a
#define C2C_DATAIN0 0x005c
#define C2C_DATAIN1 0x005e
#define C2C_DATAIN2 0x0060
#define C2C_DATAIN3 0x0062
#define C2C_DATAIN4 0x0064
#define C2C_DATAIN5 0x0066
#define C2C_DATAIN6 0x0068
#define C2C_DATAIN7 0x006a
#define C2C_DATAOUT0 0x006c
#define C2C_DATAOUT1 0x006e
#define C2C_DATAOUT2 0x0070
#define C2C_DATAOUT3 0x0072
#define C2C_DATAOUT4 0x0074
#define C2C_DATAOUT5 0x0076
#define C2C_DATAOUT6 0x0078
#define C2C_DATAOUT7 0x007a
#define C2C_DATA8 0x007c
#define C2C_DATA9 0x007e
#define C2C_DATA10 0x0080
#define C2C_DATA11 0x0082
#define C2C_DATA12 0x0084
#define C2C_DATA13 0x0086
#define C2C_DATA14 0x0088
#define C2C_DATA15 0x008a
#define LLIA_WAKEREQOUT 0x008c
#define LLIB_WAKEREQOUT 0x008e
#define HSI1_ACREADY 0x0090
#define HSI1_CAREADY 0x0092
#define HSI1_ACWAKE 0x0094
#define HSI1_CAWAKE 0x0096
#define HSI1_ACFLAG 0x0098
#define HSI1_ACDATA 0x009a
#define HSI1_CAFLAG 0x009c
#define HSI1_CADATA 0x009e
#define UART1_TX 0x00a0
#define UART1_CTS 0x00a2
#define UART1_RX 0x00a4
#define UART1_RTS 0x00a6
#define HSI2_CAREADY 0x00a8
#define HSI2_ACREADY 0x00aa
#define HSI2_CAWAKE 0x00ac
#define HSI2_ACWAKE 0x00ae
#define HSI2_CAFLAG 0x00b0
#define HSI2_CADATA 0x00b2
#define HSI2_ACFLAG 0x00b4
#define HSI2_ACDATA 0x00b6
#define UART2_RTS 0x00b8
#define UART2_CTS 0x00ba
#define UART2_RX 0x00bc
#define UART2_TX 0x00be
#define USBB1_HSIC_STROBE 0x00c0
#define USBB1_HSIC_DATA 0x00c2
#define USBB2_HSIC_STROBE 0x00c4
#define USBB2_HSIC_DATA 0x00c6
#define TIMER10_PWM_EVT 0x00c8
#define DSIPORTA_TE0 0x00ca
#define DSIPORTA_LANE0X 0x00cc
#define DSIPORTA_LANE0Y 0x00ce
#define DSIPORTA_LANE1X 0x00d0
#define DSIPORTA_LANE1Y 0x00d2
#define DSIPORTA_LANE2X 0x00d4
#define DSIPORTA_LANE2Y 0x00d6
#define DSIPORTA_LANE3X 0x00d8
#define DSIPORTA_LANE3Y 0x00da
#define DSIPORTA_LANE4X 0x00dc
#define DSIPORTA_LANE4Y 0x00de
#define DSIPORTC_LANE0X 0x00e0
#define DSIPORTC_LANE0Y 0x00e2
#define DSIPORTC_LANE1X 0x00e4
#define DSIPORTC_LANE1Y 0x00e6
#define DSIPORTC_LANE2X 0x00e8
#define DSIPORTC_LANE2Y 0x00ea
#define DSIPORTC_LANE3X 0x00ec
#define DSIPORTC_LANE3Y 0x00ee
#define DSIPORTC_LANE4X 0x00f0
#define DSIPORTC_LANE4Y 0x00f2
#define DSIPORTC_TE0 0x00f4
#define TIMER9_PWM_EVT 0x00f6
#define I2C4_SCL 0x00f8
#define I2C4_SDA 0x00fa
#define MCSPI2_CLK 0x00fc
#define MCSPI2_SIMO 0x00fe
#define MCSPI2_SOMI 0x0100
#define MCSPI2_CS0 0x0102
#define RFBI_DATA15 0x0104
#define RFBI_DATA14 0x0106
#define RFBI_DATA13 0x0108
#define RFBI_DATA12 0x010a
#define RFBI_DATA11 0x010c
#define RFBI_DATA10 0x010e
#define RFBI_DATA9 0x0110
#define RFBI_DATA8 0x0112
#define RFBI_DATA7 0x0114
#define RFBI_DATA6 0x0116
#define RFBI_DATA5 0x0118
#define RFBI_DATA4 0x011a
#define RFBI_DATA3 0x011c
#define RFBI_DATA2 0x011e
#define RFBI_DATA1 0x0120
#define RFBI_DATA0 0x0122
#define RFBI_WE 0x0124
#define RFBI_CS0 0x0126
#define RFBI_A0 0x0128
#define RFBI_RE 0x012a
#define RFBI_HSYNC0 0x012c
#define RFBI_TE_VSYNC0 0x012e
#define GPIO6_182 0x0130
#define GPIO6_183 0x0132
#define GPIO6_184 0x0134
#define GPIO6_185 0x0136
#define GPIO6_186 0x0138
#define GPIO6_187 0x013a
#define HDMI_CEC 0x013c
#define HDMI_HPD 0x013e
#define HDMI_DDC_SCL 0x0140
#define HDMI_DDC_SDA 0x0142
#define CSIPORTC_LANE0X 0x0144
#define CSIPORTC_LANE0Y 0x0146
#define CSIPORTC_LANE1X 0x0148
#define CSIPORTC_LANE1Y 0x014a
#define CSIPORTB_LANE0X 0x014c
#define CSIPORTB_LANE0Y 0x014e
#define CSIPORTB_LANE1X 0x0150
#define CSIPORTB_LANE1Y 0x0152
#define CSIPORTB_LANE2X 0x0154
#define CSIPORTB_LANE2Y 0x0156
#define CSIPORTA_LANE0X 0x0158
#define CSIPORTA_LANE0Y 0x015a
#define CSIPORTA_LANE1X 0x015c
#define CSIPORTA_LANE1Y 0x015e
#define CSIPORTA_LANE2X 0x0160
#define CSIPORTA_LANE2Y 0x0162
#define CSIPORTA_LANE3X 0x0164
#define CSIPORTA_LANE3Y 0x0166
#define CSIPORTA_LANE4X 0x0168
#define CSIPORTA_LANE4Y 0x016a
#define CAM_SHUTTER 0x016c
#define CAM_STROBE 0x016e
#define CAM_GLOBALRESET 0x0170
#define TIMER11_PWM_EVT 0x0172
#define TIMER5_PWM_EVT 0x0174
#define TIMER6_PWM_EVT 0x0176
#define TIMER8_PWM_EVT 0x0178
#define I2C3_SCL 0x017a
#define I2C3_SDA 0x017c
#define GPIO8_233 0x017e
#define GPIO8_234 0x0180
#define ABE_CLKS 0x0182
#define ABEDMIC_DIN1 0x0184
#define ABEDMIC_DIN2 0x0186
#define ABEDMIC_DIN3 0x0188
#define ABEDMIC_CLK1 0x018a
#define ABEDMIC_CLK2 0x018c
#define ABEDMIC_CLK3 0x018e
#define ABESLIMBUS1_CLOCK 0x0190
#define ABESLIMBUS1_DATA 0x0192
#define ABEMCBSP2_DR 0x0194
#define ABEMCBSP2_DX 0x0196
#define ABEMCBSP2_FSX 0x0198
#define ABEMCBSP2_CLKX 0x019a
#define ABEMCPDM_UL_DATA 0x019c
#define ABEMCPDM_DL_DATA 0x019e
#define ABEMCPDM_FRAME 0x01a0
#define ABEMCPDM_LB_CLK 0x01a2
#define WLSDIO_CLK 0x01a4
#define WLSDIO_CMD 0x01a6
#define WLSDIO_DATA0 0x01a8
#define WLSDIO_DATA1 0x01aa
#define WLSDIO_DATA2 0x01ac
#define WLSDIO_DATA3 0x01ae
#define UART5_RX 0x01b0
#define UART5_TX 0x01b2
#define UART5_CTS 0x01b4
#define UART5_RTS 0x01b6
#define I2C2_SCL 0x01b8
#define I2C2_SDA 0x01ba
#define MCSPI1_CLK 0x01bc
#define MCSPI1_SOMI 0x01be
#define MCSPI1_SIMO 0x01c0
#define MCSPI1_CS0 0x01c2
#define MCSPI1_CS1 0x01c4
#define I2C5_SCL 0x01c6
#define I2C5_SDA 0x01c8
#define PERSLIMBUS2_CLOCK 0x01ca
#define PERSLIMBUS2_DATA 0x01cc
#define UART6_TX 0x01ce
#define UART6_RX 0x01d0
#define UART6_CTS 0x01d2
#define UART6_RTS 0x01d4
#define UART3_CTS_RCTX 0x01d6
#define UART3_RTS_IRSD 0x01d8
#define UART3_TX_IRTX 0x01da
#define UART3_RX_IRRX 0x01dc
#define USBB3_HSIC_STROBE 0x01de
#define USBB3_HSIC_DATA 0x01e0
#define SDCARD_CLK 0x01e2
#define SDCARD_CMD 0x01e4
#define SDCARD_DATA2 0x01e6
#define SDCARD_DATA3 0x01e8
#define SDCARD_DATA0 0x01ea
#define SDCARD_DATA1 0x01ec
#define USBD0_HS_DP 0x01ee
#define USBD0_HS_DM 0x01f0
#define I2C1_PMIC_SCL 0x01f2
#define I2C1_PMIC_SDA 0x01f4
#define USBD0_SS_RX 0x01f6
#define LLIA_WAKEREQIN 0x0040
#define LLIB_WAKEREQIN 0x0042
#define DRM_EMU0 0x0044
#define DRM_EMU1 0x0046
#define JTAG_NTRST 0x0048
#define JTAG_TCK 0x004a
#define JTAG_RTCK 0x004c
#define JTAG_TMSC 0x004e
#define JTAG_TDI 0x0050
#define JTAG_TDO 0x0052
#define SYS_32K 0x0054
#define FREF_CLK_IOREQ 0x0056
#define FREF_CLK0_OUT 0x0058
#define FREF_CLK1_OUT 0x005a
#define FREF_CLK2_OUT 0x005c
#define FREF_CLK2_REQ 0x005e
#define FREF_CLK1_REQ 0x0060
#define SYS_NRESPWRON 0x0062
#define SYS_NRESWARM 0x0064
#define SYS_PWR_REQ 0x0066
#define SYS_NIRQ1 0x0068
#define SYS_NIRQ2 0x006a
#define SR_PMIC_SCL 0x006c
#define SR_PMIC_SDA 0x006e
#define SYS_BOOT0 0x0070
#define SYS_BOOT1 0x0072
#define SYS_BOOT2 0x0074
#define SYS_BOOT3 0x0076
#define SYS_BOOT4 0x0078
#define SYS_BOOT5 0x007a
#endif /* _MUX_OMAP5_H_ */

14
arch/arm/include/asm/iproc-common/configs.h
View file

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Broadcom Corporation.
*/
#ifndef __IPROC_COMMON_CONFIGS_H
#define __IPROC_COMMON_CONFIGS_H
#include <linux/stringify.h>
/* Memory Info */
#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */

12
arch/arm/include/asm/iproc-common/iproc_sdhci.h
View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: <SPDX License Expression> */
/*
* Copyright 2019 Broadcom
*
*/
#ifndef __IPROC_SDHCI_H
#define __IPROC_SDHCI_H
int iproc_sdhci_init(int dev_index, u32 quirks);
#endif

11
arch/arm/include/asm/kona-common/kona_sdhci.h
View file

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Broadcom Corporation.
*/
#ifndef __KONA_SDHCI_H
#define __KONA_SDHCI_H
int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
#endif

32
arch/arm/mach-at91/include/mach/at91_rtt.h
View file

@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
*
* Real-time Timer
* Based on AT91SAM9XE datasheet
*/
#ifndef AT91_RTT_H
#define AT91_RTT_H
#ifndef __ASSEMBLY__
typedef struct at91_rtt {
u32 mr; /* Mode Register RW 0x00008000 */
u32 ar; /* Alarm Register RW 0xFFFFFFFF */
u32 vr; /* Value Register RO 0x00000000 */
u32 sr; /* Status Register RO 0x00000000 */
} at91_rtt_t;
#endif /* __ASSEMBLY__ */
#define AT91_RTT_MR_RTPRES 0x0000ffff
#define AT91_RTT_MR_ALMIEN 0x00010000
#define AT91_RTT_RTTINCIEN 0x00020000
#define AT91_RTT_RTTRST 0x00040000
#define AT91_RTT_SR_ALMS 0x00000001
#define AT91_RTT_SR_RTTINC 0x00000002
#endif

35
arch/arm/mach-davinci/include/mach/aintc_defs.h
View file

@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#ifndef _DV_AINTC_DEFS_H_
#define _DV_AINTC_DEFS_H_
struct dv_aintc_regs {
unsigned int fiq0; /* 0x00 */
unsigned int fiq1; /* 0x04 */
unsigned int irq0; /* 0x08 */
unsigned int irq1; /* 0x0c */
unsigned int fiqentry; /* 0x10 */
unsigned int irqentry; /* 0x14 */
unsigned int eint0; /* 0x18 */
unsigned int eint1; /* 0x1c */
unsigned int intctl; /* 0x20 */
unsigned int eabase; /* 0x24 */
unsigned char rsvd0[8]; /* 0x28 */
unsigned int intpri0; /* 0x30 */
unsigned int intpri1; /* 0x34 */
unsigned int intpri2; /* 0x38 */
unsigned int intpri3; /* 0x3c */
unsigned int intpri4; /* 0x40 */
unsigned int intpri5; /* 0x44 */
unsigned int intpri6; /* 0x48 */
unsigned int intpri7; /* 0x4c */
};
#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
#define DV_AINTC_INTCTL_IDMODE (1 << 2)
#endif /* _DV_AINTC_DEFS_H_ */

24
arch/arm/mach-keystone/include/mach/xhci-keystone.h
View file

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* USB 3.0 DRD Controller
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*/
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
#define USB3_PHY_REF_SSP_EN BIT(29)
#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
/* KEYSTONE2 XHCI PHY register structure */
struct keystone_xhci_phy {
unsigned int phy_utmi; /* ctl0 */
unsigned int phy_pipe; /* ctl1 */
unsigned int phy_param_ctrl_1; /* ctl2 */
unsigned int phy_param_ctrl_2; /* ctl3 */
unsigned int phy_clock; /* ctl4 */
unsigned int phy_pll; /* ctl5 */
};

11
arch/arm/mach-omap2/Kconfig
View file

@ -77,16 +77,6 @@ config OMAP54XX
imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
config TI816X
bool "TI816X SoC"
select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
help
Support for AM335x SOC from Texas Instruments.
The AM335x high performance SOC features a Cortex-A8
ARM core and more.
config AM43XX
bool "AM43XX SoC"
select SPECIFY_CONSOLE_INDEX
@ -203,7 +193,6 @@ source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/compulab/cm_t43/Kconfig"

10
arch/arm/mach-omap2/am33xx/Kconfig
View file

@ -1,13 +1,3 @@
if TI816X
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
help
This option specifies support for the TI8168 EVM development platform
with PG2.0 silicon and DDR3 DRAM.
endif
if AM33XX
config AM33XX_CHILISOM

4
arch/arm/mach-omap2/am33xx/Makefile
View file

@ -9,13 +9,11 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
obj-y += clock.o
endif
obj-$(CONFIG_TI816X) += clock_ti816x.o
obj-y += sys_info.o
obj-y += ddr.o
ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y += emif4.o
endif
obj-$(CONFIG_TI816X) += ti816x_emif4.o
obj-y += board.o
obj-y += mux.o
obj-y += prcm-regs.o

407
arch/arm/mach-omap2/am33xx/clock_ti816x.c
View file

@ -1,407 +0,0 @@
/*
* clock_ti816x.c
*
* Clocks for TI816X based boards
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
*
* Based on TI-PSP-04.00.02.14 :
*
* Copyright (C) 2009, Texas Instruments, Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/emif.h>
#define CM_PLL_BASE (CTRL_BASE + 0x0400)
/* Main PLL */
#define MAIN_N 64
#define MAIN_P 0x1
#define MAIN_INTFREQ1 0x8
#define MAIN_FRACFREQ1 0x800000
#define MAIN_MDIV1 0x2
#define MAIN_INTFREQ2 0xE
#define MAIN_FRACFREQ2 0x0
#define MAIN_MDIV2 0x1
#define MAIN_INTFREQ3 0x8
#define MAIN_FRACFREQ3 0xAAAAB0
#define MAIN_MDIV3 0x3
#define MAIN_INTFREQ4 0x9
#define MAIN_FRACFREQ4 0x55554F
#define MAIN_MDIV4 0x3
#define MAIN_INTFREQ5 0x9
#define MAIN_FRACFREQ5 0x374BC6
#define MAIN_MDIV5 0xC
#define MAIN_MDIV6 0x48
#define MAIN_MDIV7 0x4
/* DDR PLL */
#define DDR_N 59
#define DDR_P 0x1
#define DDR_MDIV1 0x2
#define DDR_INTFREQ2 0x8
#define DDR_FRACFREQ2 0xD99999
#define DDR_MDIV2 0x1E
#define DDR_INTFREQ3 0x8
#define DDR_FRACFREQ3 0x0
#define DDR_MDIV3 0x4
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
#define DDR_FRACFREQ4 0x0
#define DDR_MDIV4 0x4
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
#define DDR_FRACFREQ5 0x0
#define DDR_MDIV5 0x4
#define CONTROL_STATUS (CTRL_BASE + 0x40)
#define DDR_RCD (CTRL_BASE + 0x070C)
#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
#define INTCPS_SYSCONFIG 0x48200010
#define CM_SYSCLK10_CLKSEL 0x48180324
struct cm_pll {
unsigned int mainpll_ctrl; /* offset 0x400 */
unsigned int mainpll_pwd;
unsigned int mainpll_freq1;
unsigned int mainpll_div1;
unsigned int mainpll_freq2;
unsigned int mainpll_div2;
unsigned int mainpll_freq3;
unsigned int mainpll_div3;
unsigned int mainpll_freq4;
unsigned int mainpll_div4;
unsigned int mainpll_freq5;
unsigned int mainpll_div5;
unsigned int resv0[1];
unsigned int mainpll_div6;
unsigned int resv1[1];
unsigned int mainpll_div7;
unsigned int ddrpll_ctrl; /* offset 0x440 */
unsigned int ddrpll_pwd;
unsigned int resv2[1];
unsigned int ddrpll_div1;
unsigned int ddrpll_freq2;
unsigned int ddrpll_div2;
unsigned int ddrpll_freq3;
unsigned int ddrpll_div3;
unsigned int ddrpll_freq4;
unsigned int ddrpll_div4;
unsigned int ddrpll_freq5;
unsigned int ddrpll_div5;
unsigned int videopll_ctrl; /* offset 0x470 */
unsigned int videopll_pwd;
unsigned int videopll_freq1;
unsigned int videopll_div1;
unsigned int videopll_freq2;
unsigned int videopll_div2;
unsigned int videopll_freq3;
unsigned int videopll_div3;
unsigned int resv3[4];
unsigned int audiopll_ctrl; /* offset 0x4A0 */
unsigned int audiopll_pwd;
unsigned int resv4[2];
unsigned int audiopll_freq2;
unsigned int audiopll_div2;
unsigned int audiopll_freq3;
unsigned int audiopll_div3;
unsigned int audiopll_freq4;
unsigned int audiopll_div4;
unsigned int audiopll_freq5;
unsigned int audiopll_div5;
};
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
void enable_dmm_clocks(void)
{
writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
/* Wait for dmm to be fully functional, including OCP */
while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
;
}
void enable_emif_clocks(void)
{
writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
/* Wait for clocks to be active */
while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
;
/* Wait for emif0 to be fully functional, including OCP */
while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
;
/* Wait for emif1 to be fully functional, including OCP */
while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
;
}
/* assume delay is aprox at least 1us */
static void ddr_delay(int d)
{
int i;
/*
* read a control register.
* this is a bit more delay and cannot be optimized by the compiler
* assuming one read takes 200 cycles and A8 is runing 1 GHz
* somewhat conservative setting
*/
for (i = 0; i < 50*d; i++)
readl(CONTROL_STATUS);
}
static void main_pll_init_ti816x(void)
{
u32 main_pll_ctrl = 0;
/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
main_pll_ctrl &= 0xFFFFFFFB;
main_pll_ctrl |= BIT(2);
writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
/* Enable PLL by setting BIT3 in its ctrl reg */
main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
main_pll_ctrl &= 0xFFFFFFF7;
main_pll_ctrl |= BIT(3);
writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
/* Write the values of N,P in the CTRL reg */
main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
main_pll_ctrl &= 0xFF;
main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
/* Power up clock1-7 */
writel(0x0, &cmpll->mainpll_pwd);
/* Program the freq and divider values for clock1-7 */
writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
&cmpll->mainpll_freq1);
writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
&cmpll->mainpll_freq2);
writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
&cmpll->mainpll_freq3);
writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
&cmpll->mainpll_freq4);
writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
&cmpll->mainpll_freq5);
writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
/* Wait for PLL to lock */
while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
;
/* Put the PLL in normal mode, disable bypass */
main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
main_pll_ctrl &= 0xFFFFFFFB;
writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
}
static void ddr_pll_bypass_ti816x(void)
{
u32 ddr_pll_ctrl = 0;
/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
ddr_pll_ctrl &= 0xFFFFFFFB;
ddr_pll_ctrl |= BIT(2);
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
}
static void ddr_pll_init_ti816x(void)
{
u32 ddr_pll_ctrl = 0;
/* Enable PLL by setting BIT3 in its ctrl reg */
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
ddr_pll_ctrl &= 0xFFFFFFF7;
ddr_pll_ctrl |= BIT(3);
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
/* Write the values of N,P in the CTRL reg */
ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
ddr_pll_ctrl &= 0xFF;
ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
ddr_delay(10);
/* Power up clock1-5 */
writel(0x0, &cmpll->ddrpll_pwd);
/* Program the freq and divider values for clock1-3 */
writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
ddr_delay(1);
writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
&cmpll->ddrpll_freq2);
writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
ddr_delay(1);
writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
ddr_delay(1);
writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
&cmpll->ddrpll_freq3);
ddr_delay(1);
writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
&cmpll->ddrpll_freq3);
ddr_delay(5);
/* Wait for PLL to lock */
while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
;
/* Power up RCD */
writel(BIT(0), DDR_RCD);
}
static void peripheral_enable(void)
{
/* Wake-up the l3_slow clock */
writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
/*
* Note on Timers:
* There are 8 timers(0-7) out of which timer 0 is a secure timer.
* Timer 0 mux should not be changed
*
* To access the timer registers we need the to be
* enabled which is what we do in the first step
*/
/* Enable timer1 */
writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
/* Select timer1 clock to be CLKIN (27MHz) */
writel(BIT(1), CM_TIMER1_CLKSEL);
/* Wait for timer1 to be ON-ACTIVE */
while (((readl(&cmalwon->l3slowclkstctrl)
& (0x80000<<1))>>20) != 1)
;
/* Wait for timer1 to be enabled */
while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
;
/* Active posted mode */
writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
;
/* Start timer1 */
writel(BIT(0), (DM_TIMER1_BASE + 0x38));
/* eFuse */
writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
;
/* Enable gpio0 */
writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
;
writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
/* Enable gpio1 */
writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
;
writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
/* Enable spi */
writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
;
/* Enable i2c0 */
writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
;
/* Enable ethernet0 */
writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
/* Enable hsmmc */
writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
;
}
void setup_clocks_for_console(void)
{
/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
writel(0x0, CM_SYSCLK10_CLKSEL);
ddr_pll_bypass_ti816x();
/* Enable uart0-2 */
writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
;
writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
;
writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
;
while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
;
}
void setup_early_clocks(void)
{
setup_clocks_for_console();
}
void prcm_init(void)
{
/* Enable the control */
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
main_pll_init_ti816x();
ddr_pll_init_ti816x();
/*
* With clk freqs setup to desired values,
* enable the required peripherals
*/
peripheral_enable();
}

9
arch/arm/mach-omap2/am33xx/ddr.c
View file

@ -182,14 +182,6 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
*/
void config_sdram(const struct emif_regs *regs, int nr)
{
#ifdef CONFIG_TI816X
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */
writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
#else
if (regs->zq_config) {
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@ -211,7 +203,6 @@ void config_sdram(const struct emif_regs *regs, int nr)
/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
if (regs->ocp_config)
writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
#endif
}
/**

165
arch/arm/mach-omap2/am33xx/ti816x_emif4.c
View file

@ -1,165 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ti816x_emif4.c
*
* TI816x emif4 configuration file
*
* Copyright (C) 2017, Konsulko Group
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <linux/delay.h>
/*********************************************************************
* Init DDR3 on TI816X EVM
*********************************************************************/
static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
{
/*
* setup use_rank_delays to 1. This is only necessary when
* multiple ranks are in use. Though the EVM does not have
* multiple ranks, this is a good value to set.
*/
writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
config_cmd_ctrl(ctrl, emif);
/* for ddr3 this needs to be set to 1 */
writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
/*
* This represents the initial value for the leveling process. The
* value is a ratio - so 0x100 represents one cycle. The real delay
* is determined through the leveling process.
*
* During the leveling process, 0x20 is subtracted from the value, so
* we have added that to the value we want to set. We also set the
* values such that byte3 completes leveling after byte2 and byte1
* after byte0.
*/
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */
writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */
writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */
writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */
writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */
writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */
writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */
writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */
writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */
writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */
writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */
writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */
writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */
writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */
writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */
}
static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
{
/* Set the correct value to DDR_VTP_CTRL_0 */
writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
}
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
void config_dmm(const struct dmm_lisa_map_regs *regs)
{
writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
/* Enable Tiled Access */
writel(0x80000000, DMM_PAT_BASE_ADDR);
}
void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs,
const struct dmm_lisa_map_regs *lisa_regs, int nrs)
{
int i;
enable_emif_clocks();
for (i = 0; i < nrs; i++)
ddr_init_settings(ctrl, i);
enable_dmm_clocks();
/* Program the DMM to for non-interleaved configuration */
config_dmm(lisa_regs);
/* Program EMIF CFG Registers */
for (i = 0; i < nrs; i++) {
set_sdram_timings(regs, i);
config_sdram(regs, i);
}
udelay(1000);
for (i = 0; i < nrs; i++)
ddr3_sw_levelling(data, i);
udelay(50000); /* Some delay needed */
}

20
arch/arm/mach-omap2/boot-common.c
View file

@ -74,23 +74,6 @@ void save_omap_boot_params(void)
*/
if (boot_device == BOOT_DEVICE_QSPI_4)
boot_device = BOOT_DEVICE_SPI;
#endif
#ifdef CONFIG_TI816X
/*
* On PG2.0 and later TI816x the values we get when booting are not the
* same as on PG1.0, which is what the defines are based on. Update
* them as needed.
*/
if (get_cpu_rev() != 1) {
if (boot_device == 0x05) {
omap_boot_params->boot_device = BOOT_DEVICE_NAND;
boot_device = BOOT_DEVICE_NAND;
}
if (boot_device == 0x08) {
omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
boot_device = BOOT_DEVICE_MMC1;
}
}
#endif
/*
* When booting from peripheral booting, the boot device is not usable
@ -183,8 +166,7 @@ void save_omap_boot_params(void)
gd->arch.omap_boot_mode = boot_mode;
#if !defined(CONFIG_TI816X) && \
!defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
/* CH flags */

2
arch/arm/mach-uniphier/dram/ddrphy-init.h
View file

@ -4,7 +4,7 @@
*/
#ifndef ARCH_DDRPHY_INIT_H
#define ARCH_DDRPHY_INTT_H
#define ARCH_DDRPHY_INIT_H
#include <linux/compiler.h>
#include <linux/types.h>

27
arch/powerpc/include/asm/mc146818rtc.h
View file

@ -1,27 +0,0 @@
/*
* Machine dependent access functions for RTC registers.
*/
#ifndef __ASM_PPC_MC146818RTC_H
#define __ASM_PPC_MC146818RTC_H
#include <asm/io.h>
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
#endif
/*
* The yet supported machines all access the RTC index register via
* an ISA port access but the way to access the date register differs ...
*/
#define CMOS_READ(addr) ({ \
outb_p((addr),RTC_PORT(0)); \
inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
outb_p((addr),RTC_PORT(0)); \
outb_p((val),RTC_PORT(1)); \
})
#endif /* __ASM_PPC_MC146818RTC_H */

43
arch/powerpc/include/asm/pci_io.h
View file

@ -1,43 +0,0 @@
/* originally from linux source (asm-ppc/io.h).
* Sanity added by Rob Taylor, Flying Pig Systems, 2000
*/
#ifndef _PCI_IO_H_
#define _PCI_IO_H_
#include "io.h"
#define pci_read_le16(addr, dest) \
__asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
"r" (addr), "m" (*addr));
#define pci_write_le16(addr, val) \
__asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
"r" (val), "r" (addr));
#define pci_read_le32(addr, dest) \
__asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
"r" (addr), "m" (*addr));
#define pci_write_le32(addr, val) \
__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
"r" (val), "r" (addr));
#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#if !defined(__BIG_ENDIAN)
#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
#endif
#endif /* _PCI_IO_H_ */

15
arch/riscv/include/asm/arch-fu740/eeprom.h
View file

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 SiFive, Inc.
*
* Zong Li <zong.li@sifve.com>
*/
#ifndef _ASM_RISCV_EEPROM_H
#define _ASM_RISCV_EEPROM_H
#define PCB_REVISION_REV3 0x3
u8 get_pcb_revision_from_eeprom(void);
#endif /* _ASM_RISCV_EEPROM_H */

14
arch/sh/include/asm/mmc.h
View file

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Renesas SuperH MMCIF driver.
*
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
*/
#ifndef _SH_MMC_H_
#define _SH_MMC_H_
int mmcif_mmc_init(void);
#endif /* _SH_MMC_H_ */

2
board/freescale/common/vsc3316_3308.h
View file

@ -4,7 +4,7 @@
*/
#ifndef __VSC_CROSSBAR_H_
#define __VSC_CROSSBAR_H 1_
#define __VSC_CROSSBAR_H_
#include <common.h>
#include <i2c.h>

15
board/ti/ti816x/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_TI816X_EVM
config SYS_BOARD
default "ti816x"
config SYS_VENDOR
default "ti"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "ti816x_evm"
endif

6
board/ti/ti816x/MAINTAINERS
View file

@ -1,6 +0,0 @@
TI816X BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/ti816x/
F: include/configs/ti816x_evm.h
F: configs/ti816x_evm_defconfig

10
board/ti/ti816x/Makefile
View file

@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
# Antoine Tenart, <atenart@adeneo-embedded.com>
#
# Based on TI-PSP-04.00.02.14 :
#
# Copyright (C) 2009, Texas Instruments, Incorporated
obj-y := evm.o

140
board/ti/ti816x/evm.c
View file

@ -1,140 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* evm.c
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <spl.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
return 0;
}
int board_eth_init(struct bd_info *bis)
{
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
printf("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
printf("Unable to read MAC address. Set <ethaddr>\n");
}
return 0;
}
#ifdef CONFIG_SPL_BUILD
static struct module_pin_mux mmc_pin_mux[] = {
{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
{ -1 },
};
void set_uart_mux_conf(void) {}
void set_mux_conf_regs(void)
{
configure_module_pin_mux(mmc_pin_mux);
}
/*
* EMIF Paramters. Refer the EMIF register documentation and the
* memory datasheet for details. This is for 796 MHz.
*/
#define EMIF_TIM1 0x1779C9FE
#define EMIF_TIM2 0x50608074
#define EMIF_TIM3 0x009F857F
#define EMIF_SDREF 0x10001841
#define EMIF_SDCFG 0x62A73832
#define EMIF_PHYCFG 0x00000110
static const struct emif_regs ddr3_emif_regs = {
.sdram_config = EMIF_SDCFG,
.ref_ctrl = EMIF_SDREF,
.sdram_tim1 = EMIF_TIM1,
.sdram_tim2 = EMIF_TIM2,
.sdram_tim3 = EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
};
static const struct cmd_control ddr3_ctrl = {
.cmd0csratio = 0x100,
.cmd0iclkout = 0x001,
.cmd1csratio = 0x100,
.cmd1iclkout = 0x001,
.cmd2csratio = 0x100,
.cmd2iclkout = 0x001,
};
/* These values are obtained from the CCS app */
#define RD_DQS_GATE (0x1B3)
#define RD_DQS (0x35)
#define WR_DQS (0x93)
static struct ddr_data ddr3_data = {
.datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
.datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
.datawiratio0 = ((0x20<<10) | 0x20<<0),
.datagiratio0 = ((0x20<<10) | 0x20<<0),
.datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
.datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
};
static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80640300,
.dmm_lisa_map_3 = 0xC0640320,
};
void sdram_init(void)
{
/*
* Pass in our DDR3 config information and that we have 2 EMIFs to
* configure.
*/
config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
&evm_lisa_map_regs, 2);
}
#endif /* CONFIG_SPL_BUILD */

82
configs/ti816x_evm_defconfig
View file

@ -1,82 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
CONFIG_SPL_TEXT_BASE=0x40400000
CONFIG_TI816X=y
CONFIG_TARGET_TI816X_EVM=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E0000
CONFIG_SYS_CLK_FREQ=27000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk"
CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MAX_SIZE=0xfff1b400
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set

1
drivers/i2c/Kconfig
View file

@ -744,7 +744,6 @@ config SYS_I2C_SPEED
config SYS_I2C_BUS_MAX
int "Max I2C busses"
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
default 2 if TI816X
default 3 if OMAP34XX || AM33XX || AM43XX
default 4 if ARCH_SOCFPGA || OMAP44XX
default 5 if OMAP54XX

4
drivers/net/ti/davinci_emac.c
View file

@ -833,9 +833,9 @@ static int davinci_emac_probe(struct udevice *dev)
#endif
}
#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
for (i = 0; i < num_phy; i++) {
if (phy[i].is_phy_connected(i))
phy[i].auto_negotiate(i);

2
drivers/pinctrl/exynos/pinctrl-exynos.h
View file

@ -6,7 +6,7 @@
*/
#ifndef __PINCTRL_EXYNOS_H_
#define __PINCTRL_EXYNOS__H_
#define __PINCTRL_EXYNOS_H_
#define PIN_CON 0x00 /* Offset of pin function register */
#define PIN_DAT 0x04 /* Offset of pin data register */

4
include/.gitignore vendored
View file

@ -1,4 +0,0 @@
/autoconf.mk*
/bmp_logo.h
/bmp_logo_data.h
/config.h

37
include/ali512x.h
View file

@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
*/
#ifndef __ASM_IC_ALI512X_H_
#define __ASM_IC_ALI512X_H_
# define ALI_INDEX 0x3f0
# define ALI_DATA 0x3f1
# define ALI_ENABLED 1
# define ALI_DISABLED 0
# define ALI_UART1 0
# define ALI_UART2 1
/* setup functions */
void ali512x_init(void);
void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
void ali512x_set_rtc(int enabled, u16 io, u8 irq);
void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
void ali512x_set_cio(int enabled);
/* common I/O functions */
void ali512x_cio_function(int pin, int special, int inv, int input);
void ali512x_cio_out(int pin, int value);
int ali512x_cio_in(int pin);
/* misc features */
void ali512x_set_uart2_irda(int enabled);
#endif

354
include/andestech/andes_pcu.h
View file

@ -1,354 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*/
/*
* Andes Power Control Unit
*/
#ifndef __ANDES_PCU_H
#define __ANDES_PCU_H
#ifndef __ASSEMBLY__
struct pcs {
unsigned int cr; /* PCSx Configuration (clock scaling) */
unsigned int parm; /* PCSx Parameter*/
unsigned int stat1; /* PCSx Status 1 */
unsigned int stat2; /* PCSx Stusts 2 */
unsigned int pdd; /* PCSx PDD */
};
struct andes_pcu {
unsigned int rev; /* 0x00 - PCU Revision */
unsigned int spinfo; /* 0x04 - Scratch Pad Info */
unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
unsigned int soc_id; /* 0x10 - SoC ID */
unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
unsigned int soc_apb; /* 0x18 - SoC APB configuration */
unsigned int rsvd2; /* 0x1C */
unsigned int dcsrcr0; /* 0x20 - Driving Capability
and Slew Rate Control 0 */
unsigned int dcsrcr1; /* 0x24 - Driving Capability
and Slew Rate Control 1 */
unsigned int dcsrcr2; /* 0x28 - Driving Capability
and Slew Rate Control 2 */
unsigned int rsvd3; /* 0x2C */
unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
unsigned int dmaes; /* 0x38 - DMA Engine Selection */
unsigned int rsvd4; /* 0x3C */
unsigned int oscc; /* 0x40 - OSC Control */
unsigned int pwmcd; /* 0x44 - PWM Clock divider */
unsigned int socmisc; /* 0x48 - SoC Misc. */
unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
unsigned int bsmcr; /* 0x80 - BSM Controrl */
unsigned int bsmst; /* 0x84 - BSM Status */
unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
unsigned int west; /* 0x8C - Wakeup Event Status */
unsigned int rsttiming; /* 0x90 - Reset Timing */
unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
Scratch Pad Memory 0 */
};
#endif /* __ASSEMBLY__ */
/*
* PCU Revision Register (ro)
*/
#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
/*
* Scratch Pad Info Register (ro)
*/
#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
/*
* SoC ID Register (ro)
*/
#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
/*
* SoC AHB Configuration Register (ro)
*/
#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
/*
* SoC APB Configuration Register (ro)
*/
#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
/*
* Driving Capability and Slew Rate Control Register 0 (rw)
*/
#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
/*
* Driving Capability and Slew Rate Control Register 1 (rw)
*/
#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
/*
* Driving Capability and Slew Rate Control Register 2 (rw)
*/
#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
/*
* Multi-function Port Setting Register 0 (rw)
*/
#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
/*
* Multi-function Port Setting Register 1 (rw)
*/
#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
/*
* DMA Engine Selection Register (rw)
*/
#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
/*
* OSC Control Register (rw)
*/
#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
/*
* PWM Clock Divider Register (rw)
*/
#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
/*
* SoC Misc. Register (rw)
*/
#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
/*
* BSM Control Register (rw)
*/
#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
/*
* BSM Status Register
*/
#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
/*
* Wakeup Event Sensitivity Register (rw)
*/
#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
/*
* Wakeup Event Status Register (ro)
*/
#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
/*
* Reset Timing Register
*/
#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
/*
* PCU Interrupt Status Register
*/
#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
/*
* PCSx Configuration Register
*/
#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
/*
* PCSx Parameter Register (rw)
*/
#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
/*
* PCSx Status Register 1
*/
#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
/*
* PCSx Status Register 2
*/
#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
/*
* PCSx PDD Register
* This is reserved for PCS(1-7)
*/
#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
#endif /* __ANDES_PCU_H */

9
include/asm-generic/types.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_GENERIC_TYPES_H
#define _ASM_GENERIC_TYPES_H
/*
* int-ll64 is used everywhere now.
*/
#include <asm-generic/int-ll64.h>
#endif /* _ASM_GENERIC_TYPES_H */

63
include/configs/ti816x_evm.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ti816x_evm.h
*
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
* Antoine Tenart, <atenart@adeneo-embedded.com>
*/
#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H
#include <configs/ti_armv7_omap.h>
#include <asm/arch/omap.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
#define CFG_SYS_SDRAM_BASE 0x80000000
/**
* Platform/Board specific defs
*/
#define CFG_SYS_TIMERBASE 0x4802E000
/*
* NS16550 Configuration
*/
#define CFG_SYS_NS16550_CLK (48000000)
#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
/* allow overwriting serial config and ethaddr */
/*
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.
*/
#define CFG_SYS_NAND_BASE 0x8000000
/* NAND: SPL related configs */
/* NAND: device related configs */
/* NAND: driver related configs */
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
/* SPL */
/* Defines for SPL */
#endif

84
include/dp83848.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* DP83848 ethernet Physical layer
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
*/
/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
/*--Bit definitions: DP83848_CTL_REG */
#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
#define DP83848_SPEED_SELECT (1 << 13)
#define DP83848_AUTONEG (1 << 12)
#define DP83848_POWER_DOWN (1 << 11)
#define DP83848_ISOLATE (1 << 10)
#define DP83848_RESTART_AUTONEG (1 << 9)
#define DP83848_DUPLEX_MODE (1 << 8)
#define DP83848_COLLISION_TEST (1 << 7)
/*--Bit definitions: DP83848_STAT_REG */
#define DP83848_100BASE_T4 (1 << 15)
#define DP83848_100BASE_TX_FD (1 << 14)
#define DP83848_100BASE_TX_HD (1 << 13)
#define DP83848_10BASE_T_FD (1 << 12)
#define DP83848_10BASE_T_HD (1 << 11)
#define DP83848_MF_PREAMB_SUPPR (1 << 6)
#define DP83848_AUTONEG_COMP (1 << 5)
#define DP83848_RMT_FAULT (1 << 4)
#define DP83848_AUTONEG_ABILITY (1 << 3)
#define DP83848_LINK_STATUS (1 << 2)
#define DP83848_JABBER_DETECT (1 << 1)
#define DP83848_EXTEND_CAPAB (1 << 0)
/*--definitions: DP83848_PHYID1 */
#define DP83848_PHYID1_OUI 0x2000
#define DP83848_PHYID2_OUI 0x5c90
/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
#define DP83848_NP (1 << 15)
#define DP83848_ACK (1 << 14)
#define DP83848_RF (1 << 13)
#define DP83848_PAUSE (1 << 10)
#define DP83848_T4 (1 << 9)
#define DP83848_TX_FDX (1 << 8)
#define DP83848_TX_HDX (1 << 7)
#define DP83848_10_FDX (1 << 6)
#define DP83848_10_HDX (1 << 5)
#define DP83848_AN_IEEE_802_3 0x0001
/*--Bit definitions: DP83848_ANER */
#define DP83848_PDF (1 << 4)
#define DP83848_LP_NP_ABLE (1 << 3)
#define DP83848_NP_ABLE (1 << 2)
#define DP83848_PAGE_RX (1 << 1)
#define DP83848_LP_AN_ABLE (1 << 0)
/*--Bit definitions: DP83848_PHY_STAT */
#define DP83848_RX_ERR_LATCH (1 << 13)
#define DP83848_POLARITY_STAT (1 << 12)
#define DP83848_FALSE_CAR_SENSE (1 << 11)
#define DP83848_SIG_DETECT (1 << 10)
#define DP83848_DESCRAM_LOCK (1 << 9)
#define DP83848_PAGE_RCV (1 << 8)
#define DP83848_PHY_RMT_FAULT (1 << 6)
#define DP83848_JABBER (1 << 5)
#define DP83848_AUTONEG_COMPLETE (1 << 4)
#define DP83848_LOOPBACK_STAT (1 << 3)
#define DP83848_DUPLEX (1 << 2)
#define DP83848_SPEED (1 << 1)
#define DP83848_LINK (1 << 0)

14
include/ds1722.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _DS1722_H_
#define _DS1722_H_
#define DS1722_RESOLUTION_8BIT 0x0
#define DS1722_RESOLUTION_9BIT 0x1
#define DS1722_RESOLUTION_10BIT 0x2
#define DS1722_RESOLUTION_11BIT 0x3
#define DS1722_RESOLUTION_12BIT 0x4
int ds1722_probe(int dev);
#endif /* _DS1722_H_ */

81
include/exynos_lcd.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* exynos_lcd.h - Exynos LCD Controller structures
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#ifndef _EXYNOS_LCD_H_
#define _EXYNOS_LCD_H_
enum {
FIMD_RGB_INTERFACE = 1,
FIMD_CPU_INTERFACE = 2,
};
enum exynos_fb_rgb_mode_t {
MODE_RGB_P = 0,
MODE_BGR_P = 1,
MODE_RGB_S = 2,
MODE_BGR_S = 3,
};
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_freq; /* Frequency */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix; /* Bits per pixel */
/* Horizontal control register. Timing from data sheet */
u_char vl_hspw; /* Horz sync pulse width */
u_char vl_hfpd; /* Wait before of line */
u_char vl_hbpd; /* Wait end of line */
/* Vertical control register. */
u_char vl_vspw; /* Vertical sync pulse width */
u_char vl_vfpd; /* Wait before of frame */
u_char vl_vbpd; /* Wait end of frame */
u_char vl_cmd_allow_len; /* Wait end of frame */
unsigned int win_id;
unsigned int init_delay;
unsigned int power_on_delay;
unsigned int reset_delay;
unsigned int interface_mode;
unsigned int mipi_enabled;
unsigned int dp_enabled;
unsigned int cs_setup;
unsigned int wr_setup;
unsigned int wr_act;
unsigned int wr_hold;
unsigned int logo_on;
unsigned int logo_width;
unsigned int logo_height;
int logo_x_offset;
int logo_y_offset;
unsigned long logo_addr;
unsigned int rgb_mode;
unsigned int resolution;
/* parent clock name(MPLL, EPLL or VPLL) */
unsigned int pclk_name;
/* ratio value for source clock from parent clock. */
unsigned int sclk_div;
unsigned int dual_lcd_enabled;
struct exynos_fb *reg;
struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
} vidinfo_t;
#endif

46
include/faraday/ftahbc020s.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*/
/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
#ifndef __FTAHBC020S_H
#define __FTAHBC202S_H
/* Registers Offsets */
/*
* AHB Slave BSR, offset: n * 4, n=0~31
*/
#ifndef __ASSEMBLY__
struct ftahbc02s {
unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */
unsigned int pcr; /* 0x80 - Priority Ctrl Reg */
unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */
unsigned int cr; /* 0x88 - Ctrl Reg */
};
#endif /* __ASSEMBLY__ */
/*
* FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
*/
#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20)
#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16)
/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */
/*
* FTAHBC020S_PCR - Priority Control Register
*/
#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */
/*
* FTAHBC020S_CR - Interrupt Control Register
*/
#define FTAHBC020S_CR_INTSTS (1 << 24)
#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20)
#define FTAHBC020S_CR_INTSMASK (1 << 16)
#define FTAHBC020S_CR_REMAP (1 << 0)
#endif /* __FTAHBC020S_H */

84
include/faraday/ftpci100.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
*
* Copyright (C) 2010 Andes Technology Corporation
* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*/
#ifndef __FTPCI100_H
#define __FTPCI100_H
/* AHB Control Registers */
#include <linux/bitops.h>
struct ftpci100_ahbc {
unsigned int iosize; /* 0x00 - I/O Space Size Signal */
unsigned int prot; /* 0x04 - AHB Protection */
unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
unsigned int conf; /* 0x28 - PCI Configuration */
unsigned int data; /* 0x2c - PCI Configuration DATA */
};
/*
* FTPCI100_IOSIZE_REG's constant definitions
*/
#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
/*
* PCI Configuration Register
*/
#define PCI_INT_MASK 0x4c
#define PCI_MEM_BASE_SIZE1 0x50
#define PCI_MEM_BASE_SIZE2 0x54
#define PCI_MEM_BASE_SIZE3 0x58
/*
* PCI_INT_MASK's bit definitions
*/
#define PCI_INTA_ENABLE (1 << 22)
#define PCI_INTB_ENABLE (1 << 23)
#define PCI_INTC_ENABLE (1 << 24)
#define PCI_INTD_ENABLE (1 << 25)
/*
* PCI_MEM_BASE_SIZE1's constant definitions
*/
#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
#define FTPCI100_MAX_FUNCTIONS 20
#define PCI_IRQ_LINES 4
#define MAX_BUS_NUM 256
#define MAX_DEV_NUM 32
#define MAX_FUN_NUM 8
#define PCI_MAX_BAR_PER_FUNC 6
/*
* PCI_MEM_SIZE
*/
#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
/* This definition is used by pci_ftpci_init() */
#define FTPCI100_BRIDGE_VENDORID 0x159b
#define FTPCI100_BRIDGE_DEVICEID 0x4321
void pci_ftpci_init(void);
struct pcibar {
unsigned int size;
unsigned int addr;
};
struct pci_config {
unsigned int bus;
unsigned int dev; /* device */
unsigned int func;
unsigned int pin;
unsigned short v_id; /* vendor id */
unsigned short d_id; /* device id */
struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
};
#endif

90
include/faraday/ftsdmc020.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*/
/*
* SDRAM Controller
*/
#ifndef __FTSDMC020_H
#define __FTSDMC020_H
#define FTSDMC020_OFFSET_TP0 0x00
#define FTSDMC020_OFFSET_TP1 0x04
#define FTSDMC020_OFFSET_CR 0x08
#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
#define FTSDMC020_OFFSET_BANK1_BSR 0x10
#define FTSDMC020_OFFSET_BANK2_BSR 0x14
#define FTSDMC020_OFFSET_BANK3_BSR 0x18
#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
#define FTSDMC020_OFFSET_BANK5_BSR 0x20
#define FTSDMC020_OFFSET_BANK6_BSR 0x24
#define FTSDMC020_OFFSET_BANK7_BSR 0x28
#define FTSDMC020_OFFSET_ACR 0x34
/*
* Timing Parametet 0 Register
*/
#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
/*
* Timing Parametet 1 Register
*/
#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
/*
* Configuration Register
*/
#define FTSDMC020_CR_SREF (1 << 0)
#define FTSDMC020_CR_PWDN (1 << 1)
#define FTSDMC020_CR_ISMR (1 << 2)
#define FTSDMC020_CR_IREF (1 << 3)
#define FTSDMC020_CR_IPREC (1 << 4)
#define FTSDMC020_CR_REFTYPE (1 << 5)
/*
* SDRAM External Bank Base/Size Register
*/
#define FTSDMC020_BANK_ENABLE (1 << 28)
#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
#define FTSDMC020_BANK_DDW_X4 (0 << 12)
#define FTSDMC020_BANK_DDW_X8 (1 << 12)
#define FTSDMC020_BANK_DDW_X16 (2 << 12)
#define FTSDMC020_BANK_DDW_X32 (3 << 12)
#define FTSDMC020_BANK_DSZ_16M (0 << 8)
#define FTSDMC020_BANK_DSZ_64M (1 << 8)
#define FTSDMC020_BANK_DSZ_128M (2 << 8)
#define FTSDMC020_BANK_DSZ_256M (3 << 8)
#define FTSDMC020_BANK_MBW_8 (0 << 4)
#define FTSDMC020_BANK_MBW_16 (1 << 4)
#define FTSDMC020_BANK_MBW_32 (2 << 4)
#define FTSDMC020_BANK_SIZE_1M 0x0
#define FTSDMC020_BANK_SIZE_2M 0x1
#define FTSDMC020_BANK_SIZE_4M 0x2
#define FTSDMC020_BANK_SIZE_8M 0x3
#define FTSDMC020_BANK_SIZE_16M 0x4
#define FTSDMC020_BANK_SIZE_32M 0x5
#define FTSDMC020_BANK_SIZE_64M 0x6
#define FTSDMC020_BANK_SIZE_128M 0x7
#define FTSDMC020_BANK_SIZE_256M 0x8
/*
* Arbiter Control Register
*/
#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
#define FTSDMC020_ACR_TOE (1 << 8)
#endif /* __FTSDMC020_H */

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include/faraday/ftsdmc021.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*/
/*
* FTSDMC021 - SDRAM Controller
*/
#ifndef __FTSDMC021_H
#define __FTSDMC021_H
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
struct ftsdmc021 {
unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */
unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */
unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */
unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */
unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */
unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */
unsigned int frr; /* 0x34 - Flush Request Register */
unsigned int ebisr; /* 0x38 - EBI Support Register */
unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */
unsigned int crr; /* 0x100 - Controller Revision Reg */
unsigned int cfr; /* 0x104 - Controller Feature Reg */
};
#endif /* __ASSEMBLY__ */
/*
* Timing Parameter 1 Register
*/
#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */
#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */
#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */
#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */
#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */
#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
/*
* Timing Parameter 2 Register
*/
#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */
/* b(16:19) - Initial Refresh Times */
#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
/* b(20:23) - Initial Pre-Charge Times */
#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
/*
* SDRAM Configuration Register 1
*/
#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */
#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */
#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */
#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */
/* b(16) MA2T: Double Memory Address Cycle Enable */
#define FTSDMC021_CR1_MA2T(x) (1 << 16)
/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1)
/*
* Configuration Register 2
*/
#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */
#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */
#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */
#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */
#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */
#define FTSDMC021_CR2_REFTYPE (1 << 5)
/*
* SDRAM External Bank Base/Size Register
*/
#define FTSDMC021_BANK_ENABLE (1 << 12)
/* 12-bit base address of external bank.
* Default value is 0x800.
* The 12-bit equals to the haddr[31:20] of AHB address bus. */
#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
/*
* Read Arbitration Grant Window Register
*/
#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
/*
* Flush Request Register
*/
#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */
/*
* External Bus Interface Support Register (EBISR)
*/
#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */
#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */
#define FTSDMC021_EBISR_POPREC (1 << 13)
#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */
/*
* Controller Revision Register (CRR, Read Only)
*/
#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
/*
* Controller Feature Register (CFR, Read Only)
*/
#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
#endif /* __FTSDMC021_H */

2
include/imx_sip.h
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@ -4,7 +4,7 @@
*/
#ifndef _IMX_SIP_H__
#define _IMX_SIP_H_
#define _IMX_SIP_H__
#define IMX_SIP_GPC 0xC2000000
#define IMX_SIP_GPC_PM_DOMAIN 0x03

102
include/lcd_console.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*/
/* By default we scroll by a single line */
struct console_t {
short curr_col, curr_row;
short cols, rows;
void *fbbase;
u32 lcdsizex, lcdsizey, lcdrot;
void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c);
void (*fp_console_moverow)(struct console_t *pcons,
u32 rowdst, u32 rowsrc);
void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
};
/**
* console_calc_rowcol() - calculate available rows / columns wihtin a given
* screen-size based on used VIDEO_FONT.
*
* @pcons: Pointer to struct console_t
* @sizex: size X of the screen in pixel
* @sizey: size Y of the screen in pixel
*/
void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey);
/**
* lcd_init_console() - Initialize lcd console parameters
*
* Setup the address of console base, and the number of rows and columns the
* console has.
*
* @address: Console base address
* @vl_rows: Number of rows in the console
* @vl_cols: Number of columns in the console
* @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise
*/
void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot);
/**
* lcd_set_col() - Set the number of the current lcd console column
*
* Set the number of the console column where the cursor is.
*
* @col: Column number
*/
void lcd_set_col(short col);
/**
* lcd_set_row() - Set the number of the current lcd console row
*
* Set the number of the console row where the cursor is.
*
* @row: Row number
*/
void lcd_set_row(short row);
/**
* lcd_position_cursor() - Position the cursor on the screen
*
* Position the cursor at the given coordinates on the screen.
*
* @col: Column number
* @row: Row number
*/
void lcd_position_cursor(unsigned col, unsigned row);
/**
* lcd_get_screen_rows() - Get the total number of screen rows
*
* @return: Number of screen rows
*/
int lcd_get_screen_rows(void);
/**
* lcd_get_screen_columns() - Get the total number of screen columns
*
* @return: Number of screen columns
*/
int lcd_get_screen_columns(void);
/**
* lcd_putc() - Print to screen a single character at the location of the cursor
*
* @c: The character to print
*/
void lcd_putc(const char c);
/**
* lcd_puts() - Print to screen a string at the location of the cursor
*
* @s: The string to print
*/
void lcd_puts(const char *s);
/**
* lcd_printf() - Print to screen a formatted string at location of the cursor
*
* @fmt: The formatted string to print
* @...: The arguments for the formatted string
*/
void lcd_printf(const char *fmt, ...);

69
include/lcdvideo.h
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/*
* MPC823 LCD and Video Controller
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*/
#ifndef __LCDVIDEO_H__
#define __LCDVIDEO_H__
/* LCD Controller Configuration Register.
*/
#define LCCR_BNUM ((uint)0xfffe0000)
#define LCCR_EIEN ((uint)0x00010000)
#define LCCR_IEN ((uint)0x00008000)
#define LCCR_IRQL ((uint)0x00007000)
#define LCCR_CLKP ((uint)0x00000800)
#define LCCR_OEP ((uint)0x00000400)
#define LCCR_HSP ((uint)0x00000200)
#define LCCR_VSP ((uint)0x00000100)
#define LCCR_DP ((uint)0x00000080)
#define LCCR_BPIX ((uint)0x00000060)
#define LCCR_LBW ((uint)0x00000010)
#define LCCR_SPLT ((uint)0x00000008)
#define LCCR_CLOR ((uint)0x00000004)
#define LCCR_TFT ((uint)0x00000002)
#define LCCR_PON ((uint)0x00000001)
/* Define the bit shifts to load values into the register.
*/
#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT))
#define LCCR_BNUM_BIT ((uint)14)
#define LCCR_EIEN_BIT ((uint)15)
#define LCCR_IEN_BIT ((uint)16)
#define LCCR_IROL_BIT ((uint)19)
#define LCCR_CLKP_BIT ((uint)20)
#define LCCR_OEP_BIT ((uint)21)
#define LCCR_HSP_BIT ((uint)22)
#define LCCR_VSP_BIT ((uint)23)
#define LCCR_DP_BIT ((uint)24)
#define LCCR_BPIX_BIT ((uint)26)
#define LCCR_LBW_BIT ((uint)27)
#define LCCR_SPLT_BIT ((uint)28)
#define LCCR_CLOR_BIT ((uint)29)
#define LCCR_TFT_BIT ((uint)30)
#define LCCR_PON_BIT ((uint)31)
/* LCD Horizontal control register.
*/
#define LCHCR_BO ((uint)0x01000000)
#define LCHCR_AT ((uint)0x00e00000)
#define LCHCR_HPC ((uint)0x001ffc00)
#define LCHCR_WBL ((uint)0x000003ff)
#define LCHCR_AT_BIT ((uint)10)
#define LCHCR_HPC_BIT ((uint)21)
#define LCHCR_WBL_BIT ((uint)31)
/* LCD Vertical control register.
*/
#define LCVCR_VPW ((uint)0xf0000000)
#define LCVCR_LCD_AC ((uint)0x01e00000)
#define LCVCR_VPC ((uint)0x001ff800)
#define LCVCR_WBF ((uint)0x000003ff)
#define LCVCR_VPW_BIT ((uint)3)
#define LCVCR_LCD_AC_BIT ((uint)10)
#define LCVCR_VPC_BIT ((uint)20)
#endif /* __LCDVIDEO_H__ */

86
include/linux/mc146818rtc.h
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/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
* Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
* derived from Data Sheet, Copyright Motorola 1984 (!).
* It was written to be part of the Linux operating system.
*/
/* permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
#ifndef _MC146818RTC_H
#define _MC146818RTC_H
#include <asm/io.h>
#include <linux/rtc.h> /* get the user-level API */
#include <asm/mc146818rtc.h> /* register access macros */
/**********************************************************************
* register summary
**********************************************************************/
#define RTC_SECONDS 0
#define RTC_SECONDS_ALARM 1
#define RTC_MINUTES 2
#define RTC_MINUTES_ALARM 3
#define RTC_HOURS 4
#define RTC_HOURS_ALARM 5
/* RTC_*_alarm is always true if 2 MSBs are set */
# define RTC_ALARM_DONT_CARE 0xC0
#define RTC_DAY_OF_WEEK 6
#define RTC_DAY_OF_MONTH 7
#define RTC_MONTH 8
#define RTC_YEAR 9
/* control registers - Moto names
*/
#define RTC_REG_A 10
#define RTC_REG_B 11
#define RTC_REG_C 12
#define RTC_REG_D 13
/**********************************************************************
* register details
**********************************************************************/
#define RTC_FREQ_SELECT RTC_REG_A
/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
* totalling to a max high interval of 2.228 ms.
*/
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
# define RTC_REF_CLCK_4MHZ 0x00
# define RTC_REF_CLCK_1MHZ 0x10
# define RTC_REF_CLCK_32KHZ 0x20
/* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70
/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
# define RTC_RATE_SELECT 0x0F
/**********************************************************************/
#define RTC_CONTROL RTC_REG_B
# define RTC_SET 0x80 /* disable updates for clock setting */
# define RTC_PIE 0x40 /* periodic interrupt enable */
# define RTC_AIE 0x20 /* alarm interrupt enable */
# define RTC_UIE 0x10 /* update-finished interrupt enable */
# define RTC_SQWE 0x08 /* enable square-wave output */
# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
/**********************************************************************/
#define RTC_INTR_FLAGS RTC_REG_C
/* caution - cleared by read */
# define RTC_IRQF 0x80 /* any of the following 3 is active */
# define RTC_PF 0x40
# define RTC_AF 0x20
# define RTC_UF 0x10
/**********************************************************************/
#define RTC_VALID RTC_REG_D
# define RTC_VRT 0x80 /* valid RAM and time */
/**********************************************************************/
#endif /* _MC146818RTC_H */

207
include/linux/mtd/doc2000.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Linux driver for Disk-On-Chip devices
*
* Copyright © 1999 Machine Vision Holdings, Inc.
* Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
* Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
* Copyright © 2002-2003 SnapGear Inc
*
*/
#ifndef __MTD_DOC2000_H__
#define __MTD_DOC2000_H__
#include <linux/mtd/mtd.h>
#if 0
#include <linux/mutex.h>
#endif
#define DoC_Sig1 0
#define DoC_Sig2 1
#define DoC_ChipID 0x1000
#define DoC_DOCStatus 0x1001
#define DoC_DOCControl 0x1002
#define DoC_FloorSelect 0x1003
#define DoC_CDSNControl 0x1004
#define DoC_CDSNDeviceSelect 0x1005
#define DoC_ECCConf 0x1006
#define DoC_2k_ECCStatus 0x1007
#define DoC_CDSNSlowIO 0x100d
#define DoC_ECCSyndrome0 0x1010
#define DoC_ECCSyndrome1 0x1011
#define DoC_ECCSyndrome2 0x1012
#define DoC_ECCSyndrome3 0x1013
#define DoC_ECCSyndrome4 0x1014
#define DoC_ECCSyndrome5 0x1015
#define DoC_AliasResolution 0x101b
#define DoC_ConfigInput 0x101c
#define DoC_ReadPipeInit 0x101d
#define DoC_WritePipeTerm 0x101e
#define DoC_LastDataRead 0x101f
#define DoC_NOP 0x1020
#define DoC_Mil_CDSN_IO 0x0800
#define DoC_2k_CDSN_IO 0x1800
#define DoC_Mplus_NOP 0x1002
#define DoC_Mplus_AliasResolution 0x1004
#define DoC_Mplus_DOCControl 0x1006
#define DoC_Mplus_AccessStatus 0x1008
#define DoC_Mplus_DeviceSelect 0x1008
#define DoC_Mplus_Configuration 0x100a
#define DoC_Mplus_OutputControl 0x100c
#define DoC_Mplus_FlashControl 0x1020
#define DoC_Mplus_FlashSelect 0x1022
#define DoC_Mplus_FlashCmd 0x1024
#define DoC_Mplus_FlashAddress 0x1026
#define DoC_Mplus_FlashData0 0x1028
#define DoC_Mplus_FlashData1 0x1029
#define DoC_Mplus_ReadPipeInit 0x102a
#define DoC_Mplus_LastDataRead 0x102c
#define DoC_Mplus_LastDataRead1 0x102d
#define DoC_Mplus_WritePipeTerm 0x102e
#define DoC_Mplus_ECCSyndrome0 0x1040
#define DoC_Mplus_ECCSyndrome1 0x1041
#define DoC_Mplus_ECCSyndrome2 0x1042
#define DoC_Mplus_ECCSyndrome3 0x1043
#define DoC_Mplus_ECCSyndrome4 0x1044
#define DoC_Mplus_ECCSyndrome5 0x1045
#define DoC_Mplus_ECCConf 0x1046
#define DoC_Mplus_Toggle 0x1046
#define DoC_Mplus_DownloadStatus 0x1074
#define DoC_Mplus_CtrlConfirm 0x1076
#define DoC_Mplus_Power 0x1fff
/* How to access the device?
* On ARM, it'll be mmap'd directly with 32-bit wide accesses.
* On PPC, it's mmap'd and 16-bit wide.
* Others use readb/writeb
*/
#if defined(__arm__)
#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
#define DOC_IOREMAP_LEN 0x8000
#elif defined(__ppc__)
#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
#define DOC_IOREMAP_LEN 0x4000
#else
#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg))
#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg))
#define DOC_IOREMAP_LEN 0x2000
#endif
#if defined(__i386__) || defined(__x86_64__)
#define USE_MEMCPY
#endif
/* These are provided to directly use the DoC_xxx defines */
#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg)
#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg)
#define DOC_MODE_RESET 0
#define DOC_MODE_NORMAL 1
#define DOC_MODE_RESERVED1 2
#define DOC_MODE_RESERVED2 3
#define DOC_MODE_CLR_ERR 0x80
#define DOC_MODE_RST_LAT 0x10
#define DOC_MODE_BDECT 0x08
#define DOC_MODE_MDWREN 0x04
#define DOC_ChipID_Doc2k 0x20
#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */
#define DOC_ChipID_DocMil 0x30
#define DOC_ChipID_DocMilPlus32 0x40
#define DOC_ChipID_DocMilPlus16 0x41
#define CDSN_CTRL_FR_B 0x80
#define CDSN_CTRL_FR_B0 0x40
#define CDSN_CTRL_FR_B1 0x80
#define CDSN_CTRL_ECC_IO 0x20
#define CDSN_CTRL_FLASH_IO 0x10
#define CDSN_CTRL_WP 0x08
#define CDSN_CTRL_ALE 0x04
#define CDSN_CTRL_CLE 0x02
#define CDSN_CTRL_CE 0x01
#define DOC_ECC_RESET 0
#define DOC_ECC_ERROR 0x80
#define DOC_ECC_RW 0x20
#define DOC_ECC__EN 0x08
#define DOC_TOGGLE_BIT 0x04
#define DOC_ECC_RESV 0x02
#define DOC_ECC_IGNORE 0x01
#define DOC_FLASH_CE 0x80
#define DOC_FLASH_WP 0x40
#define DOC_FLASH_BANK 0x02
/* We have to also set the reserved bit 1 for enable */
#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
#define DOC_ECC_DIS (DOC_ECC_RESV)
struct Nand {
char floor, chip;
unsigned long curadr;
unsigned char curmode;
/* Also some erase/write/pipeline info when we get that far */
};
#define MAX_FLOORS 4
#define MAX_CHIPS 4
#define MAX_FLOORS_MIL 1
#define MAX_CHIPS_MIL 1
#define MAX_FLOORS_MPLUS 2
#define MAX_CHIPS_MPLUS 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
struct DiskOnChip {
unsigned long physadr;
void __iomem *virtadr;
unsigned long totlen;
unsigned char ChipID; /* Type of DiskOnChip */
int ioreg;
unsigned long mfr; /* Flash IDs - only one type of flash per device */
unsigned long id;
int chipshift;
char page256;
char pageadrlen;
char interleave; /* Internal interleaving - Millennium Plus style */
unsigned long erasesize;
int curfloor;
int curchip;
int numchips;
struct Nand *chips;
struct mtd_info *nextdoc;
/* XXX U-BOOT XXX */
#if 0
struct mutex lock;
#endif
};
int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
/* XXX U-BOOT XXX */
#if 1
/*
* NAND Flash Manufacturer ID Codes
*/
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
#endif
#endif /* __MTD_DOC2000_H__ */

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include/linux/mtd/ndfc.h
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/*
* linux/include/linux/mtd/ndfc.h
*
* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Info:
* Contains defines, datastructures for ndfc nand controller
*
*/
#ifndef __LINUX_MTD_NDFC_H
#define __LINUX_MTD_NDFC_H
/* NDFC Register definitions */
#define NDFC_CMD 0x00
#define NDFC_ALE 0x04
#define NDFC_DATA 0x08
#define NDFC_ECC 0x10
#define NDFC_BCFG0 0x30
#define NDFC_BCFG1 0x34
#define NDFC_BCFG2 0x38
#define NDFC_BCFG3 0x3c
#define NDFC_CCR 0x40
#define NDFC_STAT 0x44
#define NDFC_HWCTL 0x48
#define NDFC_REVID 0x50
#define NDFC_STAT_IS_READY 0x01000000
#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
#define NDFC_MAX_BANKS 4
struct ndfc_controller_settings {
uint32_t ccr_settings;
uint64_t ndfc_erpn;
};
struct ndfc_chip_settings {
uint32_t bank_settings;
};
#endif

1445
include/linux_logo.h
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131
include/lxt971a.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
* @Author: Markus Pietrek
* @References: [1] NS9750 Hardware Reference, December 2003
* [2] Intel LXT971 Datasheet #249414 Rev. 02
* [3] NS7520 Linux Ethernet Driver
*/
#ifndef __LXT971A_H__
#define __LXT971A_H__
/* PHY definitions (LXT971A) [2] */
#define PHY_LXT971_PORT_CFG (0x10)
#define PHY_LXT971_STAT2 (0x11)
#define PHY_LXT971_INT_ENABLE (0x12)
#define PHY_LXT971_INT_STATUS (0x13)
#define PHY_LXT971_LED_CFG (0x14)
#define PHY_LXT971_DIG_CFG (0x1A)
#define PHY_LXT971_TX_CTRL (0x1E)
/* PORT_CFG Port Configuration Register Bit Fields */
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
#define PHY_LXT971_PORT_CFG_SQE (0x0200)
#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
/* STAT2 Status Register #2 Bit Fields */
#define PHY_LXT971_STAT2_RES1 (0x8000)
#define PHY_LXT971_STAT2_100BTX (0x4000)
#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
#define PHY_LXT971_STAT2_LINK (0x0400)
#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
#define PHY_LXT971_STAT2_RES2 (0x0040)
#define PHY_LXT971_STAT2_POLARITY (0x0020)
#define PHY_LXT971_STAT2_PAUSE (0x0010)
#define PHY_LXT971_STAT2_ERROR (0x0008)
#define PHY_LXT971_STAT2_RES3 (0x0007)
/* INT_ENABLE Interrupt Enable Register Bit Fields */
#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
/* INT_STATUS Interrupt Status Register Bit Fields */
#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
/* LED_CFG Interrupt LED Configuration Register Bit Fields */
#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
#define PHY_LXT971_LED_CFG_RES1 (0x0001)
/* only one of these values must be shifted for each SHIFT_LED? */
#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
#define PHY_LXT971_LED_CFG_LINK (0x0004)
#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
#define PHY_LXT971_LED_CFG_SPEED (0x0000)
/* DIG_CFG Digitial Configuration Register Bit Fields */
#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
#define PHY_LXT971_MDIO_MAX_CLK (8000000)
#define PHY_MDIO_MAX_CLK (2500000)
/* TX_CTRL Transmit Control Register Bit Fields
documentation is buggy for this register, therefore setting not included */
typedef enum
{
PHY_NONE = 0x0000, /* no PHY detected yet */
PHY_LXT971A = 0x0013
} PhyType;
#endif /* __LXT971A_H__ */

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include/mc13783.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
*/
#ifndef __MC13783_H__
#define __MC13783_H__
/* REG_MODE_0 */
#define VAUDIOEN (1 << 0)
#define VAUDIOSTBY (1 << 1)
#define VAUDIOMODE (1 << 2)
#define VIOHIEN (1 << 3)
#define VIOHISTBY (1 << 4)
#define VIOHIMODE (1 << 5)
#define VIOLOEN (1 << 6)
#define VIOLOSTBY (1 << 7)
#define VIOLOMODE (1 << 8)
#define VDIGEN (1 << 9)
#define VDIGSTBY (1 << 10)
#define VDIGMODE (1 << 11)
#define VGENEN (1 << 12)
#define VGENSTBY (1 << 13)
#define VGENMODE (1 << 14)
#define VRFDIGEN (1 << 15)
#define VRFDIGSTBY (1 << 16)
#define VRFDIGMODE (1 << 17)
#define VRFREFEN (1 << 18)
#define VRFREFSTBY (1 << 19)
#define VRFREFMODE (1 << 20)
#define VRFCPEN (1 << 21)
#define VRFCPSTBY (1 << 22)
#define VRFCPMODE (1 << 23)
/* REG_MODE_1 */
#define VSIMEN (1 << 0)
#define VSIMSTBY (1 << 1)
#define VSIMMODE (1 << 2)
#define VESIMEN (1 << 3)
#define VESIMSTBY (1 << 4)
#define VESIMMODE (1 << 5)
#define VCAMEN (1 << 6)
#define VCAMSTBY (1 << 7)
#define VCAMMODE (1 << 8)
#define VRFBGEN (1 << 9)
#define VRFBGSTBY (1 << 10)
#define VVIBEN (1 << 11)
#define VRF1EN (1 << 12)
#define VRF1STBY (1 << 13)
#define VRF1MODE (1 << 14)
#define VRF2EN (1 << 15)
#define VRF2STBY (1 << 16)
#define VRF2MODE (1 << 17)
#define VMMC1EN (1 << 18)
#define VMMC1STBY (1 << 19)
#define VMMC1MODE (1 << 20)
#define VMMC2EN (1 << 21)
#define VMMC2STBY (1 << 22)
#define VMMC2MODE (1 << 23)
#endif

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include/mc34704.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012 Freescale Semiconductor, Inc.
*/
#ifndef __MC34704_H__
#define __MC34704_H__
enum {
MC34704_RESERVED0_REG = 0, /* 0x00 */
MC34704_GENERAL1_REG, /* 0x01 */
MC34704_GENERAL2_REG, /* 0x02 */
MC34704_GENERAL3_REG, /* 0x03 */
MC34704_RESERVED4_REG, /* 0x04 */
MC34704_VGSET2_REG, /* 0x05 */
MC34704_REG2SET1_REG, /* 0x06 */
MC34704_REG2SET2_REG, /* 0x07 */
MC34704_REG3SET1_REG, /* 0x08 */
MC34704_REG3SET2_REG, /* 0x09 */
MC34704_REG4SET1_REG, /* 0x0a */
MC34704_REG4SET2_REG, /* 0x0b */
MC34704_REG5SET1_REG, /* 0x0c */
MC34704_REG5SET2_REG, /* 0x0d */
MC34704_REG5SET3_REG, /* 0x0e */
MC34704_RESERVEDF_REG, /* 0x0f */
MC34704_RESERVED10_REG, /* 0x10 */
MC34704_RESERVED11_REG, /* 0x11 */
MC34704_RESERVED12_REG, /* 0x12 */
MC34704_FSW2SET_REG, /* 0x13 */
MC34704_RESERVED14_REG, /* 0x14 */
MC34704_REG8SET1_REG, /* 0x15 */
MC34704_REG8SET2_REG, /* 0x16 */
MC34704_REG8SET3_REG, /* 0x17 */
MC34704_FAULTS_REG, /* 0x18 */
MC34704_I2CSET1, /* 0x19 */
MC34704_NUM_OF_REGS,
};
/* GENERAL2 register fields */
#define ONOFFE (1 << 0)
#define ONOFFD (1 << 1)
#define ONOFFA (1 << 3)
#define ALLOFF (1 << 4)
#endif /* __MC34704_H__ */

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include/mc9sdz60.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef __ASM_ARCH_MC9SDZ60_H
#define __ASM_ARCH_MC9SDZ60_H
/**
* Register addresses for the MC9SDZ60
*
* @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
* but not include/linux/mfd/mc9s08dz60/pmic.h
*
*/
enum mc9sdz60_reg {
MC9SDZ60_REG_VERSION = 0x00,
/* reserved 0x01 */
MC9SDZ60_REG_SECS = 0x02,
MC9SDZ60_REG_MINS = 0x03,
MC9SDZ60_REG_HRS = 0x04,
MC9SDZ60_REG_DAY = 0x05,
MC9SDZ60_REG_DATE = 0x06,
MC9SDZ60_REG_MONTH = 0x07,
MC9SDZ60_REG_YEAR = 0x08,
MC9SDZ60_REG_ALARM_SECS = 0x09,
MC9SDZ60_REG_ALARM_MINS = 0x0a,
MC9SDZ60_REG_ALARM_HRS = 0x0b,
/* reserved 0x0c */
/* reserved 0x0d */
MC9SDZ60_REG_TS_CONTROL = 0x0e,
MC9SDZ60_REG_X_LOW = 0x0f,
MC9SDZ60_REG_Y_LOW = 0x10,
MC9SDZ60_REG_XY_HIGH = 0x11,
MC9SDZ60_REG_X_LEFT_LOW = 0x12,
MC9SDZ60_REG_X_LEFT_HIGH = 0x13,
MC9SDZ60_REG_X_RIGHT = 0x14,
MC9SDZ60_REG_Y_TOP_LOW = 0x15,
MC9SDZ60_REG_Y_TOP_HIGH = 0x16,
MC9SDZ60_REG_Y_BOTTOM = 0x17,
/* reserved 0x18 */
/* reserved 0x19 */
MC9SDZ60_REG_RESET_1 = 0x1a,
MC9SDZ60_REG_RESET_2 = 0x1b,
MC9SDZ60_REG_POWER_CTL = 0x1c,
MC9SDZ60_REG_DELAY_CONFIG = 0x1d,
/* reserved 0x1e */
/* reserved 0x1f */
MC9SDZ60_REG_GPIO_1 = 0x20,
MC9SDZ60_REG_GPIO_2 = 0x21,
MC9SDZ60_REG_KPD_1 = 0x22,
MC9SDZ60_REG_KPD_2 = 0x23,
MC9SDZ60_REG_KPD_CONTROL = 0x24,
MC9SDZ60_REG_INT_ENABLE_1 = 0x25,
MC9SDZ60_REG_INT_ENABLE_2 = 0x26,
MC9SDZ60_REG_INT_FLAG_1 = 0x27,
MC9SDZ60_REG_INT_FLAG_2 = 0x28,
MC9SDZ60_REG_DES_FLAG = 0x29,
};
extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
#endif /* __ASM_ARCH_MC9SDZ60_H */

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include/mii_phy.h
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#ifndef _MII_PHY_H_
#define _MII_PHY_H_
void mii_discover_phy(void);
unsigned short mii_phy_read(unsigned short reg);
void mii_phy_write(unsigned short reg, unsigned short val);
#endif

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include/mk48t59.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*/
/*
* Date & Time support for the MK48T59 RTC
*/
#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
#define RTC_PORT_ADDR0 0x70
#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
#define RTC_PORT_DATA 0x76
/* RTC Offsets */
#define RTC_SECONDS 0x1FF9
#define RTC_MINUTES 0x1FFA
#define RTC_HOURS 0x1FFB
#define RTC_DAY_OF_WEEK 0x1FFC
#define RTC_DAY_OF_MONTH 0x1FFD
#define RTC_MONTH 0x1FFE
#define RTC_YEAR 0x1FFF
#define RTC_CONTROLA 0x1FF8
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CA_CALIB_SIGN 0x20
#define RTC_CA_CALIB_MASK 0x1f
#define RTC_CONTROLB 0x1FF9
#define RTC_CB_STOP 0x80
#define RTC_WATCHDOG 0x1FF7
#define RTC_WDS 0x80
#define RTC_WD_RB_16TH 0x0
#define RTC_WD_RB_4TH 0x1
#define RTC_WD_RB_1 0x2
#define RTC_WD_RB_4 0x3
void rtc_set_watchdog(short multi, short res);
void *nvram_read(void *dest, const short src, size_t count);
void nvram_write(short dest, const void *src, size_t count);
#endif

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include/mpc106.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*/
#ifndef _MPC106_PCI_H
#define _MPC106_PCI_H
/*
* Defines for the MPC106 PCI Config address and data registers followed by
* defines for the standard PCI device configuration header.
*/
#define PCIDEVID_MPC106 0x0
/*
* MPC106 Registers
*/
#define MPC106_REG 0x80000000
#ifdef CONFIG_SYS_ADDRESS_MAP_A
#define MPC106_REG_ADDR 0x80000cf8
#define MPC106_REG_DATA 0x80000cfc
#define MPC106_ISA_IO_PHYS 0x80000000
#define MPC106_ISA_IO_BUS 0x00000000
#define MPC106_ISA_IO_SIZE 0x00800000
#define MPC106_PCI_IO_PHYS 0x81000000
#define MPC106_PCI_IO_BUS 0x01000000
#define MPC106_PCI_IO_SIZE 0x3e800000
#define MPC106_PCI_MEM_PHYS 0xc0000000
#define MPC106_PCI_MEM_BUS 0x00000000
#define MPC106_PCI_MEM_SIZE 0x3f000000
#define MPC106_PCI_MEMORY_PHYS 0x00000000
#define MPC106_PCI_MEMORY_BUS 0x80000000
#define MPC106_PCI_MEMORY_SIZE 0x80000000
#else
#define MPC106_REG_ADDR 0xfec00cf8
#define MPC106_REG_DATA 0xfee00cfc
#define MPC106_ISA_MEM_PHYS 0xfd000000
#define MPC106_ISA_MEM_BUS 0x00000000
#define MPC106_ISA_MEM_SIZE 0x01000000
#define MPC106_ISA_IO_PHYS 0xfe000000
#define MPC106_ISA_IO_BUS 0x00000000
#define MPC106_ISA_IO_SIZE 0x00800000
#define MPC106_PCI_IO_PHYS 0xfe800000
#define MPC106_PCI_IO_BUS 0x00800000
#define MPC106_PCI_IO_SIZE 0x00400000
#define MPC106_PCI_MEM_PHYS 0x80000000
#define MPC106_PCI_MEM_BUS 0x80000000
#define MPC106_PCI_MEM_SIZE 0x7d000000
#define MPC106_PCI_MEMORY_PHYS 0x00000000
#define MPC106_PCI_MEMORY_BUS 0x00000000
#define MPC106_PCI_MEMORY_SIZE 0x40000000
#endif
#define CMD_SERR 0x0100
#define PCI_CMD_MASTER 0x0004
#define PCI_CMD_MEMEN 0x0002
#define PCI_CMD_IOEN 0x0001
#define PCI_STAT_NO_RSV_BITS 0xffff
#define PCI_BUSNUM 0x40
#define PCI_SUBBUSNUM 0x41
#define PCI_DISCOUNT 0x42
#define PCI_PICR1 0xA8
#define PICR1_CF_CBA(value) ((value & 0xff) << 24)
#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
#define PICR1_PROC_TYPE_603 0x40000
#define PICR1_PROC_TYPE_604 0x60000
#define PICR1_MCP_EN 0x800
#define PICR1_CF_DPARK 0x200
#define PICR1_CF_LOOP_SNOOP 0x10
#define PICR1_CF_L2_COPY_BACK 0x2
#define PICR1_CF_L2_CACHE_MASK 0x3
#define PICR1_CF_APARK 0x8
#define PICR1_ADDRESS_MAP 0x10000
#define PICR1_XIO_MODE 0x80000
#define PICR1_CF_CACHE_1G 0x200000
#define PCI_PICR2 0xAC
#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18)
#define PICR2_CF_FLUSH_L2 0x10000000
#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2)
#define PICR2_CF_INV_MODE 0x00001000
#define PICR2_CF_MOD_HIGH 0x00020000
#define PICR2_CF_HIT_HIGH 0x00010000
#define PICR2_L2_SIZE_256K 0x00000000
#define PICR2_L2_SIZE_512K 0x00000010
#define PICR2_L2_SIZE_1MB 0x00000020
#define PICR2_L2_EN 0x40000000
#define PICR2_L2_UPDATE_EN 0x80000000
#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000
#define PICR2_CF_FAST_CASTOUT 0x00000080
#define PICR2_CF_WDATA 0x00000001
#define PICR2_CF_DATA_RAM_PBURST 0x00400000
/*
* Memory controller
*/
#define MPC106_MCCR1 0xF0
#define MCCR1_TYPE_EDO 0x00020000
#define MCCR1_BK0_9BITS 0x0
#define MCCR1_BK0_10BITS 0x1
#define MCCR1_BK0_11BITS 0x2
#define MCCR1_BK0_12BITS 0x3
#define MCCR1_BK1_9BITS 0x0
#define MCCR1_BK1_10BITS 0x4
#define MCCR1_BK1_11BITS 0x8
#define MCCR1_BK1_12BITS 0xC
#define MCCR1_BK2_9BITS 0x00
#define MCCR1_BK2_10BITS 0x10
#define MCCR1_BK2_11BITS 0x20
#define MCCR1_BK2_12BITS 0x30
#define MCCR1_BK3_9BITS 0x00
#define MCCR1_BK3_10BITS 0x40
#define MCCR1_BK3_11BITS 0x80
#define MCCR1_BK3_12BITS 0xC0
#define MCCR1_MEMGO 0x00080000
#define MPC106_MCCR2 0xF4
#define MPC106_MCCR3 0xF8
#define MPC106_MCCR4 0xFC
#define MPC106_MSAR1 0x80
#define MPC106_EMSAR1 0x88
#define MPC106_EMSAR2 0x8C
#define MPC106_MEAR1 0x90
#define MPC106_EMEAR1 0x98
#define MPC106_EMEAR2 0x9C
#define MPC106_MBER 0xA0
#define MBER_BANK0 0x1
#define MBER_BANK1 0x2
#define MBER_BANK2 0x4
#define MBER_BANK3 0x8
#endif

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include/mpc86xx.h
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/*
* Copyright 2006 Freescale Semiconductor.
* Jeffrey Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
#ifndef __MPC86xx_H__
#define __MPC86xx_H__
#include <asm/fsl_lbc.h>
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*
* platform register addresses
*/
#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4)
#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000)
#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008)
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
*/
#define l2cr 1017
#define L2CR_L2E 0x80000000 /* bit 0 - enable */
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
#define HID0_XBSEN 0x00000100
#define HID0_HIGH_BAT_EN 0x00800000
#define HID0_XAEN 0x00020000
#ifndef __ASSEMBLY__
typedef struct {
unsigned long freq_processor;
unsigned long freq_systembus;
unsigned long freq_localbus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
void l2cache_enable(void);
void l1dcache_enable(void);
static __inline__ unsigned long get_hid0 (void)
{
unsigned long hid0;
asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
return hid0;
}
static __inline__ unsigned long get_hid1 (void)
{
unsigned long hid1;
asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
return hid1;
}
static __inline__ void set_hid0 (unsigned long hid0)
{
asm volatile("mtspr 1008, %0" : : "r" (hid0));
}
static __inline__ void set_hid1 (unsigned long hid1)
{
asm volatile("mtspr 1009, %0" : : "r" (hid1));
}
static __inline__ unsigned long get_l2cr (void)
{
unsigned long l2cr_val;
asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
return l2cr_val;
}
void setup_ddr_bat(phys_addr_t dram_size);
extern void setup_bats(void);
#endif /* _ASMLANGUAGE */
#endif /* __MPC86xx_H__ */

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include/mvmfp.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*/
#ifndef __MVMFP_H
#define __MVMFP_H
/*
* Header file for MultiFunctionPin (MFP) Configururation framework
*
* Processors Supported:
* 1. Marvell ARMADA100 Processors
*
* processor to be supported should be added here
*/
/*
* MFP configuration is represented by a 32-bit unsigned integer
*/
#ifdef CONFIG_MVMFP_V2
#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
/* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
/* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
/* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \
/* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \
/* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \
/* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
/* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \
/* bits 02..00 - Alt-fun select */ ((_afn) & 0x7))
#else
#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
/* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
/* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
/* bit 12 - Unused */ \
/* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \
/* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \
/* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
/* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \
/* bits 02..00 - Alt-fun select */ ((_afn) & 0x7))
#endif
/*
* to facilitate the definition, the following macros are provided
*
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0)
#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0)
#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16)
#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0)
#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1)
#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2)
#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3)
#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4)
#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5)
#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6)
#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7)
#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7)
#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0)
#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0)
#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0)
#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0)
#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0)
#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0)
#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0)
#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0)
#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0)
#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0)
#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0)
#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0)
#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0)
#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0)
#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0)
#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0)
#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0)
#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0)
#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0)
#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0)
#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0)
#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0)
#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \
| MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \
| MFP_AF_MASK)
#define MFP_EOC 0xffffffff /* indicates end-of-conf */
/* Functions */
void mfp_config(u32 *mfp_cfgs);
#endif /* __MVMFP_H */

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include/pca9564.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* File: include/pca9564.h
* Author:
*
* Created: 2009-06-23
* Description: PCA9564 i2c bridge driver
*
* Modified:
* Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
*
* Bugs:
*/
#ifndef _PCA9564_H
#define _PCA9564_H
/* Clock speeds for the bus */
#define PCA_CON_330kHz 0x00
#define PCA_CON_288kHz 0x01
#define PCA_CON_217kHz 0x02
#define PCA_CON_146kHz 0x03
#define PCA_CON_88kHz 0x04
#define PCA_CON_59kHz 0x05
#define PCA_CON_44kHz 0x06
#define PCA_CON_36kHz 0x07
#define PCA_CON_AA 0x80 /* Assert Acknowledge */
#define PCA_CON_ENSIO 0x40 /* Enable */
#define PCA_CON_STA 0x20 /* Start */
#define PCA_CON_STO 0x10 /* Stop */
#define PCA_CON_SI 0x08 /* Serial Interrupt */
#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */
#endif

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include/sja1000.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
*
* SJA1000 register layout for basic CAN mode
*/
#ifndef _SJA1000_H_
#define _SJA1000_H_
/*
* SJA1000 register layout in basic can mode
*/
struct sja1000_basic_s {
u8 cr;
u8 cmr;
u8 sr;
u8 ir;
u8 ac;
u8 am;
u8 btr0;
u8 btr1;
u8 oc;
u8 txb[10];
u8 rxb[10];
u8 unused;
u8 cdr;
};
/* control register */
#define CR_RR 0x01
/* output control register */
#define OC_MODE0 0x01
#define OC_MODE1 0x02
#define OC_POL0 0x04
#define OC_TN0 0x08
#define OC_TP0 0x10
#define OC_POL1 0x20
#define OC_TN1 0x40
#define OC_TP1 0x80
#endif

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include/sym53c8xx.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* Most of these definitions are derived from
* linux/drivers/scsi/sym53c8xx_defs.h
*/
#ifndef _SYM53C8XX_DEFS_H
#define _SYM53C8XX_DEFS_H
#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
#define SCNTL1 0x01 /* no reset */
#define ISCON 0x10 /* connected to scsi */
#define CRST 0x08 /* force reset */
#define IARB 0x02 /* immediate arbitration */
#define SCNTL2 0x02 /* no disconnect expected */
#define SDU 0x80 /* cmd: disconnect will raise error */
#define CHM 0x40 /* sta: chained mode */
#define WSS 0x08 /* sta: wide scsi send [W]*/
#define WSR 0x01 /* sta: wide scsi received [W]*/
#define SCNTL3 0x03 /* cnf system clock dependent */
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
#define ULTRA 0x80 /* cmd: ULTRA enable */
/* bits 0-2, 7 rsvd for C1010 */
#define SCID 0x04 /* cnf host adapter scsi address */
#define RRE 0x40 /* r/w:e enable response to resel. */
#define SRE 0x20 /* r/w:e enable response to select */
#define SXFER 0x05 /* ### Sync speed and count */
/* bits 6-7 rsvd for C1010 */
#define SDID 0x06 /* ### Destination-ID */
#define GPREG 0x07 /* ??? IO-Pins */
#define SFBR 0x08 /* ### First byte in phase */
#define SOCL 0x09
#define CREQ 0x80 /* r/w: SCSI-REQ */
#define CACK 0x40 /* r/w: SCSI-ACK */
#define CBSY 0x20 /* r/w: SCSI-BSY */
#define CSEL 0x10 /* r/w: SCSI-SEL */
#define CATN 0x08 /* r/w: SCSI-ATN */
#define CMSG 0x04 /* r/w: SCSI-MSG */
#define CC_D 0x02 /* r/w: SCSI-C_D */
#define CI_O 0x01 /* r/w: SCSI-I_O */
#define SSID 0x0a
#define SBCL 0x0b
#define DSTAT 0x0c
#define DFE 0x80 /* sta: dma fifo empty */
#define MDPE 0x40 /* int: master data parity error */
#define BF 0x20 /* int: script: bus fault */
#define ABRT 0x10 /* int: script: command aborted */
#define SSI 0x08 /* int: script: single step */
#define SIR 0x04 /* int: script: interrupt instruct. */
#define IID 0x01 /* int: script: illegal instruct. */
#define SSTAT0 0x0d
#define ILF 0x80 /* sta: data in SIDL register lsb */
#define ORF 0x40 /* sta: data in SODR register lsb */
#define OLF 0x20 /* sta: data in SODL register lsb */
#define AIP 0x10 /* sta: arbitration in progress */
#define LOA 0x08 /* sta: arbitration lost */
#define WOA 0x04 /* sta: arbitration won */
#define IRST 0x02 /* sta: scsi reset signal */
#define SDP 0x01 /* sta: scsi parity signal */
#define SSTAT1 0x0e
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
#define SSTAT2 0x0f
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
#define LDSC 0x02 /* sta: disconnect & reconnect */
#define DSA 0x10 /* --> Base page */
#define DSA1 0x11
#define DSA2 0x12
#define DSA3 0x13
#define ISTAT 0x14 /* --> Main Command and status */
#define CABRT 0x80 /* cmd: abort current operation */
#define SRST 0x40 /* mod: reset chip */
#define SIGP 0x20 /* r/w: message from host to ncr */
#define SEM 0x10 /* r/w: message between host + ncr */
#define CON 0x08 /* sta: connected to scsi */
#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
#define SIP 0x02 /* sta: scsi-interrupt */
#define DIP 0x01 /* sta: host/script interrupt */
#define CTEST0 0x18
#define CTEST1 0x19
#define CTEST2 0x1a
#define CSIGP 0x40
/* bits 0-2,7 rsvd for C1010 */
#define CTEST3 0x1b
#define FLF 0x08 /* cmd: flush dma fifo */
#define CLF 0x04 /* cmd: clear dma fifo */
#define FM 0x02 /* mod: fetch pin mode */
#define WRIE 0x01 /* mod: write and invalidate enable */
/* bits 4-7 rsvd for C1010 */
#define DFIFO 0x20
#define CTEST4 0x21
#define BDIS 0x80 /* mod: burst disable */
#define MPEE 0x08 /* mod: master parity error enable */
#define CTEST5 0x22
#define DFS 0x20 /* mod: dma fifo size */
/* bits 0-1, 3-7 rsvd for C1010 */
#define CTEST6 0x23
#define DBC 0x24 /* ### Byte count and command */
#define DNAD 0x28 /* ### Next command register */
#define DSP 0x2c /* --> Script Pointer */
#define DSPS 0x30 /* --> Script pointer save/opcode#2 */
#define SCRATCHA 0x34 /* Temporary register a */
#define SCRATCHA1 0x35
#define SCRATCHA2 0x36
#define SCRATCHA3 0x37
#define DMODE 0x38
#define BL_2 0x80 /* mod: burst length shift value +2 */
#define BL_1 0x40 /* mod: burst length shift value +1 */
#define ERL 0x08 /* mod: enable read line */
#define ERMP 0x04 /* mod: enable read multiple */
#define BOF 0x02 /* mod: burst op code fetch */
#define MAN 0x01 /* mod: manual start */
#define DIEN 0x39
#define SBR 0x3a
#define DCNTL 0x3b /* --> Script execution control */
#define CLSE 0x80 /* mod: cache line size enable */
#define PFF 0x40 /* cmd: pre-fetch flush */
#define PFEN 0x20 /* mod: pre-fetch enable */
#define SSM 0x10 /* mod: single step mode */
#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
#define STD 0x04 /* cmd: start dma mode */
#define IRQD 0x02 /* mod: irq disable */
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
/* bits 0-1 rsvd for C1010 */
#define ADDER 0x3c
#define SIEN 0x40 /* -->: interrupt enable */
#define SIST 0x42 /* <--: interrupt status */
#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
#define STO 0x0400/* sta: timeout (select) */
#define GEN 0x0200/* sta: timeout (general) */
#define HTH 0x0100/* sta: timeout (handshake) */
#define MA 0x80 /* sta: phase mismatch */
#define CMP 0x40 /* sta: arbitration complete */
#define SEL 0x20 /* sta: selected by another device */
#define RSL 0x10 /* sta: reselected by another device*/
#define SGE 0x08 /* sta: gross error (over/underflow)*/
#define UDC 0x04 /* sta: unexpected disconnect */
#define RST 0x02 /* sta: scsi bus reset detected */
#define PAR 0x01 /* sta: scsi parity error */
#define SLPAR 0x44
#define SWIDE 0x45
#define MACNTL 0x46
#define GPCNTL 0x47
#define STIME0 0x48 /* cmd: timeout for select&handshake*/
#define STIME1 0x49 /* cmd: timeout user defined */
#define RESPID 0x4a /* sta: Reselect-IDs */
#define STEST0 0x4c
#define STEST1 0x4d
#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
#define DBLEN 0x08 /* clock doubler running */
#define DBLSEL 0x04 /* clock doubler selected */
#define STEST2 0x4e
#define ROF 0x40 /* reset scsi offset (after gross error!) */
#define EXT 0x02 /* extended filtering */
#define STEST3 0x4f
#define TE 0x80 /* c: tolerAnt enable */
#define HSC 0x20 /* c: Halt SCSI Clock */
#define CSF 0x02 /* c: clear scsi fifo */
#define SIDL 0x50 /* Lowlevel: latched from scsi data */
#define STEST4 0x52
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
#define SMODE_HVD 0x40 /* High Voltage Differential */
#define SMODE_SE 0x80 /* Single Ended */
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
/* bits 0-5 rsvd for C1010 */
#define SODL 0x54 /* Lowlevel: data out to scsi data */
#define SBDL 0x58 /* Lowlevel: data from scsi data */
/*-----------------------------------------------------------
**
** Utility macros for the script.
**
**-----------------------------------------------------------
*/
#define REG(r) (r)
/*-----------------------------------------------------------
**
** SCSI phases
**
** DT phases illegal for ncr driver.
**
**-----------------------------------------------------------
*/
#define SCR_DATA_OUT 0x00000000
#define SCR_DATA_IN 0x01000000
#define SCR_COMMAND 0x02000000
#define SCR_STATUS 0x03000000
#define SCR_DT_DATA_OUT 0x04000000
#define SCR_DT_DATA_IN 0x05000000
#define SCR_MSG_OUT 0x06000000
#define SCR_MSG_IN 0x07000000
#define SCR_ILG_OUT 0x04000000
#define SCR_ILG_IN 0x05000000
/*-----------------------------------------------------------
**
** Data transfer via SCSI.
**
**-----------------------------------------------------------
**
** MOVE_ABS (LEN)
** <<start address>>
**
** MOVE_IND (LEN)
** <<dnad_offset>>
**
** MOVE_TBL
** <<dnad_offset>>
**
**-----------------------------------------------------------
*/
#define OPC_MOVE 0x08000000
#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
#define SCR_CHMOV_TBL (0x10000000)
/*-----------------------------------------------------------
**
** Selection
**
**-----------------------------------------------------------
**
** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
** <<alternate_address>>
**
** SEL_TBL | << dnad_offset>> [ | REL_JMP]
** <<alternate_address>>
**
**-----------------------------------------------------------
*/
#define SCR_SEL_ABS 0x40000000
#define SCR_SEL_ABS_ATN 0x41000000
#define SCR_SEL_TBL 0x42000000
#define SCR_SEL_TBL_ATN 0x43000000
#define SCR_JMP_REL 0x04000000
#define SCR_ID(id) (((unsigned long)(id)) << 16)
/*-----------------------------------------------------------
**
** Waiting for Disconnect or Reselect
**
**-----------------------------------------------------------
**
** WAIT_DISC
** dummy: <<alternate_address>>
**
** WAIT_RESEL
** <<alternate_address>>
**
**-----------------------------------------------------------
*/
#define SCR_WAIT_DISC 0x48000000
#define SCR_WAIT_RESEL 0x50000000
/*-----------------------------------------------------------
**
** Bit Set / Reset
**
**-----------------------------------------------------------
**
** SET (flags {|.. })
**
** CLR (flags {|.. })
**
**-----------------------------------------------------------
*/
#define SCR_SET(f) (0x58000000 | (f))
#define SCR_CLR(f) (0x60000000 | (f))
#define SCR_CARRY 0x00000400
#define SCR_TRG 0x00000200
#define SCR_ACK 0x00000040
#define SCR_ATN 0x00000008
/*-----------------------------------------------------------
**
** Memory to memory move
**
**-----------------------------------------------------------
**
** COPY (bytecount)
** << source_address >>
** << destination_address >>
**
** SCR_COPY sets the NO FLUSH option by default.
** SCR_COPY_F does not set this option.
**
** For chips which do not support this option,
** ncr_copy_and_bind() will remove this bit.
**-----------------------------------------------------------
*/
#define SCR_NO_FLUSH 0x01000000
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
#define SCR_COPY_F(n) (0xc0000000 | (n))
/*-----------------------------------------------------------
**
** Register move and binary operations
**
**-----------------------------------------------------------
**
** SFBR_REG (reg, op, data) reg = SFBR op data
** << 0 >>
**
** REG_SFBR (reg, op, data) SFBR = reg op data
** << 0 >>
**
** REG_REG (reg, op, data) reg = reg op data
** << 0 >>
**
**-----------------------------------------------------------
** On 810A, 860, 825A, 875, 895 and 896 chips the content
** of SFBR register can be used as data (SCR_SFBR_DATA).
** The 896 has additionnal IO registers starting at
** offset 0x80. Bit 7 of register offset is stored in
** bit 7 of the SCRIPTS instruction first DWORD.
**-----------------------------------------------------------
*/
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
#define SCR_SFBR_REG(reg,op,data) \
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_REG_SFBR(reg,op,data) \
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_REG_REG(reg,op,data) \
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_LOAD 0x00000000
#define SCR_SHL 0x01000000
#define SCR_OR 0x02000000
#define SCR_XOR 0x03000000
#define SCR_AND 0x04000000
#define SCR_SHR 0x05000000
#define SCR_ADD 0x06000000
#define SCR_ADDC 0x07000000
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
/*-----------------------------------------------------------
**
** FROM_REG (reg) SFBR = reg
** << 0 >>
**
** TO_REG (reg) reg = SFBR
** << 0 >>
**
** LOAD_REG (reg, data) reg = <data>
** << 0 >>
**
** LOAD_SFBR(data) SFBR = <data>
** << 0 >>
**
**-----------------------------------------------------------
*/
#define SCR_FROM_REG(reg) \
SCR_REG_SFBR(reg,SCR_OR,0)
#define SCR_TO_REG(reg) \
SCR_SFBR_REG(reg,SCR_OR,0)
#define SCR_LOAD_REG(reg,data) \
SCR_REG_REG(reg,SCR_LOAD,data)
#define SCR_LOAD_SFBR(data) \
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
/*-----------------------------------------------------------
**
** LOAD from memory to register.
** STORE from register to memory.
**
** Only supported by 810A, 860, 825A, 875, 895 and 896.
**
**-----------------------------------------------------------
**
** LOAD_ABS (LEN)
** <<start address>>
**
** LOAD_REL (LEN) (DSA relative)
** <<dsa_offset>>
**
**-----------------------------------------------------------
*/
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
#define SCR_NO_FLUSH2 0x02000000
#define SCR_DSA_REL2 0x10000000
#define SCR_LOAD_R(reg, how, n) \
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_STORE_R(reg, how, n) \
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
/*-----------------------------------------------------------
**
** Waiting for Disconnect or Reselect
**
**-----------------------------------------------------------
**
** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
** <<address>>
**
** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
** <<distance>>
**
** CALL [ | IFTRUE/IFFALSE ( ... ) ]
** <<address>>
**
** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
** <<distance>>
**
** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
** <<dummy>>
**
** INT [ | IFTRUE/IFFALSE ( ... ) ]
** <<ident>>
**
** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
** <<ident>>
**
** Conditions:
** WHEN (phase)
** IF (phase)
** CARRYSET
** DATA (data, mask)
**
**-----------------------------------------------------------
*/
#define SCR_NO_OP 0x80000000
#define SCR_JUMP 0x80080000
#define SCR_JUMP64 0x80480000
#define SCR_JUMPR 0x80880000
#define SCR_CALL 0x88080000
#define SCR_CALLR 0x88880000
#define SCR_RETURN 0x90080000
#define SCR_INT 0x98080000
#define SCR_INT_FLY 0x98180000
#define IFFALSE(arg) (0x00080000 | (arg))
#define IFTRUE(arg) (0x00000000 | (arg))
#define WHEN(phase) (0x00030000 | (phase))
#define IF(phase) (0x00020000 | (phase))
#define DATA(D) (0x00040000 | ((D) & 0xff))
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
#define CARRYSET (0x00200000)
#define SIR_COMPLETE 0x10000000
/* script errors */
#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
#define SIR_CMD_OUT_ILL_PH 0x00000002
#define SIR_STATUS_ILL_PH 0x00000003
#define SIR_MSG_RECEIVED 0x00000004
#define SIR_DATA_IN_ERR 0x00000005
#define SIR_DATA_OUT_ERR 0x00000006
#define SIR_SCRIPT_ERROR 0x00000007
#define SIR_MSG_OUT_NO_CMD 0x00000008
#define SIR_MSG_OVER7 0x00000009
/* Fly interrupt */
#define INT_ON_FY 0x00000080
/* Hardware errors are defined in scsi.h */
#define SCSI_IDENTIFY 0xC0
#endif

324
include/synopsys/dwcddr21mctl.h
View file

@ -1,324 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*/
/*
* DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
*/
#ifndef __DWCDDR21MCTL_H
#define __DWCDDR21MCTL_H
#ifndef __ASSEMBLY__
struct dwcddr21mctl {
unsigned int ccr; /* Controller Configuration */
unsigned int dcr; /* DRAM Configuration */
unsigned int iocr; /* I/O Configuration */
unsigned int csr; /* Controller Status */
unsigned int drr; /* DRAM refresh */
unsigned int tpr0; /* SDRAM Timing Parameters 0 */
unsigned int tpr1; /* SDRAM Timing Parameters 1 */
unsigned int tpr2; /* SDRAM Timing Parameters 2 */
unsigned int gdllcr; /* Global DLL Control */
unsigned int dllcr[10]; /* DLL Control */
unsigned int rslr[4]; /* Rank System Lantency */
unsigned int rdgr[4]; /* Rank DQS Gating */
unsigned int dqtr[9]; /* DQ Timing */
unsigned int dqstr; /* DQS Timing */
unsigned int dqsbtr; /* DQS_b Timing */
unsigned int odtcr; /* ODT Configuration */
unsigned int dtr[2]; /* Data Training */
unsigned int dtar; /* Data Training Address */
unsigned int rsved[82]; /* Reserved */
unsigned int mr; /* Mode Register */
unsigned int emr; /* Extended Mode Register */
unsigned int emr2; /* Extended Mode Register 2 */
unsigned int emr3; /* Extended Mode Register 3 */
unsigned int hpcr[32]; /* Host Port Configurarion */
unsigned int pqcr[8]; /* Priority Queue Configuration */
unsigned int mmgcr; /* Memory Manager General Config */
};
#endif /* __ASSEMBLY__ */
/*
* Control Configuration Register
*/
#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
/*
* DRAM Configuration Register
*/
#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
/*
* I/O Configuration Register
*/
#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
/*
* Controller Status Register
*/
#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
/*
* DRAM Refresh Register
*/
#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 0
*/
#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 1
*/
#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 2
*/
#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
/*
* Global DLL Control Register
*/
#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
/*
* DLL Control Register 0-9
*/
#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
/*
* Rank System Lantency Register
*/
#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
/*
* Rank DQS Gating Register
*/
#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
/*
* DQ Timing Register
*/
#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
/*
* DQS Timing Register
*/
#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
/*
* DQS_b (DQSBTR) Timing Register
*/
#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
/*
* ODT Configuration Register
*/
#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
/*
* Data Training Register
*/
#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
/*
* Data Training Address Register
*/
#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
/*
* Mode Register
*/
#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
/*
* Extended Mode register
*/
#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
/*
* Extended Mode register 2
*/
#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
/*
* Extended Mode register 3: [15:0] reserved for JEDEC.
*/
/*
* Host port Configuration register 0-31
*/
#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
/*
* Priority Queue Configuration register 0-7
*/
#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
/*
* Memory Manager General Configuration register
*/
#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
#endif /* __DWCDDR21MCTL_H */

26
include/video_easylogo.h
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@ -1,26 +0,0 @@
/*
** video easylogo
** ==============
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
**
** This utility is still under construction!
*/
#ifndef _EASYLOGO_H_
#define _EASYLOGO_H_
#if 0
#define ENABLE_ASCII_BANNERS
#endif
typedef struct {
unsigned char *data;
int width;
int height;
int bpp;
int pixel_size;
int size;
} fastimage_t ;
#endif /* _EASYLOGO_H_ */