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power: regulator: stpmu1: Introduce stpmu1 driver
Enable support for the regulator functions of the STPMU1X PMIC. The driver implements get/set api for the various BUCKS and LDOs supported by the PMIC device. This driver is controlled by a device tree node which includes voltage limits. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Christophe Kerello
Tom Rini
parent
7c339bbae6
commit
069f0b6354
3 changed files with 677 additions and 0 deletions
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@ -204,3 +204,12 @@ config DM_REGULATOR_TPS65910
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The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all
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regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
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the get/set api for value and enable.
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config DM_REGULATOR_STPMU1
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bool "Enable driver for STPMU1 regulators"
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depends on DM_REGULATOR && PMIC_STPMU1
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---help---
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Enable support for the regulator functions of the STPMU1 PMIC. The
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driver implements get/set api for the various BUCKS and LDOs supported
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by the PMIC device. This driver is controlled by a device tree node
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which includes voltage limits.
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@ -23,3 +23,4 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
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obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMU1) += stpmu1.o
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667
drivers/power/regulator/stpmu1.c
Normal file
667
drivers/power/regulator/stpmu1.c
Normal file
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@ -0,0 +1,667 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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* Author: Christophe Kerello <christophe.kerello@st.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <power/stpmu1.h>
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struct stpmu1_range {
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int min_uv;
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int min_sel;
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int max_sel;
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int step;
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};
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struct stpmu1_output_range {
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const struct stpmu1_range *ranges;
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int nbranges;
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};
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#define STPMU1_MODE(_id, _val, _name) { \
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.id = _id, \
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.register_value = _val, \
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.name = _name, \
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}
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#define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
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.min_uv = _min_uv, \
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.min_sel = _min_sel, \
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.max_sel = _max_sel, \
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.step = _step, \
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}
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#define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \
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.ranges = _ranges, \
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.nbranges = _nbranges, \
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}
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static int stpmu1_output_find_uv(int sel,
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const struct stpmu1_output_range *output_range)
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{
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const struct stpmu1_range *range;
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int i;
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for (i = 0, range = output_range->ranges;
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i < output_range->nbranges; i++, range++) {
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if (sel >= range->min_sel && sel <= range->max_sel)
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return range->min_uv +
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(sel - range->min_sel) * range->step;
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}
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return -EINVAL;
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}
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static int stpmu1_output_find_sel(int uv,
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const struct stpmu1_output_range *output_range)
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{
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const struct stpmu1_range *range;
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int i;
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for (i = 0, range = output_range->ranges;
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i < output_range->nbranges; i++, range++) {
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if (uv == range->min_uv && !range->step)
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return range->min_sel;
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if (uv >= range->min_uv &&
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uv <= range->min_uv +
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(range->max_sel - range->min_sel) * range->step)
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return range->min_sel +
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(uv - range->min_uv) / range->step;
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}
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return -EINVAL;
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}
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/*
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* BUCK regulators
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*/
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static const struct stpmu1_range buck1_ranges[] = {
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STPMU1_RANGE(600000, 0, 30, 25000),
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STPMU1_RANGE(1350000, 31, 63, 0),
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};
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static const struct stpmu1_range buck2_ranges[] = {
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STPMU1_RANGE(1000000, 0, 17, 0),
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STPMU1_RANGE(1050000, 18, 19, 0),
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STPMU1_RANGE(1100000, 20, 21, 0),
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STPMU1_RANGE(1150000, 22, 23, 0),
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STPMU1_RANGE(1200000, 24, 25, 0),
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STPMU1_RANGE(1250000, 26, 27, 0),
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STPMU1_RANGE(1300000, 28, 29, 0),
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STPMU1_RANGE(1350000, 30, 31, 0),
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STPMU1_RANGE(1400000, 32, 33, 0),
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STPMU1_RANGE(1450000, 34, 35, 0),
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STPMU1_RANGE(1500000, 36, 63, 0),
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};
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static const struct stpmu1_range buck3_ranges[] = {
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STPMU1_RANGE(1000000, 0, 19, 0),
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STPMU1_RANGE(1100000, 20, 23, 0),
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STPMU1_RANGE(1200000, 24, 27, 0),
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STPMU1_RANGE(1300000, 28, 31, 0),
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STPMU1_RANGE(1400000, 32, 35, 0),
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STPMU1_RANGE(1500000, 36, 55, 100000),
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STPMU1_RANGE(3400000, 56, 63, 0),
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};
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static const struct stpmu1_range buck4_ranges[] = {
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STPMU1_RANGE(600000, 0, 27, 25000),
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STPMU1_RANGE(1300000, 28, 29, 0),
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STPMU1_RANGE(1350000, 30, 31, 0),
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STPMU1_RANGE(1400000, 32, 33, 0),
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STPMU1_RANGE(1450000, 34, 35, 0),
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STPMU1_RANGE(1500000, 36, 60, 100000),
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STPMU1_RANGE(3900000, 61, 63, 0),
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};
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/* BUCK: 1,2,3,4 - voltage ranges */
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static const struct stpmu1_output_range buck_voltage_range[] = {
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STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
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STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
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STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
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STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
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};
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/* BUCK modes */
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static const struct dm_regulator_mode buck_modes[] = {
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STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"),
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STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"),
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};
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static int stpmu1_buck_get_uv(struct udevice *dev, int buck)
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{
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int sel;
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sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck));
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if (sel < 0)
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return sel;
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sel &= STPMU1_BUCK_OUTPUT_MASK;
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sel >>= STPMU1_BUCK_OUTPUT_SHIFT;
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return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]);
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}
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static int stpmu1_buck_get_value(struct udevice *dev)
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{
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return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1);
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}
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static int stpmu1_buck_set_value(struct udevice *dev, int uv)
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{
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int sel, buck = dev->driver_data - 1;
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sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]);
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if (sel < 0)
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return sel;
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return pmic_clrsetbits(dev->parent,
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STPMU1_BUCKX_CTRL_REG(buck),
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STPMU1_BUCK_OUTPUT_MASK,
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sel << STPMU1_BUCK_OUTPUT_SHIFT);
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}
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static int stpmu1_buck_get_enable(struct udevice *dev)
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{
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
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if (ret < 0)
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return false;
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return ret & STPMU1_BUCK_EN ? true : false;
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}
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static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
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{
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struct dm_regulator_uclass_platdata *uc_pdata;
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int ret, uv;
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/* if regulator is already in the wanted state, nothing to do */
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if (stpmu1_buck_get_enable(dev) == enable)
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return 0;
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if (enable) {
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uc_pdata = dev_get_uclass_platdata(dev);
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uv = stpmu1_buck_get_value(dev);
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if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
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stpmu1_buck_set_value(dev, uc_pdata->min_uV);
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}
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ret = pmic_clrsetbits(dev->parent,
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STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
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STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0);
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if (enable)
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mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
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return ret;
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}
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static int stpmu1_buck_get_mode(struct udevice *dev)
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{
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
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if (ret < 0)
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return ret;
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return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP :
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STPMU1_BUCK_MODE_HP;
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}
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static int stpmu1_buck_set_mode(struct udevice *dev, int mode)
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{
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return pmic_clrsetbits(dev->parent,
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STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
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STPMU1_BUCK_MODE,
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mode ? STPMU1_BUCK_MODE : 0);
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}
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static int stpmu1_buck_probe(struct udevice *dev)
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{
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struct dm_regulator_uclass_platdata *uc_pdata;
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if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK)
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return -EINVAL;
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uc_pdata = dev_get_uclass_platdata(dev);
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uc_pdata->type = REGULATOR_TYPE_BUCK;
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uc_pdata->mode = (struct dm_regulator_mode *)buck_modes;
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uc_pdata->mode_count = ARRAY_SIZE(buck_modes);
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return 0;
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}
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static const struct dm_regulator_ops stpmu1_buck_ops = {
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.get_value = stpmu1_buck_get_value,
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.set_value = stpmu1_buck_set_value,
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.get_enable = stpmu1_buck_get_enable,
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.set_enable = stpmu1_buck_set_enable,
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.get_mode = stpmu1_buck_get_mode,
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.set_mode = stpmu1_buck_set_mode,
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};
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U_BOOT_DRIVER(stpmu1_buck) = {
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.name = "stpmu1_buck",
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.id = UCLASS_REGULATOR,
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.ops = &stpmu1_buck_ops,
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.probe = stpmu1_buck_probe,
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};
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/*
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* LDO regulators
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*/
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static const struct stpmu1_range ldo12_ranges[] = {
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STPMU1_RANGE(1700000, 0, 7, 0),
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STPMU1_RANGE(1700000, 8, 24, 100000),
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STPMU1_RANGE(3300000, 25, 31, 0),
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};
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static const struct stpmu1_range ldo3_ranges[] = {
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STPMU1_RANGE(1700000, 0, 7, 0),
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STPMU1_RANGE(1700000, 8, 24, 100000),
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STPMU1_RANGE(3300000, 25, 30, 0),
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/* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */
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};
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static const struct stpmu1_range ldo5_ranges[] = {
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STPMU1_RANGE(1700000, 0, 7, 0),
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STPMU1_RANGE(1700000, 8, 30, 100000),
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STPMU1_RANGE(3900000, 31, 31, 0),
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};
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static const struct stpmu1_range ldo6_ranges[] = {
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STPMU1_RANGE(900000, 0, 24, 100000),
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STPMU1_RANGE(3300000, 25, 31, 0),
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};
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/* LDO: 1,2,3,4,5,6 - voltage ranges */
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static const struct stpmu1_output_range ldo_voltage_range[] = {
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STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
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STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
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STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
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STPMU1_OUTPUT_RANGE(NULL, 0),
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STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
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STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
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};
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/* LDO modes */
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static const struct dm_regulator_mode ldo_modes[] = {
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STPMU1_MODE(STPMU1_LDO_MODE_NORMAL,
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STPMU1_LDO_MODE_NORMAL, "NORMAL"),
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STPMU1_MODE(STPMU1_LDO_MODE_BYPASS,
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STPMU1_LDO_MODE_BYPASS, "BYPASS"),
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STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE,
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STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
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};
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static int stpmu1_ldo_get_value(struct udevice *dev)
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{
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int sel, ldo = dev->driver_data - 1;
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sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
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if (sel < 0)
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return sel;
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/* ldo4 => 3,3V */
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if (ldo == STPMU1_LDO4)
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return STPMU1_LDO4_UV;
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sel &= STPMU1_LDO12356_OUTPUT_MASK;
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sel >>= STPMU1_LDO12356_OUTPUT_SHIFT;
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/* ldo3, sel = 31 => BUCK2/2 */
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if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL)
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return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
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return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]);
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}
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static int stpmu1_ldo_set_value(struct udevice *dev, int uv)
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{
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int sel, ldo = dev->driver_data - 1;
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/* ldo4 => not possible */
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if (ldo == STPMU1_LDO4)
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return -EINVAL;
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sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]);
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if (sel < 0)
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return sel;
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return pmic_clrsetbits(dev->parent,
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STPMU1_LDOX_CTRL_REG(ldo),
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STPMU1_LDO12356_OUTPUT_MASK,
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sel << STPMU1_LDO12356_OUTPUT_SHIFT);
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}
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static int stpmu1_ldo_get_enable(struct udevice *dev)
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{
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMU1_LDOX_CTRL_REG(dev->driver_data - 1));
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if (ret < 0)
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return false;
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return ret & STPMU1_LDO_EN ? true : false;
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}
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static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
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{
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struct dm_regulator_uclass_platdata *uc_pdata;
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int ret, uv;
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/* if regulator is already in the wanted state, nothing to do */
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if (stpmu1_ldo_get_enable(dev) == enable)
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return 0;
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if (enable) {
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uc_pdata = dev_get_uclass_platdata(dev);
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uv = stpmu1_ldo_get_value(dev);
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if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
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stpmu1_ldo_set_value(dev, uc_pdata->min_uV);
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}
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ret = pmic_clrsetbits(dev->parent,
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STPMU1_LDOX_CTRL_REG(dev->driver_data - 1),
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STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0);
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if (enable)
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mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
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return ret;
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}
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static int stpmu1_ldo_get_mode(struct udevice *dev)
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{
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int ret, ldo = dev->driver_data - 1;
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if (ldo != STPMU1_LDO3)
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return -EINVAL;
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ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
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||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (ret & STPMU1_LDO3_MODE)
|
||||
return STPMU1_LDO_MODE_BYPASS;
|
||||
|
||||
ret &= STPMU1_LDO12356_OUTPUT_MASK;
|
||||
ret >>= STPMU1_LDO12356_OUTPUT_SHIFT;
|
||||
|
||||
return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE :
|
||||
STPMU1_LDO_MODE_NORMAL;
|
||||
}
|
||||
|
||||
static int stpmu1_ldo_set_mode(struct udevice *dev, int mode)
|
||||
{
|
||||
int ret, ldo = dev->driver_data - 1;
|
||||
|
||||
if (ldo != STPMU1_LDO3)
|
||||
return -EINVAL;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
switch (mode) {
|
||||
case STPMU1_LDO_MODE_SINK_SOURCE:
|
||||
ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
|
||||
ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
|
||||
case STPMU1_LDO_MODE_NORMAL:
|
||||
ret &= ~STPMU1_LDO3_MODE;
|
||||
break;
|
||||
case STPMU1_LDO_MODE_BYPASS:
|
||||
ret |= STPMU1_LDO3_MODE;
|
||||
break;
|
||||
}
|
||||
|
||||
return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret);
|
||||
}
|
||||
|
||||
static int stpmu1_ldo_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
|
||||
if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO)
|
||||
return -EINVAL;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_pdata->type = REGULATOR_TYPE_LDO;
|
||||
if (dev->driver_data - 1 == STPMU1_LDO3) {
|
||||
uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes;
|
||||
uc_pdata->mode_count = ARRAY_SIZE(ldo_modes);
|
||||
} else {
|
||||
uc_pdata->mode_count = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_regulator_ops stpmu1_ldo_ops = {
|
||||
.get_value = stpmu1_ldo_get_value,
|
||||
.set_value = stpmu1_ldo_set_value,
|
||||
.get_enable = stpmu1_ldo_get_enable,
|
||||
.set_enable = stpmu1_ldo_set_enable,
|
||||
.get_mode = stpmu1_ldo_get_mode,
|
||||
.set_mode = stpmu1_ldo_set_mode,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stpmu1_ldo) = {
|
||||
.name = "stpmu1_ldo",
|
||||
.id = UCLASS_REGULATOR,
|
||||
.ops = &stpmu1_ldo_ops,
|
||||
.probe = stpmu1_ldo_probe,
|
||||
};
|
||||
|
||||
/*
|
||||
* VREF DDR regulator
|
||||
*/
|
||||
|
||||
static int stpmu1_vref_ddr_get_value(struct udevice *dev)
|
||||
{
|
||||
/* BUCK2/2 */
|
||||
return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
|
||||
}
|
||||
|
||||
static int stpmu1_vref_ddr_get_enable(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG);
|
||||
if (ret < 0)
|
||||
return false;
|
||||
|
||||
return ret & STPMU1_VREF_EN ? true : false;
|
||||
}
|
||||
|
||||
static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* if regulator is already in the wanted state, nothing to do */
|
||||
if (stpmu1_vref_ddr_get_enable(dev) == enable)
|
||||
return 0;
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG,
|
||||
STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0);
|
||||
if (enable)
|
||||
mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stpmu1_vref_ddr_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_pdata->type = REGULATOR_TYPE_FIXED;
|
||||
uc_pdata->mode_count = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_regulator_ops stpmu1_vref_ddr_ops = {
|
||||
.get_value = stpmu1_vref_ddr_get_value,
|
||||
.get_enable = stpmu1_vref_ddr_get_enable,
|
||||
.set_enable = stpmu1_vref_ddr_set_enable,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stpmu1_vref_ddr) = {
|
||||
.name = "stpmu1_vref_ddr",
|
||||
.id = UCLASS_REGULATOR,
|
||||
.ops = &stpmu1_vref_ddr_ops,
|
||||
.probe = stpmu1_vref_ddr_probe,
|
||||
};
|
||||
|
||||
/*
|
||||
* BOOST regulator
|
||||
*/
|
||||
|
||||
static int stpmu1_boost_get_enable(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
|
||||
if (ret < 0)
|
||||
return false;
|
||||
|
||||
return ret & STPMU1_USB_BOOST_EN ? true : false;
|
||||
}
|
||||
|
||||
static int stpmu1_boost_set_enable(struct udevice *dev, bool enable)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!enable && ret & STPMU1_USB_PWR_SW_EN)
|
||||
return -EINVAL;
|
||||
|
||||
/* if regulator is already in the wanted state, nothing to do */
|
||||
if (!!(ret & STPMU1_USB_BOOST_EN) == enable)
|
||||
return 0;
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
|
||||
STPMU1_USB_BOOST_EN,
|
||||
enable ? STPMU1_USB_BOOST_EN : 0);
|
||||
if (enable)
|
||||
mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stpmu1_boost_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_pdata->type = REGULATOR_TYPE_FIXED;
|
||||
uc_pdata->mode_count = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_regulator_ops stpmu1_boost_ops = {
|
||||
.get_enable = stpmu1_boost_get_enable,
|
||||
.set_enable = stpmu1_boost_set_enable,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stpmu1_boost) = {
|
||||
.name = "stpmu1_boost",
|
||||
.id = UCLASS_REGULATOR,
|
||||
.ops = &stpmu1_boost_ops,
|
||||
.probe = stpmu1_boost_probe,
|
||||
};
|
||||
|
||||
/*
|
||||
* USB power switch
|
||||
*/
|
||||
|
||||
static int stpmu1_pwr_sw_get_enable(struct udevice *dev)
|
||||
{
|
||||
uint mask = 1 << dev->driver_data;
|
||||
int ret;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
|
||||
if (ret < 0)
|
||||
return false;
|
||||
|
||||
return ret & mask ? true : false;
|
||||
}
|
||||
|
||||
static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
|
||||
{
|
||||
uint mask = 1 << dev->driver_data;
|
||||
int ret;
|
||||
|
||||
ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* if regulator is already in the wanted state, nothing to do */
|
||||
if (!!(ret & mask) == enable)
|
||||
return 0;
|
||||
|
||||
/* Boost management */
|
||||
if (enable && !(ret & STPMU1_USB_BOOST_EN)) {
|
||||
pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
|
||||
STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN);
|
||||
mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
|
||||
} else if (!enable && ret & STPMU1_USB_BOOST_EN &&
|
||||
(ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) {
|
||||
pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
|
||||
STPMU1_USB_BOOST_EN, 0);
|
||||
}
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
|
||||
mask, enable ? mask : 0);
|
||||
if (enable)
|
||||
mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stpmu1_pwr_sw_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
|
||||
if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW)
|
||||
return -EINVAL;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_pdata->type = REGULATOR_TYPE_FIXED;
|
||||
uc_pdata->mode_count = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_regulator_ops stpmu1_pwr_sw_ops = {
|
||||
.get_enable = stpmu1_pwr_sw_get_enable,
|
||||
.set_enable = stpmu1_pwr_sw_set_enable,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stpmu1_pwr_sw) = {
|
||||
.name = "stpmu1_pwr_sw",
|
||||
.id = UCLASS_REGULATOR,
|
||||
.ops = &stpmu1_pwr_sw_ops,
|
||||
.probe = stpmu1_pwr_sw_probe,
|
||||
};
|
||||
Loading…
Reference in a new issue