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https://github.com/AsahiLinux/u-boot
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arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig
Enable ELBC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
8e63ed518d
commit
068789773d
16 changed files with 20 additions and 16 deletions
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@ -455,6 +455,7 @@ config ARCH_MPC8536
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_MPC8540
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bool
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@ -478,6 +479,7 @@ config ARCH_MPC8544
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_MPC8548
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bool
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@ -524,6 +526,7 @@ config ARCH_MPC8569
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select FSL_ELBC
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config ARCH_MPC8572
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bool
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@ -538,6 +541,7 @@ config ARCH_MPC8572
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1010
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bool
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@ -572,6 +576,7 @@ config ARCH_P1011
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1020
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bool
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@ -585,6 +590,7 @@ config ARCH_P1020
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1021
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bool
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@ -598,6 +604,7 @@ config ARCH_P1021
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1022
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bool
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@ -613,6 +620,7 @@ config ARCH_P1022
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1023
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bool
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@ -624,6 +632,7 @@ config ARCH_P1023
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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config ARCH_P1024
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bool
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@ -637,6 +646,7 @@ config ARCH_P1024
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P1025
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bool
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@ -650,6 +660,7 @@ config ARCH_P1025
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P2020
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bool
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@ -664,6 +675,7 @@ config ARCH_P2020
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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config ARCH_P2041
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bool
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@ -685,6 +697,7 @@ config ARCH_P2041
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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config ARCH_P3041
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bool
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@ -708,6 +721,7 @@ config ARCH_P3041
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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config ARCH_P4080
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bool
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@ -742,6 +756,7 @@ config ARCH_P4080
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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config ARCH_P5020
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bool
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@ -762,6 +777,7 @@ config ARCH_P5020
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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select FSL_ELBC
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config ARCH_P5040
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bool
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@ -782,6 +798,7 @@ config ARCH_P5040
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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select FSL_ELBC
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config ARCH_QEMU_E500
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bool
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@ -1277,6 +1294,9 @@ config SYS_PPC_E500_USE_DEBUG_TLB
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config FSL_IFC
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bool
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config FSL_ELBC
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bool
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config SYS_PPC_E500_DEBUG_TLB
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int "Temporary TLB entry for external debugger"
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depends on SYS_PPC_E500_USE_DEBUG_TLB
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@ -37,7 +37,6 @@
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
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#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
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#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
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@ -10,8 +10,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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@ -28,7 +28,6 @@
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/* High Level Configuration Options */
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#define CONFIG_MP 1 /* support multiple processors */
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#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
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#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
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#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
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@ -96,7 +96,6 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
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@ -25,7 +25,6 @@
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/* High Level Configuration Options */
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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@ -41,7 +41,6 @@
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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@ -14,7 +14,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_FSL_ELBC
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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@ -137,7 +137,6 @@
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_SYS_ELBC_BASE 0xe0000000
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#ifdef CONFIG_PHYS_64BIT
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@ -59,7 +59,6 @@
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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@ -49,7 +49,6 @@
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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@ -35,7 +35,6 @@
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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@ -260,7 +260,6 @@
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#define CONFIG_MP
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#define CONFIG_FSL_ELBC
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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@ -40,7 +40,6 @@
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#define CONFIG_MP
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#define CONFIG_FSL_ELBC
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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@ -29,7 +29,6 @@
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_ELBC 1
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/*
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* Multicore config
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@ -30,7 +30,6 @@
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_ELBC 1
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/*
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* Multicore config
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