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ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices
Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2 changed files with 30 additions and 0 deletions
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@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
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static xilinx_desc fpga;
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/* It can be done differently */
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static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
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static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
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static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
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static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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@ -37,9 +40,18 @@ int board_init(void)
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idcode = zynq_slcr_get_idcode();
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switch (idcode) {
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case XILINX_ZYNQ_7007S:
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fpga = fpga007s;
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break;
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case XILINX_ZYNQ_7010:
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fpga = fpga010;
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break;
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case XILINX_ZYNQ_7012S:
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fpga = fpga012s;
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break;
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case XILINX_ZYNQ_7014S:
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fpga = fpga014s;
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break;
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case XILINX_ZYNQ_7015:
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fpga = fpga015;
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break;
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@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op;
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# define FPGA_ZYNQPL_OPS NULL
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#endif
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#define XILINX_ZYNQ_7007S 0x3
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#define XILINX_ZYNQ_7010 0x2
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#define XILINX_ZYNQ_7012S 0x1c
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#define XILINX_ZYNQ_7014S 0x8
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#define XILINX_ZYNQ_7015 0x1b
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#define XILINX_ZYNQ_7020 0x7
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#define XILINX_ZYNQ_7030 0xc
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@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op;
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#define XILINX_ZYNQ_7100 0x16
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/* Device Image Sizes */
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#define XILINX_XC7Z007S_SIZE 16669920/8
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#define XILINX_XC7Z010_SIZE 16669920/8
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#define XILINX_XC7Z012S_SIZE 28085344/8
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#define XILINX_XC7Z014S_SIZE 32364512/8
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#define XILINX_XC7Z015_SIZE 28085344/8
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#define XILINX_XC7Z020_SIZE 32364512/8
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#define XILINX_XC7Z030_SIZE 47839328/8
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@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op;
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#define XILINX_XC7Z100_SIZE 139330784/8
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/* Descriptor Macros */
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#define XILINX_XC7Z007S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z007s" }
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#define XILINX_XC7Z010_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z010" }
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#define XILINX_XC7Z012S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z012s" }
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#define XILINX_XC7Z014S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z014s" }
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#define XILINX_XC7Z015_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z015" }
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