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Merge branch '2023-11-22-TI-K3-cleanups' into next

Browse source 
This brings in a large number of cleanups and reorganizations to the TI
K3 family of SoCs. We get DTS resyncs for most of the SoCs under that
umbrella as well, and a few enhancements too.
This commit is contained in:
Tom Rini 2023-11-22 14:05:53 -05:00
commit 054222eb68
149 changed files with 13735 additions and 2539 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/dts/Makefile
View file

@ -1400,7 +1400,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
k3-j721e-r5-sk.dtb
k3-j721e-r5-sk.dtb \
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\

12
arch/arm/dts/k3-am62-main.dtsi
View file

@ -81,7 +81,8 @@
};
dmss: bus@48000000 {
compatible = "simple-mfd";
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
@ -90,6 +91,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@ -165,6 +167,7 @@
};
dmsc: system-controller@44043000 {
bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@ -174,16 +177,19 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
@ -202,6 +208,7 @@
};
secure_proxy_sa3: mailbox@43600000 {
bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@ -217,6 +224,7 @@
};
main_pmx0: pinctrl@f4000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
@ -225,12 +233,14 @@
};
main_esm: esm@420000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/dts/k3-am62-mcu.dtsi
View file

@ -7,6 +7,7 @@
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
@ -15,6 +16,7 @@
};
mcu_esm: esm@4100000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;

6
arch/arm/dts/k3-am62-verdin-wifi.dtsi
View file

@ -35,5 +35,11 @@
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
fw-init-baudrate = <3000000>;
};
};

1
arch/arm/dts/k3-am62-verdin.dtsi
View file

@ -1061,6 +1061,7 @@
vddc-supply = <&reg_1v2_dsi>;
vddmipi-supply = <&reg_1v2_dsi>;
vddio-supply = <&reg_1v8_dsi>;
status = "disabled";
dsi_bridge_ports: ports {
#address-cells = <1>;

2
arch/arm/dts/k3-am62-wakeup.dtsi
View file

@ -7,6 +7,7 @@
&cbass_wakeup {
wkup_conf: syscon@43000000 {
bootph-all;
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
@ -14,6 +15,7 @@
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};

3
arch/arm/dts/k3-am62.dtsi
View file

@ -47,6 +47,7 @@
};
cbass_main: bus@f0000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -86,6 +87,7 @@
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
cbass_mcu: bus@4000000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -93,6 +95,7 @@
};
cbass_wakeup: bus@b00000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;

268
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
View file

@ -6,151 +6,49 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-am625-sk-binman.dtsi"
#include "k3-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
/* Keep the LEDs on by default to indicate life */
leds {
bootph-all;
led-0 {
default-state = "on";
bootph-all;
};
led-1 {
default-state = "on";
bootph-all;
};
led-2 {
default-state = "on";
bootph-all;
};
led-3 {
default-state = "on";
bootph-all;
};
led-4 {
default-state = "on";
bootph-all;
};
};
};
&cbass_main {
bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&wkup_conf {
bootph-all;
};
&chipid {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&console_pins_default {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&local_i2c_pins_default {
bootph-all;
};
&gpio0_pins_default {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&sdhci0 {
/* EMMC */
bootph-all;
};
&emmc_pins_default {
bootph-all;
};
&sd_pins_default {
bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@ -163,33 +61,155 @@
>;
};
&tps65219 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
#ifdef CONFIG_TARGET_AM625_A53_EVM
#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
&spl_am625_sk_dtb {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
&am625_sk_dtb {
filename = AM625_BEAGLEPLAY_DTB;
};
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
&spl_am625_sk_dtb_unsigned {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
&am625_sk_dtb_unsigned {
filename = AM625_BEAGLEPLAY_DTB;
};
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-beagleplay";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am625_bp_dtb_unsigned: blob {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am625-beagleplay";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
};
fdt-0 {
description = "k3-am625-beagleplay";
type = "flat_dt";
arch = "arm";
compression = "none";
am625_bp_dtb_unsigned: blob {
filename = AM625_BEAGLEPLAY_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am625-beagleplay";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

34
arch/arm/dts/k3-am625-beagleplay.dts
View file

@ -46,6 +46,7 @@
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@ -58,7 +59,7 @@
ramoops: ramoops@9ca00000 {
compatible = "ramoops";
reg = <0x00 0x9c700000 0x00 0x00100000>;
reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
@ -83,6 +84,7 @@
};
vsys_5v0: regulator-1 {
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
@ -93,6 +95,7 @@
vdd_3v3: regulator-2 {
/* output of TLV62595DMQR-U12 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
@ -118,6 +121,7 @@
vdd_3v3_sd: regulator-4 {
/* output of TPS22918DBVR-U21 */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
@ -132,6 +136,7 @@
};
vdd_sd_dv: regulator-5 {
bootph-all;
compatible = "regulator-gpio";
regulator-name = "sd_hs200_switch";
pinctrl-names = "default";
@ -146,9 +151,11 @@
};
leds {
bootph-all;
compatible = "gpio-leds";
led-0 {
bootph-all;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
@ -156,6 +163,7 @@
};
led-1 {
bootph-all;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
function = LED_FUNCTION_DISK_ACTIVITY;
@ -163,16 +171,19 @@
};
led-2 {
bootph-all;
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
};
led-3 {
bootph-all;
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_LAN;
};
led-4 {
bootph-all;
gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
};
@ -245,6 +256,7 @@
&main_pmx0 {
gpio0_pins_default: gpio0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
@ -264,6 +276,7 @@
};
vdd_sd_dv_pins_default: vdd-sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
@ -283,6 +296,7 @@
};
local_i2c_pins_default: local-i2c-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
@ -321,6 +335,7 @@
};
emmc_pins_default: emmc-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
@ -336,12 +351,14 @@
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@ -418,6 +435,7 @@
};
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
@ -426,6 +444,7 @@
};
console_pins_default: console-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
@ -597,6 +616,7 @@
};
&main_gpio0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
@ -616,6 +636,7 @@
};
&main_gpio1 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_gpio_pins_default>;
gpio-line-names = "", "", "", "", "", /* 0-4 */
@ -633,6 +654,7 @@
};
&main_i2c0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&local_i2c_pins_default>;
clock-frequency = <400000>;
@ -651,6 +673,7 @@
};
tps65219: pmic@30 {
bootph-all;
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
@ -801,6 +824,7 @@
};
&sdhci0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
@ -810,6 +834,7 @@
&sdhci1 {
/* SD/MMC */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
@ -850,6 +875,7 @@
};
&main_uart0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
status = "okay";
@ -870,6 +896,12 @@
pinctrl-names = "default";
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
mcu {
compatible = "ti,cc1352p7";
reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
vdds-supply = <&vdd_3v3>;
};
};
&dss {

48
arch/arm/dts/k3-am625-r5-beagleplay.dts
View file

@ -54,12 +54,7 @@
ti,secure-host;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
@ -73,10 +68,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
@ -84,3 +75,42 @@
&main_bcdma {
ti,sci = <&dm_tifs>;
};
&binman {
tiboot3-am62x-gp-evm.bin {
filename = "tiboot3-am62x-gp-evm.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x43c3a800>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};

21
arch/arm/dts/k3-am625-r5-sk.dts
View file

@ -55,20 +55,11 @@
ti,secure-host;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
&main_esm {
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@ -78,22 +69,14 @@
};
};
&wkup_uart0_pins_default {
bootph-pre-ram;
};
&main_uart1_pins_default {
bootph-pre-ram;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
bootph-pre-ram;
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
bootph-pre-ram;
status = "okay";
};
&ospi0 {

157
arch/arm/dts/k3-am625-sk-binman.dtsi
View file

@ -141,10 +141,7 @@
#ifdef CONFIG_TARGET_AM625_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
@ -155,55 +152,11 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@ -213,23 +166,6 @@
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@ -263,29 +199,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Board";
};
fdt-0 {
@ -323,67 +242,17 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@ -411,26 +280,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Board";
};
fdt-0 {

145
arch/arm/dts/k3-am625-sk-u-boot.dtsi
View file

@ -8,122 +8,12 @@
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
aliases {
mmc1 = &sdhci1;
};
memory@80000000 {
bootph-all;
};
};
&main_conf {
bootph-all;
};
&cbass_main {
bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&wkup_conf {
bootph-all;
};
&chipid {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&fss {
bootph-all;
};
&ospi0_pins_default {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
partitions {
bootph-all;
partition@3fc0000 {
bootph-all;
};
};
};
};
&inta_main_dmss {
bootph-all;
};
&main_bcdma {
@ -153,41 +43,6 @@
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&cpsw3g_phy1 {
bootph-all;
};
&main_rgmii1_pins_default {
bootph-all;
};
&main_rgmii2_pins_default {
bootph-all;
};
&phy_gmii_sel {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
status = "disabled";
};

27
arch/arm/dts/k3-am625-sk.dts
View file

@ -31,6 +31,7 @@
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
@ -41,6 +42,7 @@
vcc_5v0: regulator-1 {
/* Output of LM34936 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
@ -52,6 +54,7 @@
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
@ -63,6 +66,7 @@
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
@ -75,6 +79,7 @@
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
bootph-all;
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
@ -102,6 +107,7 @@
&main_pmx0 {
main_rgmii2_pins_default: main-rgmii2-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
@ -119,6 +125,7 @@
};
ospi0_pins_default: ospi0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
@ -135,20 +142,32 @@
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
&main_gpio0 {
bootph-all;
};
&main_gpio1 {
bootph-all;
};
&main_i2c1 {
bootph-all;
exp1: gpio@22 {
bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
@ -207,12 +226,18 @@
};
};
&fss {
bootph-all;
};
&ospi0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@ -225,6 +250,7 @@
cdns,read-delay = <4>;
partitions {
bootph-all;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@ -260,6 +286,7 @@
};
partition@3fc0000 {
bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};

9
arch/arm/dts/k3-am625-verdin-r5.dts
View file

@ -69,16 +69,7 @@
ti,secure-host;
};
&main_esm {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};

163
arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
View file

@ -5,14 +5,6 @@
#include "k3-binman.dtsi"
&custmpk_pem {
filename = "../../ti/keys/custMpk.pem";
};
&dkey_pem {
filename = "../../ti/keys/ti-degenerate-key.pem";
};
#ifndef CONFIG_ARM64
&bcfg_yaml {
@ -214,10 +206,7 @@
#ifdef CONFIG_TARGET_VERDIN_AM62_A53
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define VERDIN_AM62_DTB "u-boot.dtb"
&binman {
@ -228,54 +217,12 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@ -285,23 +232,6 @@
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@ -333,29 +263,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot fot AM625 Verdin Board";
};
fdt-0 {
@ -392,66 +305,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@ -479,26 +342,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM625 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM625 Verdin Board";
};
fdt-0 {

56
arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
View file

@ -21,25 +21,8 @@
};
};
&cbass_main {
bootph-all;
timer@2400000 {
clock-frequency = <25000000>;
bootph-all;
};
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&chipid {
bootph-all;
&main_timer0 {
clock-frequency = <25000000>;
};
&main_bcdma {
@ -53,6 +36,7 @@
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
@ -98,34 +82,16 @@
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&dmss {
bootph-all;
};
&fss {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
@ -156,10 +122,6 @@
};
};
&main_pmx0 {
bootph-all;
};
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
bootph-all;
@ -170,10 +132,6 @@
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&pinctrl_ctrl_sleep_moci {
bootph-all;
};
@ -210,18 +168,10 @@
status = "disabled";
};
&secure_proxy_main {
bootph-all;
};
&verdin_ctrl_sleep_moci {
bootph-all;
};
&wkup_conf {
bootph-all;
};
/* Verdin UART_2 */
&wkup_uart0 {
bootph-all;

585
arch/arm/dts/k3-am62a-main.dtsi
View file

@ -48,6 +48,18 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
epwm_tbclk: clock-controller@4130 {
compatible = "ti,am62-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
};
dmss: bus@48000000 {
@ -69,6 +81,67 @@
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
inta_main_dmss: interrupt-controller@48000000 {
compatible = "ti,sci-inta";
reg = <0x00 0x48000000 0x00 0x100000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <28>;
ti,interrupt-ranges = <6 70 34>;
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
};
main_bcdma: dma-controller@485c0100 {
compatible = "ti,am64-dmss-bcdma";
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <26>;
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
};
main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <30>;
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
<0x24>, /* CPSW_TX_CHAN */
<0x25>, /* SAUL_TX_0_CHAN */
<0x26>; /* SAUL_TX_1_CHAN */
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
<0x11>, /* RING_CPSW_TX_CHAN */
<0x12>, /* RING_SAUL_TX_0_CHAN */
<0x13>; /* RING_SAUL_TX_1_CHAN */
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
<0x2b>, /* CPSW_RX_CHAN */
<0x2d>, /* SAUL_RX_0_CHAN */
<0x2f>, /* SAUL_RX_1_CHAN */
<0x31>, /* SAUL_RX_2_CHAN */
<0x33>; /* SAUL_RX_3_CHAN */
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
<0x2c>, /* FLOW_CPSW_RX_CHAN */
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
};
};
dmsc: system-controller@44043000 {
@ -77,8 +150,8 @@
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
mboxes = <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
@ -96,6 +169,21 @@
};
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@ -104,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 36 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 36 2>;
assigned-clock-parents = <&k3_clks 36 3>;
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 37 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 37 2>;
assigned-clock-parents = <&k3_clks 37 3>;
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 38 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 38 2>;
assigned-clock-parents = <&k3_clks 38 3>;
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 39 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 39 2>;
assigned-clock-parents = <&k3_clks 39 3>;
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 40 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 40 2>;
assigned-clock-parents = <&k3_clks 40 3>;
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 41 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 41 2>;
assigned-clock-parents = <&k3_clks 41 3>;
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 42 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 42 2>;
assigned-clock-parents = <&k3_clks 42 3>;
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 43 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 43 2>;
assigned-clock-parents = <&k3_clks 43 3>;
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@ -222,6 +406,39 @@
status = "disabled";
};
main_spi0: spi@20100000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x20100000 0x00 0x400>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 0>;
status = "disabled";
};
main_spi1: spi@20110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20110000 0x00 0x400>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 142 0>;
status = "disabled";
};
main_spi2: spi@20120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20120000 0x00 0x400>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 143 0>;
status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
@ -295,4 +512,368 @@
no-1-8-v;
status = "disabled";
};
usbss0: dwc3-usb@f900000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f900000 0x00 0x800>;
clocks = <&k3_clks 161 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
ranges;
status = "disabled";
usb0: usb@31000000 {
compatible = "snps,dwc3";
reg = <0x00 0x31000000 0x00 0x50000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
usbss1: dwc3-usb@f910000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f910000 0x00 0x800>;
clocks = <&k3_clks 162 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
ranges;
status = "disabled";
usb1: usb@31100000 {
compatible = "snps,dwc3";
reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
ospi0: spi@fc40000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 75 7>;
assigned-clocks = <&k3_clks 75 7>;
assigned-clock-parents = <&k3_clks 75 8>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x8000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
clocks = <&k3_clks 13 0>;
assigned-clocks = <&k3_clks 13 3>;
assigned-clock-parents = <&k3_clks 13 11>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
dmas = <&main_pktdma 0xc600 15>,
<&main_pktdma 0xc601 15>,
<&main_pktdma 0xc602 15>,
<&main_pktdma 0xc603 15>,
<&main_pktdma 0xc604 15>,
<&main_pktdma 0xc605 15>,
<&main_pktdma 0xc606 15>,
<&main_pktdma 0xc607 15>,
<&main_pktdma 0x4600 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&wkup_conf 0x200>;
};
cpsw_port2: port@2 {
reg = <2>;
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
};
};
cpsw3g_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 13 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@29000000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29000000 0x00 0x200>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster1: mailbox@29010000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29010000 0x00 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster2: mailbox@29020000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29020000 0x00 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster3: mailbox@29030000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29030000 0x00 0x200>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_mcan0: can@20701000 {
compatible = "bosch,m_can";
reg = <0x00 0x20701000 0x00 0x200>,
<0x00 0x20708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_rti0: watchdog@e000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e000000 0x00 0x100>;
clocks = <&k3_clks 125 0>;
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 125 0>;
assigned-clock-parents = <&k3_clks 125 2>;
};
main_rti1: watchdog@e010000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e010000 0x00 0x100>;
clocks = <&k3_clks 126 0>;
power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 126 0>;
assigned-clock-parents = <&k3_clks 126 2>;
};
main_rti2: watchdog@e020000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e020000 0x00 0x100>;
clocks = <&k3_clks 127 0>;
power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 127 0>;
assigned-clock-parents = <&k3_clks 127 2>;
};
main_rti3: watchdog@e030000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e030000 0x00 0x100>;
clocks = <&k3_clks 128 0>;
power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 128 0>;
assigned-clock-parents = <&k3_clks 128 2>;
};
main_rti4: watchdog@e040000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e040000 0x00 0x100>;
clocks = <&k3_clks 205 0>;
power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 205 0>;
assigned-clock-parents = <&k3_clks 205 2>;
};
epwm0: pwm@23000000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23000000 0x00 0x100>;
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
epwm1: pwm@23010000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23010000 0x00 0x100>;
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
epwm2: pwm@23020000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x23020000 0x00 0x100>;
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ecap0: pwm@23100000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23100000 0x00 0x100>;
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>;
clock-names = "fck";
status = "disabled";
};
ecap1: pwm@23110000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23110000 0x00 0x100>;
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>;
clock-names = "fck";
status = "disabled";
};
ecap2: pwm@23120000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23120000 0x00 0x100>;
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>;
clock-names = "fck";
status = "disabled";
};
mcasp0: audio-controller@2b00000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b00000 0x00 0x2000>,
<0x00 0x02b08000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 190 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 190 0>;
assigned-clock-parents = <&k3_clks 190 2>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp1: audio-controller@2b10000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b10000 0x00 0x2000>,
<0x00 0x02b18000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 191 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 191 0>;
assigned-clock-parents = <&k3_clks 191 2>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
mcasp2: audio-controller@2b20000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x00 0x02b20000 0x00 0x2000>,
<0x00 0x02b28000 0x00 0x400>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
dma-names = "tx", "rx";
clocks = <&k3_clks 192 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 192 0>;
assigned-clock-parents = <&k3_clks 192 2>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};

131
arch/arm/dts/k3-am62a-mcu.dtsi
View file

@ -15,6 +15,51 @@
status = "disabled";
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 2>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 2>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 2>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 2>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@ -36,4 +81,90 @@
clock-names = "fck";
status = "disabled";
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
status = "disabled";
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x04201000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <24>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
status = "disabled";
};
mcu_rti0: watchdog@4880000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x04880000 0x00 0x100>;
clocks = <&k3_clks 131 0>;
power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 131 0>;
assigned-clock-parents = <&k3_clks 131 2>;
/* Tightly coupled to M4F */
status = "reserved";
};
mcu_mcan0: can@4e08000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e08000 0x00 0x200>,
<0x00 0x4e00000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
mcu_mcan1: can@4e18000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e18000 0x00 0x200>,
<0x00 0x4e10000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
};

158
arch/arm/dts/k3-am62a-sk-binman.dtsi
View file

@ -144,10 +144,7 @@
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
@ -158,55 +155,11 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@ -216,23 +169,6 @@
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@ -266,29 +202,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM62Ax board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM62Ax Board";
};
fdt-0 {
@ -326,67 +245,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@ -414,26 +282,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM62Ax board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM62Ax Board";
};
fdt-0 {

47
arch/arm/dts/k3-am62a-thermal.dtsi Normal file
View file

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main2_thermal: main2-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
main2_crit: main2-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

21
arch/arm/dts/k3-am62a-wakeup.dtsi
View file

@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x02b200000 0x00 0x100>;
reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
wkup_rti0: watchdog@2b000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2b000000 0x00 0x100>;
clocks = <&k3_clks 132 0>;
power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 132 0>;
assigned-clock-parents = <&k3_clks 132 2>;
/* Used by DM firmware */
status = "reserved";
};
wkup_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

5
arch/arm/dts/k3-am62a.dtsi
View file

@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
@ -114,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
#include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

74
arch/arm/dts/k3-am62a7-r5-sk.dts
View file

@ -7,7 +7,6 @@
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
@ -15,33 +14,6 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
a53_0: a53@0 {
@ -81,67 +53,39 @@
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-pre-ram;
};
&secure_proxy_sa3 {
/* Needed for initial handshake with ROM */
status = "okay";
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&mcu_pmx0 {
status = "okay";
&wkup_uart0_pins_default {
bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
bootph-pre-ram;
};
};
&main_pmx0 {
&main_uart1_pins_default {
bootph-pre-ram;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
bootph-pre-ram;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};

139
arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
View file

@ -4,137 +4,186 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62a-sk-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-pre-ram;
bootph-all;
};
};
&cbass_main{
bootph-pre-ram;
&main_timer0 {
bootph-all;
};
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
bootph-pre-ram;
};
&cbass_main {
bootph-all;
};
&dmss {
bootph-pre-ram;
bootph-all;
};
&secure_proxy_main {
bootph-pre-ram;
bootph-all;
};
&dmsc {
bootph-pre-ram;
bootph-all;
};
&k3_pds {
bootph-pre-ram;
bootph-all;
};
&k3_clks {
bootph-pre-ram;
bootph-all;
};
&k3_reset {
bootph-pre-ram;
bootph-all;
};
&wkup_conf {
bootph-pre-ram;
bootph-all;
};
&chipid {
bootph-pre-ram;
bootph-all;
};
&main_pmx0 {
bootph-pre-ram;
bootph-all;
};
&main_uart0 {
bootph-pre-ram;
bootph-all;
};
&main_uart0_pins_default {
bootph-pre-ram;
};
&main_uart1 {
bootph-pre-ram;
bootph-all;
};
&cbass_mcu {
bootph-pre-ram;
bootph-all;
};
&cbass_wakeup {
bootph-pre-ram;
bootph-all;
};
&mcu_pmx0 {
bootph-pre-ram;
};
&wkup_uart0 {
bootph-pre-ram;
bootph-all;
};
&main_gpio0 {
bootph-pre-ram;
bootph-all;
};
&main_i2c0 {
bootph-pre-ram;
bootph-all;
};
&main_i2c0_pins_default {
bootph-pre-ram;
bootph-all;
};
&main_i2c1 {
bootph-pre-ram;
bootph-all;
};
&main_i2c1_pins_default {
bootph-pre-ram;
bootph-all;
};
&exp1 {
bootph-pre-ram;
bootph-all;
};
&sdhci1 {
bootph-pre-ram;
bootph-all;
};
&main_mmc1_pins_default {
bootph-pre-ram;
bootph-all;
};
&k3_reset {
bootph-pre-ram;
bootph-all;
};
&dmsc {
bootph-pre-ram;
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
bootph-all;
};
};
&vdd_mmc1 {
bootph-pre-ram;
bootph-all;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x20000>,
<0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
bootph-all;
};
&main_mdio1_pins_default {
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&main_rgmii1_pins_default {
bootph-all;
};
&phy_gmii_sel {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&cpsw_port1 {
bootph-all;
};

347
arch/arm/dts/k3-am62a7-sk.dts
View file

@ -9,15 +9,17 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
#include "k3-am62a-sk-binman.dtsi"
/ {
compatible = "ti,am62a7-sk", "ti,am62a7";
compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@ -77,10 +79,10 @@
regulator-boot-on;
};
vcc_3v3_sys: regulator-2 {
vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
@ -99,6 +101,17 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
vcc_3v3_sys: regulator-4 {
/* output of TPS222965DSGT */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_main>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -112,38 +125,100 @@
default-state = "off";
};
};
tlv320_mclk: clk-0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12288000>;
};
codec_audio: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62Ax-SKEVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In",
"Microphone", "Microphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In",
"MIC3R", "Microphone Jack",
"Microphone Jack", "Mic Bias";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&tlv320_mclk>;
};
};
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
>;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "reserved";
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@ -155,11 +230,64 @@
>;
};
usr_led_pins_default: usr-led-pins-default {
usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
main_mdio1_pins_default: main-mdio1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
>;
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
>;
};
main_mcasp1_pins_default: main-mcasp1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
};
&mcu_pmx0 {
status = "okay";
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
>;
};
};
&mcu_gpio0 {
status = "okay";
};
&main_i2c0 {
@ -167,13 +295,112 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
typec_pd0: usb-power-controller@3f {
compatible = "ti,tps6598x";
reg = <0x3f>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
self-powered;
data-role = "dual";
power-role = "sink";
port {
usb_con_hs: endpoint {
remote-endpoint = <&usb0_hs_ep>;
};
};
};
};
tps659312: pmic@48 {
compatible = "ti,tps6593-q1";
reg = <0x48>;
ti,primary-pmic;
system-power-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&mcu_gpio0>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
buck123-supply = <&vcc_3v3_sys>;
buck4-supply = <&vcc_3v3_sys>;
buck5-supply = <&vcc_3v3_sys>;
ldo1-supply = <&vcc_3v3_sys>;
ldo2-supply = <&vcc_3v3_sys>;
ldo3-supply = <&buck5>;
ldo4-supply = <&vcc_3v3_sys>;
regulators {
buck123: buck123 {
regulator-name = "vcc_core";
regulator-min-microvolt = <715000>;
regulator-max-microvolt = <895000>;
regulator-boot-on;
regulator-always-on;
};
buck4: buck4 {
regulator-name = "vcc_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
buck5: buck5 {
regulator-name = "vcc_1v8_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: ldo1 {
regulator-name = "vddshv5_sdio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: ldo2 {
regulator-name = "vpp_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: ldo3 {
regulator-name = "vcc_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: ldo4 {
regulator-name = "vdda_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
@ -194,6 +421,19 @@
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
ai3x-micbias-vg = <1>; /* 2.0V */
/* Regulators */
AVDD-supply = <&vcc_3v3_sys>;
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
};
&sdhci1 {
@ -223,3 +463,84 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "reserved";
};
&usbss0 {
status = "okay";
ti,vbus-divider;
};
&usb0 {
usb-role-switch;
port {
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
};
};
&usbss1 {
status = "okay";
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&main_usb1_pins_default>;
};
&cpsw3g {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
status = "disabled";
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&mcasp1 {
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&main_mcasp1_pins_default>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 0 2 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

3
arch/arm/dts/k3-am62a7.dtsi
View file

@ -95,8 +95,9 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};

109
arch/arm/dts/k3-am62x-sk-common.dtsi
View file

@ -28,6 +28,7 @@
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@ -114,11 +115,23 @@
clocks = <&tlv320_mclk>;
};
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
};
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
@ -126,6 +139,7 @@
};
main_uart1_pins_default: main-uart1-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
@ -156,6 +170,7 @@
};
main_mmc0_pins_default: main-mmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
@ -171,6 +186,7 @@
};
main_mmc1_pins_default: main-mmc1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
@ -196,6 +212,7 @@
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
@ -226,10 +243,44 @@
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
main_dss0_pins_default: main-dss0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
>;
};
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
@ -241,12 +292,14 @@
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
@ -254,6 +307,7 @@
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
@ -300,7 +354,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
@ -313,9 +367,40 @@
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
};
sii9022: bridge-hdmi@3b {
compatible = "sil,sii9022";
reg = <0x3b>;
interrupt-parent = <&exp1>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 >;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&sdhci0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
@ -325,6 +410,7 @@
&sdhci1 {
/* SD/MMC */
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
@ -333,21 +419,25 @@
};
&cpsw3g {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw3g_mdio {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
bootph-all;
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@ -410,3 +500,20 @@
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_dss0_pins_default>;
};
&dss_ports {
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};

151
arch/arm/dts/k3-am64x-binman.dtsi
View file

@ -118,87 +118,27 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
&binman {
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am642-evm";
@ -254,29 +194,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM64 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM64 Board";
};
fdt-0 {
@ -340,65 +263,17 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-am642-evm";
type = "flat_dt";
@ -443,26 +318,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM64 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM64 Board";
};
fdt-0 {

273
arch/arm/dts/k3-am65x-binman.dtsi
View file

@ -42,77 +42,7 @@
};
itb {
filename = "sysfw-am65x_sr2-hs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";\
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_template>;
};
};
@ -149,55 +79,14 @@
itb_gp {
filename = "sysfw-am65x_sr2-gp-evm.itb";
symlink = "sysfw.itb";
insert-template = <&itb_unsigned_template>;
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
@ -206,86 +95,22 @@
#ifdef CONFIG_TARGET_AM654_A53_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM654_EVM_DTB "u-boot.dtb"
&binman {
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-am654-base-board";
type = "flat_dt";
@ -317,29 +142,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM65 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for AM65 Board";
};
fdt-0 {
@ -378,67 +186,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -466,26 +223,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for AM65 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for AM65 Board";
};
fdt-0 {

56
arch/arm/dts/k3-am68-sk-base-board.dts
View file

@ -553,3 +553,59 @@
};
};
};
&serdes_ln_ctrl {
idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
<J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
};
&serdes_refclk {
clock-frequency = <100000000>;
};
&serdes0 {
status = "okay";
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
serdes0_usb_link: phy@2 {
status = "okay";
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 3>;
};
};
&pcie1_rc {
status = "okay";
reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&usb_serdes_mux {
idle-states = <0>; /* USB0 to SERDES lane 2 */
};
&usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
};
&usb0 {
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};

208
arch/arm/dts/k3-am68-sk-som.dtsi
View file

@ -25,6 +25,108 @@
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a8000000 {
reg = <0x00 0xa8000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
};
@ -49,3 +151,109 @@
reg = <0x51>;
};
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};

359
arch/arm/dts/k3-binman.dtsi
View file

@ -13,14 +13,14 @@
custMpk {
filename = "custMpk.pem";
custmpk_pem: blob-ext {
filename = "../keys/custMpk.pem";
filename = "arch/arm/mach-k3/keys/custMpk.pem";
};
};
ti-degenerate-key {
filename = "ti-degenerate-key.pem";
dkey_pem: blob-ext {
filename = "../keys/ti-degenerate-key.pem";
filename = "arch/arm/mach-k3/keys/ti-degenerate-key.pem";
};
};
};
@ -32,28 +32,28 @@
filename = "board-cfg.bin";
bcfg_yaml: ti-board-config {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
pm-cfg {
filename = "pm-cfg.bin";
pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
sec-cfg {
filename = "sec-cfg.bin";
scfg_yaml: ti-board-config {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
combined-tifs-cfg {
@ -61,19 +61,19 @@
ti-board-config {
bcfg_yaml_tifs: board-cfg {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
scfg_yaml_tifs: sec-cfg {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
pcfg_yaml_tifs: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_tifs: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
};
@ -82,11 +82,11 @@
ti-board-config {
pcfg_yaml_dm: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_dm: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
};
@ -95,22 +95,349 @@
ti-board-config {
bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
schema = "board/ti/common/schema.yaml";
};
};
};
};
&binman {
itb_template: template-5 {
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
};
itb_unsigned_template: template-6 {
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_fs";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
};
};
#else
&binman {
ti_spl_template: template-1 {
filename = "tispl.bin";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
};
};
};
ti_spl_unsigned_template: template-2 {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
};
};
};
u_boot_template: template-3 {
filename = "u-boot.img";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
};
};
};
};
u_boot_unsigned_template: template-4 {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = "u-boot-nodtb.bin";
};
hash {
algo = "crc32";
};
};
};
};
};
};
#endif

159
arch/arm/dts/k3-j7200-binman.dtsi
View file

@ -180,10 +180,7 @@
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
@ -194,82 +191,20 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@ -302,29 +237,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J7200 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J7200 Board";
};
fdt-0 {
@ -362,67 +280,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = SPL_NODTB;
};
};
fdt-1 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@ -450,26 +317,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J7200 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J7200 Board";
};
fdt-1 {

2
arch/arm/dts/k3-j7200-main.dtsi
View file

@ -91,7 +91,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;

9
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
View file

@ -318,7 +318,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -637,4 +637,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
};

358
arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi Normal file
View file

@ -0,0 +1,358 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-binman.dtsi"
/ {
memory@80000000 {
bootph-all;
};
/* Keep the LEDs on by default to indicate life */
leds {
bootph-all;
led-0 {
default-state = "on";
bootph-all;
};
led-1 {
default-state = "on";
bootph-all;
};
led-2 {
default-state = "on";
bootph-all;
};
led-3 {
default-state = "on";
bootph-all;
};
led-4 {
default-state = "on";
bootph-all;
};
};
};
&cbass_main {
bootph-all;
};
&main_navss {
bootph-all;
};
&cbass_mcu_wakeup {
bootph-all;
chipid@43000014 {
bootph-all;
};
};
&mcu_navss {
bootph-all;
};
&mcu_ringacc {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
bootph-all;
};
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&wkup_pmx0 {
bootph-all;
};
&main_pmx0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_sdhci0 {
bootph-all;
};
&main_sdhci1 {
bootph-all;
sdhci-caps-mask = <0x00000007 0x00000000>;
/delete-property/ cd-gpios;
/delete-property/ cd-debounce-delay-ms;
/delete-property/ ti,fails-without-test-cd;
/delete-property/ no-1-8-v;
};
&main_mmc1_pins_default {
bootph-all;
};
&mcu_cpsw {
bootph-all;
};
&davinci_mdio {
bootph-all;
};
&phy0 {
bootph-all;
};
&serdes2 {
bootph-all;
};
&serdes_ln_ctrl {
bootph-all;
};
&serdes2_usb_link {
bootph-all;
};
&usb_serdes_mux {
bootph-all;
};
&serdes_wiz2 {
bootph-all;
};
&main_usbss1_pins_default {
bootph-all;
};
&mcu_usbss1_pins_default {
bootph-all;
};
&usbss1 {
bootph-all;
};
&usb1 {
bootph-all;
};
&wkup_i2c0_pins_default {
bootph-all;
};
&wkup_i2c0 {
bootph-all;
};
#ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-beagleboneai64";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_J721E_BBAI64_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j721e-beagleboneai64";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
};
fdt-0 {
description = "k3-j721e-beagleboneai64";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = J721E_BBAI64_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j721e-beagleboneai64";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

993
arch/arm/dts/k3-j721e-beagleboneai64.dts Normal file
View file

@ -0,0 +1,993 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
#include "k3-j721e.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
/ {
compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
model = "BeagleBoard.org BeagleBone AI-64";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &wkup_i2c0;
i2c1 = &main_i2c6;
i2c2 = &main_i2c2;
i2c3 = &main_i2c4;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c66_0_memory_region: c66-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c66_1_memory_region: c66-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a8100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@aa000000 {
reg = <0x00 0xaa000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&sw_pwr_pins_default>;
button-1 {
label = "BOOT";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
};
button-2 {
label = "POWER";
linux,code = <KEY_POWER>;
gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_default>;
led-0 {
gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
led-1 {
gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_DISK_ACTIVITY;
linux,default-trigger = "mmc0";
};
led-2 {
gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
linux,default-trigger = "cpu";
};
led-3 {
gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_DISK_ACTIVITY;
linux,default-trigger = "mmc1";
};
led-4 {
gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
default-state = "off";
};
};
evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: regulator-1 {
/* Output of LMS140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: regulator-2 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&sd_pwr_en_pins_default>;
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv_alt: regulator-4 {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
regulator-name = "tlv71033";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
dp_pwr_3v3: regulator-5 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&dp0_3v3_en_pins_default>;
regulator-name = "dp-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
enable-active-high;
};
dp0: connector {
compatible = "dp-connector";
label = "DP0";
type = "full-size";
dp-pwr-supply = <&dp_pwr_3v3>;
port {
dp_connector_in: endpoint {
remote-endpoint = <&dp0_out>;
};
};
};
};
&main_pmx0 {
led_pins_default: led-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
sd_pwr_en_pins_default: sd-pwr-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
>;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
>;
};
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
>;
};
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
>;
};
dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
>;
};
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
>;
};
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
main_i2c4_pins_default: main-i2c4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
>;
};
main_i2c5_pins_default: main-i2c5-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
>;
};
main_i2c6_pins_default: main-i2c6-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
>;
};
csi0_gpio_pins_default: csi0-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
>;
};
csi1_gpio_pins_default: csi1-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
>;
};
pcie1_rst_pins_default: pcie1-rst-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
>;
};
};
&wkup_pmx0 {
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
>;
};
mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
>;
};
mcu_adc1_pins_default: mcu-adc1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
>;
};
mikro_bus_pins_default: mikro-bus-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
>;
};
sw_pwr_pins_default: sw-pwr-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_usbss1_pins_default: mcu-usbss1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by TIFS firmware. */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD Card */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
/* BBB Header: P9.19 and P9.20 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <100000>;
};
&main_i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
};
&main_i2c4 {
/* BBB Header: P9.24 and P9.26 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c4_pins_default>;
clock-frequency = <100000>;
};
&main_i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c5_pins_default>;
clock-frequency = <400000>;
};
&main_i2c6 {
/* BBB Header: P9.17 and P9.18 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c6_pins_default>;
clock-frequency = <100000>;
status = "okay";
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
};
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
<&mikro_bus_pins_default>;
};
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
};
&main_gpio1 {
status = "okay";
};
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};
&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
&serdes_wiz3 {
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
};
&serdes3 {
serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
};
};
&serdes4 {
torrent_phy_dp: phy@0 {
reg = <0>;
resets = <&serdes_wiz4 1>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <4>;
cdns,max-bit-rate = <5400>;
#phy-cells = <0>;
};
};
&mhdp {
phys = <&torrent_phy_dp>;
phy-names = "dpphy";
pinctrl-names = "default";
pinctrl-0 = <&dp0_pins_default>;
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
};
&usb0 {
dr_mode = "peripheral";
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&serdes2 {
serdes2_usb_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz2 2>;
};
};
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
ti,vbus-divider;
};
&usb1 {
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes2_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&tscadc0 {
status = "okay";
/* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
};
};
&tscadc1 {
status = "okay";
/* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
adc {
ti,adc-channels = <0>;
};
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mdio_pins_default>;
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};
&dss {
/*
* These clock assignments are chosen to enable the following outputs:
*
* VP0 - DisplayPort SST
* VP1 - DPI0
* VP2 - DSI
* VP3 - DPI1
*/
assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
<&k3_clks 152 4>, /* VP 2 pixel clock */
<&k3_clks 152 9>, /* VP 3 pixel clock */
<&k3_clks 152 13>; /* VP 4 pixel clock */
assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
<&k3_clks 152 6>, /* PLL19_HSDIV0 */
<&k3_clks 152 11>, /* PLL18_HSDIV0 */
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
};
&dss_ports {
port {
dpi0_out: endpoint {
remote-endpoint = <&dp0_in>;
};
};
};
&dp0_ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
port@4 {
reg = <4>;
dp0_out: endpoint {
remote-endpoint = <&dp_connector_in>;
};
};
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&serdes1 {
serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
};
};
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins_default>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
max-link-speed = <3>;
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
&ufs_wrapper {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster3 {
status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c66_1: mbox-c66-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};

332
arch/arm/dts/k3-j721e-binman.dtsi
View file

@ -42,78 +42,7 @@
};
itb {
filename = "sysfw-j721e_sr1_1-hs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&board_cfg>;
keyfile = "custMpk.pem";
};
board_cfg: board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&pm_cfg>;
keyfile = "custMpk.pem";
};
pm_cfg: pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&rm_cfg>;
keyfile = "custMpk.pem";
};
rm_cfg: rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
ti-secure {
content = <&sec_cfg>;
keyfile = "custMpk.pem";
};
sec_cfg: sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_template>;
};
};
@ -145,62 +74,7 @@
};
itb_fs {
filename = "sysfw-j721e_sr2-hs-fs-evm.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_fs";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
board-cfg {
filename = "board-cfg.bin";
type = "blob-ext";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
pm-cfg {
filename = "pm-cfg.bin";
type = "blob-ext";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
rm-cfg {
filename = "rm-cfg.bin";
type = "blob-ext";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
sec-cfg {
filename = "sec-cfg.bin";
type = "blob-ext";
};
};
};
};
insert-template = <&itb_unsigned_template>;
};
};
@ -237,55 +111,15 @@
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
insert-template = <&itb_unsigned_template>;
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
@ -294,11 +128,9 @@
#ifdef CONFIG_TARGET_J721E_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_EVM_DTB "u-boot.dtb"
#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
@ -310,55 +142,11 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@ -368,24 +156,6 @@
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -439,29 +209,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J721E Board";
};
fdt-0 {
@ -524,67 +277,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@ -629,26 +331,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for j721e board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J721E Board";
};
fdt-0 {

2200
arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

2
arch/arm/dts/k3-j721e-main.dtsi
View file

@ -181,7 +181,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;

9
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
View file

@ -440,7 +440,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -671,4 +671,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
};

185
arch/arm/dts/k3-j721e-r5-beagleboneai64.dts Normal file
View file

@ -0,0 +1,185 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-j721e-beagleboneai64.dts"
#include "k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi"
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-beagleboneai64-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
chosen {
tick-timer = &mcu_timer0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_mcu 21>,
<&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_mcu 6>,
<&secure_proxy_mcu 8>,
<&secure_proxy_mcu 5>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&mcu_timer0 {
status = "okay";
bootph-pre-ram;
};
&secure_proxy_mcu {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
&wkup_uart0_pins_default {
bootph-pre-ram;
};
&wkup_i2c0 {
bootph-pre-ram;
};
&binman {
tiboot3-j721e-gp-evm.bin {
filename = "tiboot3-j721e-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>;
core = "public";
load = <CONFIG_SPL_TEXT_BASE>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
};
sysfw_gp {
filename = "sysfw.bin_gp";
ti-secure-rom {
content = <&ti_fs>;
core = "secure";
load = <0x40000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
};
ti_fs: ti-fs.bin {
filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin";
type = "blob-ext";
optional;
};
};
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
fit {
description = "SYSFW and Config fragments";
#address-cells = <1>;
images {
sysfw.bin {
description = "sysfw";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
board-cfg.bin {
description = "board-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "board-cfg.bin";
};
};
pm-cfg.bin {
description = "pm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "pm-cfg.bin";
};
};
rm-cfg.bin {
description = "rm-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "rm-cfg.bin";
};
};
sec-cfg.bin {
description = "sec-cfg";
type = "firmware";
arch = "arm";
compression = "none";
blob-ext {
filename = "sec-cfg.bin";
};
};
};
};
};
};

157
arch/arm/dts/k3-j721s2-binman.dtsi
View file

@ -141,11 +141,9 @@
#ifdef CONFIG_TARGET_J721S2_A72_EVM
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721S2_EVM_DTB "u-boot.dtb"
#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
@ -157,55 +155,11 @@
};
};
ti-spl {
filename = "tispl.bin";
pad-byte = <0xff>;
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
content = <&atf>;
keyfile = "custMpk.pem";
};
atf: atf-bl31 {
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@ -215,23 +169,6 @@
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
ti-secure {
content = <&u_boot_spl_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_spl_nodtb: blob-ext {
filename = SPL_NODTB;
};
};
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@ -285,29 +222,12 @@
&binman {
u-boot {
filename = "u-boot.img";
pad-byte = <0xff>;
insert-template = <&u_boot_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J721S2 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
ti-secure {
content = <&u_boot_nodtb>;
keyfile = "custMpk.pem";
};
u_boot_nodtb: u-boot-nodtb {
};
hash {
algo = "crc32";
};
description = "U-Boot for J721S2 Board";
};
fdt-0 {
@ -371,67 +291,16 @@
&binman {
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
insert-template = <&ti_spl_unsigned_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf-bl31 {
filename = "bl31.bin";
};
};
tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee-os {
filename = "tee-raw.bin";
};
};
dm {
description = "DM binary";
type = "firmware";
arch = "arm32";
compression = "none";
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
spl {
description = "SPL (64-bit)";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
blob {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@ -475,26 +344,12 @@
&binman {
u-boot_unsigned {
filename = "u-boot.img_unsigned";
pad-byte = <0xff>;
insert-template = <&u_boot_unsigned_template>;
fit {
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot for J721S2 board";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
blob {
filename = UBOOT_NODTB;
};
hash {
algo = "crc32";
};
description = "U-Boot for J721S2 Board";
};
fdt-0 {

232
arch/arm/dts/k3-j721s2-main.dtsi
View file

@ -775,7 +775,7 @@
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@ -807,6 +807,7 @@
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
@ -1103,6 +1104,22 @@
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
main_bcdma_csi: dma-controller@311a0000 {
compatible = "ti,j721s2-dmss-bcdma-csi";
reg = <0x00 0x311a0000 0x00 0x100>,
<0x00 0x35d00000 0x00 0x20000>,
<0x00 0x35c00000 0x00 0x10000>,
<0x00 0x35e00000 0x00 0x80000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <3>;
ti,sci = <&sms>;
ti,sci-dev-id = <225>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
status = "disabled";
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
@ -1695,4 +1712,217 @@
dss_ports: ports {
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <279>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 279 1>;
firmware-name = "j721s2-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5d00000 0x00010000>,
<0x5d10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <280>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 280 1>;
firmware-name = "j721s2-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
<0x5f00000 0x00 0x5f00000 0x20000>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@5e00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5e00000 0x00010000>,
<0x5e10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <281>;
ti,sci-proc-ids = <0x08 0xff>;
resets = <&k3_reset 281 1>;
firmware-name = "j721s2-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@5f00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5f00000 0x00010000>,
<0x5f10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <282>;
ti,sci-proc-ids = <0x09 0xff>;
resets = <&k3_reset 282 1>;
firmware-name = "j721s2-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c71_0: dsp@64800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x64800000 0x00 0x00080000>,
<0x00 0x64e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <8>;
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 8 1>;
firmware-name = "j721s2-c71_0-fw";
status = "disabled";
};
c71_1: dsp@65800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x65800000 0x00 0x00080000>,
<0x00 0x65e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <11>;
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 11 1>;
firmware-name = "j721s2-c71_1-fw";
status = "disabled";
};
main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x700000 0x00 0x1000>;
ti,esm-pins = <688>, <689>;
bootph-pre-ram;
};
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2200000 0x00 0x100>;
clocks = <&k3_clks 286 1>;
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 286 1>;
assigned-clock-parents = <&k3_clks 286 5>;
};
watchdog1: watchdog@2210000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2210000 0x00 0x100>;
clocks = <&k3_clks 287 1>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 287 1>;
assigned-clock-parents = <&k3_clks 287 5>;
};
/*
* The following RTI instances are coupled with MCU R5Fs, c7x and
* GPU so keeping them reserved as these will be used by their
* respective firmware
*/
watchdog2: watchdog@22f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x22f0000 0x00 0x100>;
clocks = <&k3_clks 290 1>;
power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 290 1>;
assigned-clock-parents = <&k3_clks 290 5>;
/* reserved for GPU */
status = "reserved";
};
watchdog3: watchdog@2300000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2300000 0x00 0x100>;
clocks = <&k3_clks 288 1>;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 288 1>;
assigned-clock-parents = <&k3_clks 288 5>;
/* reserved for C7X_0 */
status = "reserved";
};
watchdog4: watchdog@2310000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2310000 0x00 0x100>;
clocks = <&k3_clks 289 1>;
power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 289 1>;
assigned-clock-parents = <&k3_clks 289 5>;
/* reserved for C7X_1 */
status = "reserved";
};
watchdog5: watchdog@23c0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23c0000 0x00 0x100>;
clocks = <&k3_clks 291 1>;
power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 291 1>;
assigned-clock-parents = <&k3_clks 291 5>;
/* reserved for MAIN_R5F0_0 */
status = "reserved";
};
watchdog6: watchdog@23d0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23d0000 0x00 0x100>;
clocks = <&k3_clks 292 1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 292 1>;
assigned-clock-parents = <&k3_clks 292 5>;
/* reserved for MAIN_R5F0_1 */
status = "reserved";
};
watchdog7: watchdog@23e0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23e0000 0x00 0x100>;
clocks = <&k3_clks 293 1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 293 1>;
assigned-clock-parents = <&k3_clks 293 5>;
/* reserved for MAIN_R5F1_0 */
status = "reserved";
};
watchdog8: watchdog@23f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23f0000 0x00 0x100>;
clocks = <&k3_clks 294 1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 294 1>;
assigned-clock-parents = <&k3_clks 294 5>;
/* reserved for MAIN_R5F1_1 */
status = "reserved";
};
};

82
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
View file

@ -443,7 +443,7 @@
};
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@ -655,4 +655,84 @@
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j721s2-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <284>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 284 1>;
firmware-name = "j721s2-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j721s2-r5f";
reg = <0x41400000 0x00010000>,
<0x41410000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <285>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 285 1>;
firmware-name = "j721s2-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
ti,esm-pins = <95>;
bootph-pre-ram;
};
wkup_esm: esm@42080000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
ti,esm-pins = <63>;
bootph-pre-ram;
};
/*
* The 2 RTI instances are couple with MCU R5Fs so keeping them
* reserved as these will be used by their respective firmware
*/
mcu_watchdog0: watchdog@40600000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x40600000 0x00 0x100>;
clocks = <&k3_clks 295 1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 295 1>;
assigned-clock-parents = <&k3_clks 295 5>;
/* reserved for MCU_R5F0_0 */
status = "reserved";
};
mcu_watchdog1: watchdog@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x40610000 0x00 0x100>;
clocks = <&k3_clks 296 1>;
power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 296 1>;
assigned-clock-parents = <&k3_clks 296 5>;
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
};

208
arch/arm/dts/k3-j721s2-som-p0.dtsi
View file

@ -29,6 +29,108 @@
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a8000000 {
reg = <0x00 0xa8000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
mux0: mux-controller {
@ -151,3 +253,109 @@
cdns,read-delay = <4>;
};
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};

2
arch/arm/dts/k3-serdes.h
View file

@ -111,7 +111,7 @@
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0

75
arch/arm/mach-k3/Kconfig
View file

@ -24,6 +24,11 @@ config SOC_K3_AM62A7
endchoice
if SOC_K3_J721E
config SOC_K3_J721E_J7200
bool "TI's K3 based J7200 SoC variant Family Support"
endif
config SYS_SOC
default "k3"
@ -109,56 +114,9 @@ config K3_EARLY_CONS_IDX
Use this option to set the index of the serial device to be used
for the early console during SPL execution.
config K3_LOAD_SYSFW
bool
depends on SPL
config K3_SYSFW_IMAGE_NAME
string "File name of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
default "sysfw.itb"
help
Filename of the combined System Firmware and configuration image tree
blob to be loaded when booting from a filesystem.
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
hex "MMC sector to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
default 0x3600
help
Address on the MMC to load the combined System Firmware and
configuration image tree blob from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
hex "MMC partition to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
default 2
help
Partition on the MMC to the combined System Firmware and configuration
image tree blob from, when the MMC is being used in raw mode.
config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW
default 280000
help
Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image
tree blob. Keep it as tight as possible, as this directly affects the
overall SPL memory footprint.
config K3_SYSFW_IMAGE_SPI_OFFS
hex "SPI offset of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
default 0x6C0000
help
Offset of the combined System Firmware and configuration image tree
blob to be loaded when booting from a SPI flash memory.
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
depends on SPL && CPU_V7R
depends on CPU_V7R
help
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
@ -172,7 +130,7 @@ config K3_ATF_LOAD_ADDR
config K3_DM_FW
bool "Separate DM firmware image"
depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@ -187,12 +145,15 @@ config K3_X509_SWRV
help
SWRV for X509 certificate used for boot images
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/am62x/Kconfig"
source "board/ti/am62ax/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
source "board/ti/j721s2/Kconfig"
source "board/toradex/verdin-am62/Kconfig"
if CPU_V7R
source "arch/arm/mach-k3/r5/Kconfig"
endif
source "arch/arm/mach-k3/am65x/Kconfig"
source "arch/arm/mach-k3/am64x/Kconfig"
source "arch/arm/mach-k3/am62x/Kconfig"
source "arch/arm/mach-k3/am62ax/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
endif

7
arch/arm/mach-k3/Makefile
View file

@ -3,12 +3,8 @@
# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
@ -24,6 +20,5 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o security.o

2
arch/arm/mach-k3/am625_init.c
View file

@ -209,7 +209,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
}
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

36
arch/arm/mach-k3/am62ax/Kconfig Normal file
View file

@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_AM62A7
choice
prompt "K3 AM62Ax based boards"
optional
config TARGET_AM62A7_A53_EVM
bool "TI K3 based AM62A7 EVM running on A53"
select ARM64
select BINMAN
imply BOARD
imply SPL_BOARD
imply TI_I2C_BOARD_DETECT
config TARGET_AM62A7_R5_EVM
bool "TI K3 based AM62A7 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
source "board/ti/am62ax/Kconfig"
endif

50
arch/arm/mach-k3/am62x/Kconfig Normal file
View file

@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_AM625
choice
prompt "K3 AM62x based boards"
optional
config TARGET_AM625_A53_EVM
bool "TI K3 based AM625 EVM running on A53"
select ARM64
select BINMAN
config TARGET_AM625_R5_EVM
bool "TI K3 based AM625 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
config TARGET_VERDIN_AM62_A53
bool "Toradex Verdin AM62 running on A53"
select ARM64
select BINMAN
config TARGET_VERDIN_AM62_R5
bool "Toradex Verdin AM62 running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
endchoice
source "board/beagle/beagleplay/Kconfig"
source "board/ti/am62x/Kconfig"
source "board/toradex/verdin-am62/Kconfig"
endif

36
arch/arm/mach-k3/am64x/Kconfig Normal file
View file

@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_AM642
choice
prompt "K3 AM64 based boards"
optional
config TARGET_AM642_A53_EVM
bool "TI K3 based AM642 EVM running on A53"
select ARM64
select BINMAN
imply BOARD
imply SPL_BOARD
imply TI_I2C_BOARD_DETECT
config TARGET_AM642_R5_EVM
bool "TI K3 based AM642 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
source "board/ti/am64x/Kconfig"
endif

2
arch/arm/mach-k3/am654_init.c
View file

@ -258,7 +258,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

45
arch/arm/mach-k3/am65x/Kconfig Normal file
View file

@ -0,0 +1,45 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_AM654
choice
prompt "K3 AM65 based boards"
optional
config TARGET_AM654_A53_EVM
bool "TI K3 based AM654 EVM running on A53"
select ARM64
select SYS_DISABLE_DCACHE_OPS
select BOARD_LATE_INIT
select BINMAN
imply TI_I2C_BOARD_DETECT
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select K3_AM654_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
config TARGET_IOT2050_A53
bool "IOT2050 running on A53"
depends on SOC_K3_AM654
select ARM64
select BOARD_LATE_INIT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
help
This builds U-Boot for the IOT2050 devices.
endchoice
source "board/ti/am65x/Kconfig"
source "board/siemens/iot2050/Kconfig"
endif

108
arch/arm/mach-k3/arm64-mmu.c
View file

@ -67,7 +67,59 @@ struct mm_region *mem_map = am654_mem_map;
#ifdef CONFIG_SOC_K3_J721E
#ifdef CONFIG_TARGET_J721E_A72_EVM
#ifdef CONFIG_SOC_K3_J721E_J7200
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xa4800000UL,
.phys = 0xa4800000UL,
.size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j7200_mem_map;
#else /* CONFIG_SOC_K3_J721E_J7200 */
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
@ -124,59 +176,7 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
};
struct mm_region *mem_map = j721e_mem_map;
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xa4800000UL,
.phys = 0xa4800000UL,
.size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#endif /* CONFIG_SOC_K3_J721E_J7200 */
#endif /* CONFIG_SOC_K3_J721E */

4
arch/arm/mach-k3/common.c
View file

@ -521,7 +521,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
}
}
void spl_enable_dcache(void)
void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
@ -542,7 +542,7 @@ void spl_enable_dcache(void)
gd->arch.tlb_addr + gd->arch.tlb_size);
gd->relocaddr = gd->arch.tlb_addr;
dcache_enable();
enable_caches();
#endif
}

2
arch/arm/mach-k3/common.h
View file

@ -37,7 +37,7 @@ void disable_linefill_optimization(void);
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
void spl_enable_cache(void);
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);

58
arch/arm/mach-k3/j721e/Kconfig Normal file
View file

@ -0,0 +1,58 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_J721E
choice
prompt "K3 J721E based boards"
optional
config TARGET_J721E_A72_EVM
bool "TI K3 based J721E EVM running on A72"
select ARM64
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
config TARGET_J721E_R5_EVM
bool "TI K3 based J721E EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
config TARGET_J7200_A72_EVM
bool "TI K3 based J7200 EVM running on A72"
select ARM64
select SOC_K3_J721E_J7200
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
config TARGET_J7200_R5_EVM
bool "TI K3 based J7200 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
source "board/beagle/beagleboneai64/Kconfig"
source "board/ti/j721e/Kconfig"
endif

11
arch/arm/mach-k3/j721e_init.c
View file

@ -286,14 +286,21 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
if (spl_mmc_emmc_boot_partition(mmc))
return MMCSD_MODE_EMMCBOOT;
return MMCSD_MODE_FS;
}
if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:

36
arch/arm/mach-k3/j721s2/Kconfig Normal file
View file

@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
if SOC_K3_J721S2
choice
prompt "K3 J721S2 based boards"
optional
config TARGET_J721S2_A72_EVM
bool "TI K3 based J721S2 EVM running on A72"
select ARM64
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
config TARGET_J721S2_R5_EVM
bool "TI K3 based J721S2 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
source "board/ti/j721s2/Kconfig"
endif

2
arch/arm/mach-k3/j721s2_init.c
View file

@ -231,7 +231,7 @@ void k3_mem_init(void)
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
spl_enable_dcache();
spl_enable_cache();
}
/* Support for the various EVM / SK families */

0
board/ti/keys/custMpk.crt → arch/arm/mach-k3/keys/custMpk.crt
View file

0
board/ti/keys/custMpk.key → arch/arm/mach-k3/keys/custMpk.key
View file

0
board/ti/keys/custMpk.pem → arch/arm/mach-k3/keys/custMpk.pem
View file

0
board/ti/keys/ti-degenerate-key.pem → arch/arm/mach-k3/keys/ti-degenerate-key.pem
View file

45
arch/arm/mach-k3/r5/Kconfig Normal file
View file

@ -0,0 +1,45 @@
config K3_LOAD_SYSFW
bool
config K3_SYSFW_IMAGE_NAME
string "File name of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
default "sysfw.itb"
help
Filename of the combined System Firmware and configuration image tree
blob to be loaded when booting from a filesystem.
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
hex "MMC sector to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
default 0x3600
help
Address on the MMC to load the combined System Firmware and
configuration image tree blob from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
hex "MMC partition to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
default 2
help
Partition on the MMC to the combined System Firmware and configuration
image tree blob from, when the MMC is being used in raw mode.
config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW
default 280000
help
Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image
tree blob. Keep it as tight as possible, as this directly affects the
overall SPL memory footprint.
config K3_SYSFW_IMAGE_SPI_OFFS
hex "SPI offset of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
default 0x6C0000
help
Offset of the combined System Firmware and configuration image tree
blob to be loaded when booting from a SPI flash memory.

17
arch/arm/mach-k3/r5/Makefile Normal file
View file

@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_SOC_K3_J721E) += j721e/
obj-$(CONFIG_SOC_K3_J721E) += j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
obj-y += lowlevel_init.o
obj-y += r5_mpu.o
ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif

0
arch/arm/mach-k3/am62ax/Makefile → arch/arm/mach-k3/r5/am62ax/Makefile
View file

0
arch/arm/mach-k3/am62ax/am62a_qos_data.c → arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
View file

0
arch/arm/mach-k3/am62ax/clk-data.c → arch/arm/mach-k3/r5/am62ax/clk-data.c
View file

1
arch/arm/mach-k3/am62ax/dev-data.c → arch/arm/mach-k3/r5/am62ax/dev-data.c
View file

@ -52,6 +52,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(161, &soc_lpsc_list[5]),
PSC_DEV(162, &soc_lpsc_list[6]),
PSC_DEV(75, &soc_lpsc_list[7]),
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
PSC_DEV(166, &soc_lpsc_list[9]),

0
arch/arm/mach-k3/am62x/Makefile → arch/arm/mach-k3/r5/am62x/Makefile
View file

0
arch/arm/mach-k3/am62x/clk-data.c → arch/arm/mach-k3/r5/am62x/clk-data.c
View file

0
arch/arm/mach-k3/am62x/dev-data.c → arch/arm/mach-k3/r5/am62x/dev-data.c
View file

0
arch/arm/mach-k3/j7200/Makefile → arch/arm/mach-k3/r5/j7200/Makefile
View file

0
arch/arm/mach-k3/j7200/clk-data.c → arch/arm/mach-k3/r5/j7200/clk-data.c
View file

0
arch/arm/mach-k3/j7200/dev-data.c → arch/arm/mach-k3/r5/j7200/dev-data.c
View file

0
arch/arm/mach-k3/j721e/Makefile → arch/arm/mach-k3/r5/j721e/Makefile
View file

0
arch/arm/mach-k3/j721e/clk-data.c → arch/arm/mach-k3/r5/j721e/clk-data.c
View file

0
arch/arm/mach-k3/j721e/dev-data.c → arch/arm/mach-k3/r5/j721e/dev-data.c
View file

0
arch/arm/mach-k3/j721s2/Makefile → arch/arm/mach-k3/r5/j721s2/Makefile
View file

0
arch/arm/mach-k3/j721s2/clk-data.c → arch/arm/mach-k3/r5/j721s2/clk-data.c
View file

0
arch/arm/mach-k3/j721s2/dev-data.c → arch/arm/mach-k3/r5/j721s2/dev-data.c
View file

0
arch/arm/mach-k3/lowlevel_init.S → arch/arm/mach-k3/r5/lowlevel_init.S
View file

3
arch/arm/mach-k3/r5_mpu.c → arch/arm/mach-k3/r5/r5_mpu.c
View file

@ -6,9 +6,10 @@
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#include <config.h>
#include <asm/io.h>
#include <linux/kernel.h>
#include "common.h"
#include <asm/armv7_mpu.h>
struct mpu_region_config k3_mpu_regions[16] = {
/*

2
arch/arm/mach-k3/sysfw-loader.c → arch/arm/mach-k3/r5/sysfw-loader.c
View file

@ -22,7 +22,7 @@
#include <spi_flash.h>
#include <asm/io.h>
#include "common.h"
#include "../common.h"
DECLARE_GLOBAL_DATA_PTR;

2
arch/arm/mach-omap2/omap3/Kconfig
View file

@ -152,7 +152,7 @@ config SYS_SOC
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/beagle/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig"

2
board/ti/beagle/Kconfig → board/beagle/beagle/Kconfig
View file

@ -4,7 +4,7 @@ config SYS_BOARD
default "beagle"
config SYS_VENDOR
default "ti"
default "beagle"
config SYS_CONFIG_NAME
default "omap3_beagle"

2
board/ti/beagle/MAINTAINERS → board/beagle/beagle/MAINTAINERS
View file

@ -1,6 +1,6 @@
BEAGLE BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/beagle/
F: board/beagle/beagle/
F: include/configs/omap3_beagle.h
F: configs/omap3_beagle_defconfig

0
board/ti/beagle/Makefile → board/beagle/beagle/Makefile
View file

0
board/ti/beagle/beagle.c → board/beagle/beagle/beagle.c
View file

0
board/ti/beagle/beagle.h → board/beagle/beagle/beagle.h
View file

0
board/ti/beagle/led.c → board/beagle/beagle/led.c
View file

59
board/beagle/beagleboneai64/Kconfig Normal file
View file

@ -0,0 +1,59 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
#
choice
prompt "BeagleBoard.org J721E/TDA4VM based BeagleBone AI-64 board"
optional
config TARGET_J721E_A72_BEAGLEBONEAI64
bool "BeagleBoard.org J721E BeagleBone AI-64 running on A72"
select ARM64
select SYS_DISABLE_DCACHE_OPS
select BINMAN
config TARGET_J721E_R5_BEAGLEBONEAI64
bool "BeagleBoard.org J721E BeagleBone AI-64 running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
endchoice
if TARGET_J721E_A72_BEAGLEBONEAI64
config SYS_BOARD
default "beagleboneai64"
config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
default "j721e_evm"
source "board/ti/common/Kconfig"
endif
if TARGET_J721E_R5_BEAGLEBONEAI64
config SYS_BOARD
default "beagleboneai64"
config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
default "j721e_evm"
source "board/ti/common/Kconfig"
endif

6
board/beagle/beagleboneai64/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
BEAGLEBONE-AI64 BOARD
M: Nishanth Menon <nm@ti.com>
M: Robert Nelson <robertcnelson@gmail.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
N: beagleboneai64

10
board/beagle/beagleboneai64/Makefile Normal file
View file

@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# https://beagleboard.org/ai-64
#
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
#
obj-y += beagleboneai64.o

30
board/beagle/beagleboneai64/beagleboneai64.c Normal file
View file

@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/ai-64
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include <cpu_func.h>
#include <env.h>
#include <fdt_support.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}

0
board/ti/am62x/beagleplay.env → board/beagle/beagleboneai64/beagleboneai64.env
View file

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