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https://github.com/AsahiLinux/u-boot
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ppc4xx: Update lwmon5 board
- Add optional ECC generation routine to preserve existing RAM values. This is needed for the Linux log-buffer support - Add optional DDR2 setup with CL=4 - GPIO50 not used anymore - Lime register setup added Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
98c440bee6
commit
04e6c38b76
3 changed files with 87 additions and 10 deletions
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@ -19,9 +19,10 @@
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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#include <asm/processor.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -220,6 +221,13 @@ int misc_init_r(void)
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udelay(500);
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gpio_write_bit(CFG_GPIO_LIME_RST, 1);
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/* Lime memory clock adjusted to 133MHz */
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out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
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/* Wait untill time expired. Because of requirements in lime manual */
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udelay(300);
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/* Write lime controller memory parameters */
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out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
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/*
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* Reset PHY's
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*/
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@ -229,13 +237,6 @@ int misc_init_r(void)
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gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
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/*
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* Reset USB hub
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*/
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gpio_write_bit(CFG_GPIO_HUB_RST, 0);
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udelay(100);
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gpio_write_bit(CFG_GPIO_HUB_RST, 1);
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return 0;
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}
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@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
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blank_string(strlen(str));
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} else {
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/* ECC bit set method for cached memory */
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#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
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/*
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* Some boards (like lwmon5) need to preserve the memory
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* content upon ECC generation (for the log-buffer).
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* Therefore we don't fill the memory with a pattern or
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* just zero it, but write the same values back that are
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* already in the memory cells.
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*/
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address_increment = CFG_CACHELINE_SIZE;
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end_address = current_address + num_bytes;
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current_address = start_address;
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while (current_address < end_address) {
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ppcDcbi(current_address);
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ppcDcbf(current_address);
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current_address += CFG_CACHELINE_SIZE;
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}
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#else
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dcbz_area(start_address, num_bytes);
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dflush();
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#endif
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}
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sync();
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@ -518,6 +537,8 @@ long int initdram (int board_type)
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{
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u32 val;
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#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
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/* CL=3 */
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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@ -558,6 +579,49 @@ long int initdram (int board_type)
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mtsdram(DDR0_43, 0x030A0200);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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#else
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/* CL=4 */
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
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mtsdram(DDR0_04, 0x0B030300);
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mtsdram(DDR0_05, 0x02020308);
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mtsdram(DDR0_06, 0x0003C812);
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mtsdram(DDR0_07, 0x00090100);
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mtsdram(DDR0_08, 0x03c80001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000300);
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mtsdram(DDR0_11, 0x000CC800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x1e000000);
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mtsdram(DDR0_18, 0x1e1e1e1e);
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mtsdram(DDR0_19, 0x1e1e1e1e);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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#ifdef CONFIG_DDR_ECC
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mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
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#else
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mtsdram(DDR0_22, 0x00267F0B);
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#endif
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mtsdram(DDR0_23, 0x01000000);
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mtsdram(DDR0_24, 0x01010001);
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mtsdram(DDR0_26, 0x2D93028A);
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mtsdram(DDR0_27, 0x0784682B);
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mtsdram(DDR0_28, 0x00000080);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000008);
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mtsdram(DDR0_43, 0x050A0200);
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mtsdram(DDR0_44, 0x00000005);
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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#endif
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wait_for_dlllock();
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@ -326,13 +326,25 @@
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#define CFG_EBC_CFG 0xb8400000
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/*-----------------------------------------------------------------------
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* Graphics (Fujitsu Lime)
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*----------------------------------------------------------------------*/
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/* SDRAM Clock frequency adjustment register */
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#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
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/* Lime Clock frequency is to set 133MHz */
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#define CFG_LIME_CLOCK_133MHZ 0x10000
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/* SDRAM Parameter register */
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#define CFG_LIME_MMR 0xC1FCFFFC
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/* SDRAM parameter value */
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#define CFG_LIME_MMR_VALUE 0x414FB7F2
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_GPIO_PHY1_RST 12
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#define CFG_GPIO_FLASH_WP 14
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#define CFG_GPIO_PHY0_RST 22
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#define CFG_GPIO_HUB_RST 50
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#define CFG_GPIO_WATCHDOG 58
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#define CFG_GPIO_LIME_S 59
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#define CFG_GPIO_LIME_RST 60
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@ -396,7 +408,7 @@
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
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