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https://github.com/AsahiLinux/u-boot
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sh: Update MS7750SE01 platform
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
parent
516ad760db
commit
047375bfa4
3 changed files with 94 additions and 50 deletions
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@ -1,7 +1,28 @@
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/*
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modified from SH-IPL+g
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Renesaso SuperH Solution Enginge MS775x BSC setting
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Coyright (c) 2007 Nobuhiro Iwamatsu
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Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
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Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
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Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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@ -9,38 +30,34 @@
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#include <asm/processor.h>
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#ifdef CONFIG_CPU_SUBTYPE_SH7751
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#ifdef CONFIG_CPU_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
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#ifdef CONFIG_MRSHPC
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#ifdef CONFIG_MARUBUN_PCCARD
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#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#else /* CONFIG_MRSHPC*/
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#else /* CONFIG_MARUBUN_PCCARD */
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#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#endif /* CONFIG_MRSHPC */
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#endif /* CONFIG_MARUBUN_PCCARD */
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#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define LED_ADDRESS 0xBA000000 /* Address of LED register */
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#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
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#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
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#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
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#define SWITCH_ADDR 0xB9000000 /* Address of DIP switches */
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#else /* CONFIG_CPU_SUBTYPE_SH7751 */
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#else /* CONFIG_CPU_SH7751 */
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#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
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#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
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#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:15 A0B:7 */
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#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define LED_ADDRESS 0xB0C00000 /* Address of LED register */
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#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
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#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
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#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
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#define SWITCH_ADDR 0xb0800000 /* Address of DIP switches */
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#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
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#endif /* CONFIG_CPU_SH7751 */
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.global lowlevel_init
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.text
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@ -48,8 +65,8 @@
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lowlevel_init:
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mov.l L_CCR, r1 ! CCR Address
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mov.l L_CCR_DISABLE, r0 ! CCR Data
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mov.l CCR_A, r1 ! CCR Address
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mov.l CCR_D_DISABLE, r0 ! CCR Data
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mov.l r0, @r1
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init_bsc:
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@ -77,11 +94,6 @@ init_bsc:
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mov.l WCR3_D,r0 /* WCR3 Data */
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mov.l r0,@r1
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mov.l LED_A,r1 /* LED Address */
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mov #0xff,r0 /* LED ALL 'on' */
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shll8 r0
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mov.w r0,@r1
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mov.l MCR_A,r1 /* MCR Address */
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mov.l MCR_D1,r0 /* MCR Data1 */
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mov.l r0,@r1
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@ -129,19 +141,19 @@ init_bsc:
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.align 2
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L_CCR: .long CCR
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L_CCR_DISABLE: .long 0x0808
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CCR_A: .long CCR
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CCR_D_DISABLE: .long 0x0808
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FRQCR_A: .long FRQCR
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FRQCR_D:
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#ifdef CONFIG_CPU_SUBTYPE_SH_R
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#ifdef CONFIG_CPU_TYPE_R
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.long 0x00000e1a /* 12:3:3 */
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#else
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#else /* CONFIG_CPU_TYPE_R */
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#ifdef CONFIG_GOOD_SESH4
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.long 0x00000e13 /* 6:2:1 */
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#else
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.long 0x00000e23 /* 6:1:1 */
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#endif
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#endif /* CONFIG_CPU_SUBTYPE_SH_R */
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#endif /* CONFIG_CPU_TYPE_R */
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BCR1_A: .long BCR1
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BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
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@ -153,7 +165,6 @@ WCR2_A: .long WCR2
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WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
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WCR3_A: .long WCR3
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
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LED_A: .long LED_ADDRESS /* LED Address */
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RTCSR_A: .long RTCSR
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RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
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RTCNT_A: .long RTCNT
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@ -26,7 +26,7 @@
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int checkboard(void)
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{
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puts("BOARD: SH7750 Solution Engine\n");
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puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
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return 0;
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}
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@ -1,28 +1,58 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Configuation settings for the Hitachi Solution Engine 7750
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MS7750SE_H
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#define __MS7750SE_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH4 1
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#define CONFIG_CPU_SH7750 1
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/* #define CONFIG_CPU_SH7751 1 */
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/* #define CONFIG_CPU_TYPE_R 1 */
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#define CONFIG_MS7750SE 1
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#define __LITTLE_ENDIAN__ 1
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//#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING)
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#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET
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/*
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* Command line configuration.
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*/
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//#include <config_cmd_default.h>
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_ENV
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#define CFG_SCIF_CONSOLE 1
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_CONS_SCIF1 1
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#define BOARD_LATE_INIT 1
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_BOOTARGS "console=ttySC0,38400"
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CFG_SDRAM_BASE (0x8C000000)
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#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
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@ -32,11 +62,20 @@
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#define CFG_PBSIZE 256
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#define CFG_MAXARGS 16
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#define CFG_BARGSIZE 512
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */
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/* List of legal baudrate settings for this board */
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
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#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
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/* NOR Flash */
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/* #define CFG_FLASH_BASE (0xA1000000)*/
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#define CFG_FLASH_BASE (0xA0000000)
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#define CFG_MAX_FLASH_BANKS (1) /* Max number of
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* Flash memory banks
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*/
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#define CFG_MAX_FLASH_SECT 142
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
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@ -53,12 +92,6 @@
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#undef CFG_FLASH_QUIET_TEST
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_BASE (0xA1000000)
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#define CFG_MAX_FLASH_BANKS (1) /* Max number of
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* Flash memory banks
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*/
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#define CFG_MAX_FLASH_SECT 142
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000
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@ -67,9 +100,9 @@
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#define CFG_FLASH_ERASE_TOUT 120000
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#define CFG_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define TMU_CLK_DIVIDER 4
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
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#define CFG_PLL_SETTLING_TIME 100 /* in us */
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#endif /* __CONFIG_H */
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#endif /* __MS7750SE_H */
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