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sh: Update MS7750SE01 platform

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Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2007-09-23 02:19:24 +09:00
parent 516ad760db
commit 047375bfa4
3 changed files with 94 additions and 50 deletions
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63
board/ms7750se/lowlevel_init.S
View file

@ -1,7 +1,28 @@
/* /*
modified from SH-IPL+g modified from SH-IPL+g
Renesaso SuperH Solution Enginge MS775x BSC setting Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
Coyright (c) 2007 Nobuhiro Iwamatsu
Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/ */
#include <config.h> #include <config.h>
@ -9,38 +30,34 @@
#include <asm/processor.h> #include <asm/processor.h>
#ifdef CONFIG_CPU_SUBTYPE_SH7751 #ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MRSHPC #ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */ A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MRSHPC*/ #else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */ A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MRSHPC */ #endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */ A2: 1-3 A1: 1-3 A0: 0-1 */
#define LED_ADDRESS 0xBA000000 /* Address of LED register */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#define SWITCH_ADDR 0xB9000000 /* Address of DIP switches */ #else /* CONFIG_CPU_SH7751 */
#else /* CONFIG_CPU_SUBTYPE_SH7751 */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */ A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */ A2: 1-3 A1: 1-3 A0: 0-1 */
#define LED_ADDRESS 0xB0C00000 /* Address of LED register */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#define SWITCH_ADDR 0xb0800000 /* Address of DIP switches */ #endif /* CONFIG_CPU_SH7751 */
#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
.global lowlevel_init .global lowlevel_init
.text .text
@ -48,8 +65,8 @@
lowlevel_init: lowlevel_init:
mov.l L_CCR, r1 ! CCR Address mov.l CCR_A, r1 ! CCR Address
mov.l L_CCR_DISABLE, r0 ! CCR Data mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1 mov.l r0, @r1
init_bsc: init_bsc:
@ -77,11 +94,6 @@ init_bsc:
mov.l WCR3_D,r0 /* WCR3 Data */ mov.l WCR3_D,r0 /* WCR3 Data */
mov.l r0,@r1 mov.l r0,@r1
mov.l LED_A,r1 /* LED Address */
mov #0xff,r0 /* LED ALL 'on' */
shll8 r0
mov.w r0,@r1
mov.l MCR_A,r1 /* MCR Address */ mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D1,r0 /* MCR Data1 */ mov.l MCR_D1,r0 /* MCR Data1 */
mov.l r0,@r1 mov.l r0,@r1
@ -129,19 +141,19 @@ init_bsc:
.align 2 .align 2
L_CCR: .long CCR CCR_A: .long CCR
L_CCR_DISABLE: .long 0x0808 CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR FRQCR_A: .long FRQCR
FRQCR_D: FRQCR_D:
#ifdef CONFIG_CPU_SUBTYPE_SH_R #ifdef CONFIG_CPU_TYPE_R
.long 0x00000e1a /* 12:3:3 */ .long 0x00000e1a /* 12:3:3 */
#else #else /* CONFIG_CPU_TYPE_R */
#ifdef CONFIG_GOOD_SESH4 #ifdef CONFIG_GOOD_SESH4
.long 0x00000e13 /* 6:2:1 */ .long 0x00000e13 /* 6:2:1 */
#else #else
.long 0x00000e23 /* 6:1:1 */ .long 0x00000e23 /* 6:1:1 */
#endif #endif
#endif /* CONFIG_CPU_SUBTYPE_SH_R */ #endif /* CONFIG_CPU_TYPE_R */
BCR1_A: .long BCR1 BCR1_A: .long BCR1
BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
@ -153,7 +165,6 @@ WCR2_A: .long WCR2
WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
WCR3_A: .long WCR3 WCR3_A: .long WCR3
WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
LED_A: .long LED_ADDRESS /* LED Address */
RTCSR_A: .long RTCSR RTCSR_A: .long RTCSR
RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
RTCNT_A: .long RTCNT RTCNT_A: .long RTCNT

2
board/ms7750se/ms7750se.c
View file

@ -26,7 +26,7 @@
int checkboard(void) int checkboard(void)
{ {
puts("BOARD: SH7750 Solution Engine\n"); puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
return 0; return 0;
} }

79
include/configs/ms7750se.h
View file

@ -1,50 +1,89 @@
#ifndef __CONFIG_H /*
#define __CONFIG_H * Configuation settings for the Hitachi Solution Engine 7750
*
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MS7750SE_H
#define __MS7750SE_H
#undef DEBUG #undef DEBUG
#define CONFIG_SH 1 #define CONFIG_SH 1
#define CONFIG_SH4 1 #define CONFIG_SH4 1
#define CONFIG_CPU_SH7750 1 #define CONFIG_CPU_SH7750 1
/* #define CONFIG_CPU_SH7751 1 */
/* #define CONFIG_CPU_TYPE_R 1 */
#define CONFIG_MS7750SE 1 #define CONFIG_MS7750SE 1
#define __LITTLE_ENDIAN__ 1 #define __LITTLE_ENDIAN__ 1
//#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING) /*
#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET * Command line configuration.
*/
//#include <config_cmd_default.h>
#define CONFIG_CMD_DFL
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV
#define CFG_SCIF_CONSOLE 1 #define CFG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 38400 #define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_SCIF1 1 #define CONFIG_CONS_SCIF1 1
#define BOARD_LATE_INIT 1 #define BOARD_LATE_INIT 1
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTARGS "console=ttySC0,38400"
#define CONFIG_ENV_OVERWRITE 1 #define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (64 * 1024 * 1024) #define CFG_SDRAM_SIZE (64 * 1024 * 1024)
#define CFG_LONGHELP #define CFG_LONGHELP
#define CFG_PROMPT "=> " #define CFG_PROMPT "=> "
#define CFG_CBSIZE 256 #define CFG_CBSIZE 256
#define CFG_PBSIZE 256 #define CFG_PBSIZE 256
#define CFG_MAXARGS 16 #define CFG_MAXARGS 16
#define CFG_BARGSIZE 512 #define CFG_BARGSIZE 512
#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */ /* List of legal baudrate settings for this board */
#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
#define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_START (CFG_SDRAM_BASE)
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
/* NOR Flash */
/* #define CFG_FLASH_BASE (0xA1000000)*/
#define CFG_FLASH_BASE (0xA0000000)
#define CFG_MAX_FLASH_BANKS (1) /* Max number of
* Flash memory banks
*/
#define CFG_MAX_FLASH_SECT 142
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
#define CFG_MONITOR_LEN (128 * 1024) #define CFG_MONITOR_LEN (128 * 1024)
#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
#define CFG_BOOTMAPSZ (8 * 1024 * 1024) #define CFG_BOOTMAPSZ (8 * 1024 * 1024)
#define CFG_RX_ETH_BUFFER (8) #define CFG_RX_ETH_BUFFER (8)
#define CFG_FLASH_CFI #define CFG_FLASH_CFI
@ -53,12 +92,6 @@
#undef CFG_FLASH_QUIET_TEST #undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_BASE (0xA1000000)
#define CFG_MAX_FLASH_BANKS (1) /* Max number of
* Flash memory banks
*/
#define CFG_MAX_FLASH_SECT 142
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_ENV_IS_IN_FLASH #define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SECT_SIZE 0x20000
@ -67,9 +100,9 @@
#define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500 #define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333 #define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4 #define TMU_CLK_DIVIDER 4
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CFG_PLL_SETTLING_TIME 100 /* in us */
#endif /* __CONFIG_H */ #endif /* __MS7750SE_H */