mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
This commit is contained in:
Wolfgang Denk
commit
045639397d
9 changed files with 343 additions and 224 deletions
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@ -180,13 +180,7 @@ static struct manufacturer_info flash_manufacturers[] = {
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* BF51x, BF533, BF561: SSEL2
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*/
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#ifndef CONFIG_SPI_FLASH_SSEL
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# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
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defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
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defined(__ADSPBF51x__)
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# define CONFIG_SPI_FLASH_SSEL 2
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# else
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# define CONFIG_SPI_FLASH_SSEL 1
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# endif
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# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL
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#endif
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#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
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@ -20,7 +20,7 @@
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#include "serial.h"
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__attribute__((always_inline))
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static inline uint32_t serial_init(void)
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static inline void serial_init(void)
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{
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#ifdef __ADSPBF54x__
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# ifdef BFIN_BOOT_UART_USE_RTS
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@ -61,27 +61,18 @@ static inline uint32_t serial_init(void)
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}
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#endif
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uint32_t old_baud;
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if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
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old_baud = serial_early_get_baud();
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else
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old_baud = CONFIG_BAUDRATE;
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if (BFIN_DEBUG_EARLY_SERIAL) {
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int ucen = *pUART_GCTL & UCEN;
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serial_early_init();
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/* If the UART is off, that means we need to program
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* the baud rate ourselves initially.
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*/
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if (!old_baud) {
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old_baud = CONFIG_BAUDRATE;
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if (ucen != UCEN)
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serial_early_set_baud(CONFIG_BAUDRATE);
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}
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}
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return old_baud;
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}
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__attribute__((always_inline))
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static inline void serial_deinit(void)
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{
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@ -93,30 +84,6 @@ static inline void serial_deinit(void)
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#endif
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}
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/* We need to reset the baud rate when we have early debug turned on
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* or when we are booting over the UART.
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* XXX: we should fix this to calc the old baud and restore it rather
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* than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
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* to figure out how to avoid the division in the baud calc ...
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*/
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__attribute__((always_inline))
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static inline void serial_reset_baud(uint32_t baud)
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{
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if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
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return;
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#ifndef CONFIG_LDR_LOAD_BAUD
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# define CONFIG_LDR_LOAD_BAUD 115200
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#endif
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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serial_early_set_baud(baud);
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else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
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serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
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else
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serial_early_set_baud(CONFIG_BAUDRATE);
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}
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__attribute__((always_inline))
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static inline void serial_putc(char c)
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{
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@ -133,12 +100,22 @@ static inline void serial_putc(char c)
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}
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/* Max SCLK can be 133MHz ... dividing that by 4 gives
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* us a freq of 33MHz for SPI which should generally be
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/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
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* us a freq of 16MHz for SPI which should generally be
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* slow enough for the slow reads the bootrom uses.
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*/
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#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
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((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
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(defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
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# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
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#else
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# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
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#endif
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#ifndef CONFIG_SPI_BAUD_INITBLOCK
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# define CONFIG_SPI_BAUD_INITBLOCK 4
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# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
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#endif
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#ifdef SPI0_BAUD
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# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
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#endif
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/* PLL_DIV defines */
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@ -168,11 +145,18 @@ static inline void serial_putc(char c)
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#ifndef CONFIG_EBIU_RSTCTL_VAL
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# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
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#endif
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#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
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# error invalid EBIU_RSTCTL value: must not set reserved bits
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#endif
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#ifndef CONFIG_EBIU_MBSCTL_VAL
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# define CONFIG_EBIU_MBSCTL_VAL 0
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#endif
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#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
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# error invalid EBIU_DDRQUE value: must not set reserved bits
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#endif
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/* Make sure our voltage value is sane so we don't blow up! */
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#ifndef CONFIG_VR_CTL_VAL
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# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
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@ -199,6 +183,9 @@ static inline void serial_putc(char c)
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# elif defined(__ADSPBF54x__) /* TBD; use default */
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# undef CONFIG_VR_CTL_VLEV
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# define CONFIG_VR_CTL_VLEV VLEV_120
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# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
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# undef CONFIG_VR_CTL_VLEV
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# define CONFIG_VR_CTL_VLEV VLEV_125
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# endif
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# ifdef CONFIG_BFIN_MAC
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@ -216,10 +203,17 @@ static inline void serial_putc(char c)
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# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
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#endif
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__attribute__((saveall))
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BOOTROM_CALLED_FUNC_ATTR
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void initcode(ADI_BOOT_DATA *bootstruct)
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{
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uint32_t old_baud = serial_init();
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/* Save the clock pieces that are used in baud rate calculation */
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unsigned int sdivB, divB, vcoB;
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serial_init();
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if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
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sdivB = bfin_read_PLL_DIV() & 0xf;
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vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
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divB = serial_early_get_div();
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}
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#ifdef CONFIG_HW_WATCHDOG
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# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
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@ -244,12 +238,11 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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* boot. Once we switch over to u-boot's SPI flash driver, we'll
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* increase the speed appropriately.
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*/
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#ifdef SPI0_BAUD
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bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
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#else
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
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if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
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bootstruct->dFlags |= BFLAG_FASTREAD;
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bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
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#endif
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}
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serial_putc('B');
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@ -267,6 +260,21 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_SIC_IWR(1);
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#endif
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/* With newer bootroms, we use the helper function to set up
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* the memory controller. Older bootroms lacks such helpers
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* so we do it ourselves.
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*/
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if (BOOTROM_CAPS_SYSCONTROL) {
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serial_putc('S');
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ADI_SYSCTRL_VALUES memory_settings;
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memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
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memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
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memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
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memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
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syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
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(CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
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} else {
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serial_putc('L');
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bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
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@ -296,11 +304,24 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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}
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}
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/* Since we've changed the SCLK above, we may need to update
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* the UART divisors (UART baud rates are based on SCLK).
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* Do the division by hand as there are no native instructions
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* for dividing which means we'd generate a libgcc reference.
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*/
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serial_reset_baud(old_baud);
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
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unsigned int sdivR, vcoR;
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sdivR = bfin_read_PLL_DIV() & 0xf;
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vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
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int dividend = sdivB * divB * vcoR;
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int divisor = vcoB * sdivR;
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unsigned int quotient;
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for (quotient = 0; dividend > 0; ++quotient)
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dividend -= divisor;
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serial_early_put_div(quotient - ANOMALY_05000230);
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}
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serial_putc('F');
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@ -156,44 +156,8 @@ static inline void serial_early_init(void)
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}
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__attribute__((always_inline))
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static inline uint32_t serial_early_get_baud(void)
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static inline void serial_early_put_div(uint16_t divisor)
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{
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/* If the UART isnt enabled, then we are booting an LDR
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* from a non-UART source (so like flash) which means
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* the baud rate here is meaningless.
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*/
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if ((*pUART_GCTL & UCEN) != UCEN)
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return 0;
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#if (0) /* See comment for serial_reset_baud() in initcode.c */
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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uint8_t dll = *pUART_DLL;
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uint8_t dlh = *pUART_DLH;
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uint16_t divisor = (dlh << 8) | dll;
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uint32_t baud = get_sclk() / (divisor * 16);
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/* Clear DLAB in LCR to Access THR RBR IER */
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ACCESS_PORT_IER();
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SSYNC();
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return baud;
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#else
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return CONFIG_BAUDRATE;
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#endif
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}
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__attribute__((always_inline))
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static inline void serial_early_set_baud(uint32_t baud)
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{
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/* Translate from baud into divisor in terms of SCLK. The
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* weird multiplication is to make sure we over sample just
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* a little rather than under sample the incoming signals.
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*/
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uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230;
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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@ -208,6 +172,34 @@ static inline void serial_early_set_baud(uint32_t baud)
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SSYNC();
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}
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__attribute__((always_inline))
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static inline uint16_t serial_early_get_div(void)
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{
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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uint8_t dll = *pUART_DLL;
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uint8_t dlh = *pUART_DLH;
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uint16_t divisor = (dlh << 8) | dll;
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/* Clear DLAB in LCR to Access THR RBR IER */
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ACCESS_PORT_IER();
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SSYNC();
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return divisor;
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}
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__attribute__((always_inline))
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static inline void serial_early_set_baud(uint32_t baud)
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{
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/* Translate from baud into divisor in terms of SCLK. The
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* weird multiplication is to make sure we over sample just
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* a little rather than under sample the incoming signals.
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*/
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serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
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}
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#ifndef BFIN_IN_INITCODE
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__attribute__((always_inline))
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static inline void serial_early_puts(const char *s)
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@ -235,32 +227,6 @@ static inline void serial_early_puts(const char *s)
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#endif
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.endm
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/* Recursively expand calls to _serial_putc for every byte
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* passed to us. Append a newline when we're all done.
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*/
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.macro _serial_early_putc byte:req morebytes:vararg
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#ifdef CONFIG_DEBUG_EARLY_SERIAL
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R0 = \byte;
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call _serial_putc;
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.ifnb \morebytes
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_serial_early_putc \morebytes
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.else
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.if (\byte != '\n')
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_serial_early_putc '\n'
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.endif
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.endif
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#endif
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.endm
|
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|
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/* Wrapper around recurisve _serial_early_putc macro which
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* simply prepends the string "Early: "
|
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*/
|
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.macro serial_early_putc byte:req morebytes:vararg
|
||||
#ifdef CONFIG_DEBUG_EARLY_SERIAL
|
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_serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes
|
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#endif
|
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.endm
|
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|
||||
/* Since we embed the string right into our .text section, we need
|
||||
* to find its address. We do this by getting our PC and adding 2
|
||||
* bytes (which is the length of the jump instruction). Then we
|
||||
|
|
|
|||
|
|
@ -60,4 +60,13 @@ static inline const char *get_bfin_boot_mode(int bfin_boot)
|
|||
}
|
||||
#endif
|
||||
|
||||
/* Define the default SPI CS used when booting out of SPI */
|
||||
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
|
||||
defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
|
||||
defined(__ADSPBF51x__)
|
||||
# define BFIN_BOOT_SPI_SSEL 2
|
||||
#else
|
||||
# define BFIN_BOOT_SPI_SSEL 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,82 +7,154 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
|
||||
* - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
|
||||
* - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
|
||||
# define ANOMALY_BF526 1
|
||||
#else
|
||||
# define ANOMALY_BF526 0
|
||||
#endif
|
||||
#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
|
||||
# define ANOMALY_BF527 1
|
||||
#else
|
||||
# define ANOMALY_BF527 0
|
||||
#endif
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
#define ANOMALY_05000328 (1)
|
||||
#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
|
||||
#define ANOMALY_05000337 (1)
|
||||
#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
|
||||
#define ANOMALY_05000341 (1)
|
||||
#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
|
||||
#define ANOMALY_05000342 (1)
|
||||
#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* USB Calibration Value Is Not Initialized */
|
||||
#define ANOMALY_05000346 (1)
|
||||
#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* USB Calibration Value to use */
|
||||
#define ANOMALY_05000346_value 0xE510
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (1)
|
||||
#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Security Features Are Not Functional */
|
||||
#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
|
||||
#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
#define ANOMALY_05000353 (ANOMALY_BF526)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (1)
|
||||
#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Incorrect Revision Number in DSPID Register */
|
||||
#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
|
||||
#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* New Feature: Higher Default CCLK Rate */
|
||||
#define ANOMALY_05000368 (1)
|
||||
/* Incorrect Default CSEL Value in PLL_DIV */
|
||||
#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Authentication Fails To Initiate */
|
||||
#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
|
||||
#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Data Read From L3 Memory by USB DMA May be Corrupted */
|
||||
#define ANOMALY_05000380 (1)
|
||||
/* USB Full-speed Mode not Fully Tested */
|
||||
#define ANOMALY_05000381 (1)
|
||||
/* New Feature: Boot from OTP Memory */
|
||||
#define ANOMALY_05000385 (1)
|
||||
/* New Feature: bfrom_SysControl() Routine */
|
||||
#define ANOMALY_05000386 (1)
|
||||
/* New Feature: Programmable Preboot Settings */
|
||||
#define ANOMALY_05000387 (1)
|
||||
#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
|
||||
/* Host Must Not Read Back During Host DMA Boot */
|
||||
#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Boot from OTP Memory Not Functional */
|
||||
#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Routine Not Functional */
|
||||
#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Programmable Preboot Settings Not Functional */
|
||||
#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* CRC32 Checksum Support Not Functional */
|
||||
#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
|
||||
/* Reset Vector Must Not Be in SDRAM Memory Space */
|
||||
#define ANOMALY_05000389 (1)
|
||||
/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (1)
|
||||
/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (1)
|
||||
/* New Feature: Log Buffer Functionality */
|
||||
#define ANOMALY_05000394 (1)
|
||||
/* New Feature: Hook Routine Functionality */
|
||||
#define ANOMALY_05000395 (1)
|
||||
/* New Feature: Header Indirect Bit */
|
||||
#define ANOMALY_05000396 (1)
|
||||
/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
|
||||
#define ANOMALY_05000397 (1)
|
||||
/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
|
||||
#define ANOMALY_05000398 (1)
|
||||
/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
|
||||
#define ANOMALY_05000399 (1)
|
||||
#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Log Buffer Not Functional */
|
||||
#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Hook Routine Not Functional */
|
||||
#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Header Indirect Bit Not Functional */
|
||||
#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
|
||||
#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
|
||||
#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
|
||||
#define ANOMALY_05000401 (1)
|
||||
#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* Incorrect Default Internal Voltage Regulator Setting */
|
||||
#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* DEB2_URGENT Bit Not Functional */
|
||||
#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
|
||||
#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
|
||||
#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
|
||||
/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
|
||||
#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
|
||||
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
|
||||
#define ANOMALY_05000421 (1)
|
||||
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
|
||||
#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
|
||||
/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
|
||||
#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
|
||||
/* Internal Voltage Regulator Not Trimmed */
|
||||
#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
|
||||
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
|
||||
#define ANOMALY_05000432 (ANOMALY_BF526)
|
||||
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
|
||||
#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
|
@ -95,10 +167,12 @@
|
|||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
|
||||
* - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -97,11 +97,11 @@
|
|||
/* UART STB Bit Incorrectly Affects Receiver Setting */
|
||||
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
|
||||
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
|
||||
#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
|
||||
#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
|
||||
/* Incorrect Revision Number in DSPID Register */
|
||||
#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
|
||||
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
|
||||
#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
|
||||
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
|
||||
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
|
||||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
|
||||
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
|
|
@ -131,7 +131,7 @@
|
|||
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
|
||||
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
|
||||
#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
|
||||
|
|
@ -141,23 +141,23 @@
|
|||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* Writes to Synchronous SDRAM Memory May Be Lost */
|
||||
#define ANOMALY_05000273 (1)
|
||||
#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
|
||||
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
|
||||
#define ANOMALY_05000276 (1)
|
||||
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
|
||||
#define ANOMALY_05000277 (1)
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (1)
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
|
||||
/* False Hardware Error Exception When ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (1)
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (1)
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
|
||||
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (1)
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (1)
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (1)
|
||||
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
|
||||
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
|
||||
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
|
||||
|
|
@ -169,30 +169,37 @@
|
|||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
|
||||
#define ANOMALY_05000311 (1)
|
||||
#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
|
||||
/* PPI Is Level-Sensitive on First Transfer */
|
||||
#define ANOMALY_05000313 (1)
|
||||
#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
|
||||
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
|
||||
#define ANOMALY_05000315 (1)
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
|
||||
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
|
||||
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
|
||||
#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
|
||||
/* PPI Does Not Start Properly In Specific Mode */
|
||||
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
|
||||
#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
|
|
@ -271,5 +278,9 @@
|
|||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -148,6 +148,14 @@
|
|||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
|
@ -160,5 +168,9 @@
|
|||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
/* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
|
||||
/* External FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
|
|
@ -61,6 +61,8 @@
|
|||
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value Is Not Intialized */
|
||||
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value to use */
|
||||
#define ANOMALY_05000346_value 0x5411
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost when Core Reads SDH Data FIFO */
|
||||
|
|
@ -68,7 +70,7 @@
|
|||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
|
|
@ -86,13 +88,13 @@
|
|||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* Mobile DDR Operation Not Functional */
|
||||
#define ANOMALY_05000377 (1)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (1)
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
|
|
@ -126,25 +128,37 @@
|
|||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (1)
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (1)
|
||||
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (1)
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (1)
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (1)
|
||||
/* FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000412 (1)
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (1)
|
||||
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (1)
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
||||
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
|
@ -161,5 +175,8 @@
|
|||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
* - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -264,6 +264,18 @@
|
|||
#define ANOMALY_05000371 (1)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
|
||||
#define ANOMALY_05000412 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
|
||||
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000158 (0)
|
||||
|
|
@ -271,5 +283,8 @@
|
|||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue