mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
pico-imx7d: add baseboard SD card boot detect
Technexion PICO-IMX7 SoM is supporting USDHC3 (eMMC or micro SD on SoM) and USDHC1 (SD on carrier board) to use on any carrier board like PICO-NYMPH. Based on the U-Boot version from Technexion it adds baseboard SD card boot detect to able to boot from selected USDHC1 or USDHC3 boot devices. Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu> Tested-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
parent
04bb59b408
commit
03622f3012
5 changed files with 151 additions and 9 deletions
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@ -3,6 +3,7 @@
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/{
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc1;
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usb0 = &usbotg1;
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display0 = &lcdif;
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};
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@ -1,4 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2017 NXP Semiconductors
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obj-y := pico-imx7d.o spl.o
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obj-y := pico-imx7d.o spl.o ../../freescale/common/mmc.o
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@ -13,6 +13,7 @@
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <common.h>
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#include <miiphy.h>
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@ -25,6 +26,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define PICO_MMC0 0
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#define PICO_MMC0_BLK 2
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#define PICO_MMC1 1
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#define PICO_MMC1_BLK 0
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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@ -150,6 +156,12 @@ int board_late_init(void)
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set_wdog_reset(wdog);
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#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
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#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
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board_late_mmc_env_init();
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#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */
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#endif
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/*
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* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
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* since we use PMIC_PWRON to reset the board.
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@ -184,3 +196,53 @@ int board_ehci_hcd_init(int port)
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}
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return 0;
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}
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#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
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#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
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int board_mmc_get_env_dev(int devno)
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{
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int dev_env = 0;
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switch (get_boot_device()) {
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case SD3_BOOT:
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case MMC3_BOOT:
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env_set("bootdev", "MMC3");
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dev_env = PICO_MMC0;
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break;
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case SD1_BOOT:
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env_set("bootdev", "SD1");
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dev_env = PICO_MMC1;
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break;
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default:
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printf("Wrong boot device!");
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}
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return dev_env;
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}
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int mmc_map_to_kernel_blk(int dev_no)
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{
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int blk_no = 0;
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switch (dev_no) {
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case PICO_MMC0:
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blk_no = PICO_MMC0_BLK;
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break;
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case PICO_MMC1:
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blk_no = PICO_MMC1_BLK;
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break;
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default:
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printf("Invalid MMC device!");
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}
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return blk_no;
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}
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#endif
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#if CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
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int mmc_get_env_dev(void)
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{
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return board_mmc_get_env_dev(0);
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}
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#endif
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#endif /* CONFIG_FSL_ESDHC_IMX */
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@ -15,6 +15,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-mx7/mx7-ddr.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/gpio.h>
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#include <asm/sections.h>
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#include <fsl_esdhc_imx.h>
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@ -159,7 +160,20 @@ void reset_cpu(void)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
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/* EMMC/SD */
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static const iomux_v3_cfg_t usdhc1_pads[] = {
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
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static const iomux_v3_cfg_t usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -173,20 +187,83 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC3_BASE_ADDR},
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{USDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* Assume uSDHC3 emmc is always present */
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return 1;
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(struct bd_info *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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int ret;
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u32 index;
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/*
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* Following map is done:
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* (USDHC) (Physical Port)
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* usdhc3 SOM MicroSD/MMC
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* usdhc1 Carrier board MicroSD
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* Always set boot USDHC as mmc0
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*/
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imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
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ARRAY_SIZE(usdhc3_emmc_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
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ARRAY_SIZE(usdhc1_pads));
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gpio_direction_input(USDHC1_CD_GPIO);
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switch (get_boot_device()) {
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case SD1_BOOT:
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usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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case MMC3_BOOT:
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 8;
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usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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case SD3_BOOT:
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default:
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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}
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for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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@ -13,7 +13,7 @@
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#define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR
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/* MMC Config */
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
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#define CFG_DFU_ENV_SETTINGS \
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"dfu_alt_info=" \
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"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
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"fastboot_partition_alias_system=rootfs\0" \
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"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
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"mmcautodetect=yes\0" \
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PICO_BOOT_ENV
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(PXE, pxe, na) \
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