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Merge branch 'master' of git://git.denx.de/u-boot-spi

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This commit is contained in:
Tom Rini 2017-01-15 13:33:30 -05:00
commit 035ebf85b0
8 changed files with 0 additions and 757 deletions
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12
arch/m68k/cpu/mcf52x2/cpu_init.c
View file

@ -318,18 +318,6 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
#endif /* CONFIG_CMD_NET */
#if defined(CONFIG_CF_QSPI)
/* Configure PIOs for SIN, SOUT, and SCK */
void cfspi_port_conf(void)
{
mbar_writeByte(MCF_GPIO_PAR_QSPI,
MCF_GPIO_PAR_QSPI_SIN_SIN |
MCF_GPIO_PAR_QSPI_SOUT_SOUT |
MCF_GPIO_PAR_QSPI_SCK_SCK);
}
#endif /* CONFIG_CF_QSPI */
#endif /* CONFIG_M5271 */
#if defined(CONFIG_M5272)

98
board/cirrus/edb93xx/edb93xx.c
View file

@ -282,101 +282,3 @@ int dram_init(void)
gd->ram_size = dram_init_banksize_int(1);
return 0;
}
#ifdef CONFIG_EP93XX_SPI
#include <spi.h>
/*
* EGIO0-EGIPO7 -> port A
* EGIO8-EGIP15 -> port B
*/
static void ep93xx_set_epgio(unsigned num)
{
struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
if (num < 8)
writel(readl(&regs->padr) | (1<<num), &regs->padr);
else
writel(readl(&regs->pbdr) | (1<<(num-8)), &regs->pbdr);
}
static void ep93xx_clear_epgio(unsigned num)
{
struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
if (num < 8)
writel(readl(&regs->padr) & (~(1<<num)), &regs->padr);
else
writel(readl(&regs->pbdr) & (~(1<<(num-8))), &regs->pbdr);
}
static void ep93xx_dir_epgio_out(unsigned num)
{
struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
if (num < 8)
writel(readl(&regs->paddr) | (1<<num), &regs->paddr);
else
writel(readl(&regs->pbddr) | (1<<(num-8)), &regs->pbddr);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (bus == 0 && cs < 16)
return 1;
return 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
ep93xx_clear_epgio(slave->cs);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
ep93xx_set_epgio(slave->cs);
}
#ifdef CONFIG_MMC_SPI
#include <mmc.h>
#ifndef CONFIG_MMC_SPI_CS_EPGIO
# define CONFIG_MMC_SPI_CS_EPGIO 4
#endif
#ifndef CONFIG_MMC_SPI_SPEED
# define CONFIG_MMC_SPI_SPEED 25000000
#endif
#ifndef CONFIG_MMC_SPI_MODE
# define CONFIG_MMC_SPI_MODE SPI_MODE_0
#endif
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
#ifdef CONFIG_MMC_SPI_POWER_EGPIO
ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
#endif
struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
if (!mmc) {
printf("Failed to create MMC Device\n");
return 1;
}
mmc_init(mmc);
return 0;
}
#endif /* CONFIG_MMC_SPI */
#endif /* CONFIG_EP93XX_SPI */

2
drivers/spi/Makefile
View file

@ -23,10 +23,8 @@ obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o

354
drivers/spi/cf_qspi.c
View file

@ -1,354 +0,0 @@
/*
* Freescale Coldfire Queued SPI driver
*
* NOTE:
* This driver is written to transfer 8 bit at-a-time and uses the dedicated
* SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
*
* Copyright (C) 2011 Ruggedcom, Inc.
* Richard Retanubun (richardretanubun@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
struct cf_qspi_slave {
struct spi_slave slave; /* Specific bus:cs ID for each device */
qspi_t *regs; /* Pointer to SPI controller registers */
u16 qmr; /* QMR: Queued Mode Register */
u16 qwr; /* QWR: Queued Wrap Register */
u16 qcr; /* QCR: Queued Command Ram */
};
/* Register write wrapper functions */
static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; }
static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; }
static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; }
static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; }
static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; }
/* Register read wrapper functions */
static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; }
static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; }
static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; }
/* These call points may be different for each ColdFire CPU */
extern void cfspi_port_conf(void);
static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
__attribute__((weak))
void spi_init(void)
{
cfspi_port_conf();
}
__attribute__((weak))
void spi_cs_activate(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
}
__attribute__((weak))
void spi_cs_deactivate(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
}
__attribute__((weak))
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Only 1 bus and 4 chipselect per controller */
if (bus == 0 && (cs >= 0 && cs < 4))
return 1;
else
return 0;
}
void spi_free_slave(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
free(dev);
}
/* Translate information given by spi_setup_slave to members of cf_qspi_slave */
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct cf_qspi_slave *dev = NULL;
if (!spi_cs_is_valid(bus, cs))
return NULL;
dev = spi_alloc_slave(struct cf_qspi_slave, bus, cs);
if (!dev)
return NULL;
/* Initialize to known value */
dev->regs = (qspi_t *)MMAP_QSPI;
dev->qmr = 0;
dev->qwr = 0;
dev->qcr = 0;
/* Map max_hz to QMR[BAUD] */
if (max_hz == 0) /* Go as fast as possible */
dev->qmr = 2u;
else /* Get the closest baud rate */
dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
2lu, 255lu);
/* Map mode to QMR[CPOL] and QMR[CPHA] */
if (mode & SPI_CPOL)
dev->qmr |= QSPI_QMR_CPOL;
if (mode & SPI_CPHA)
dev->qmr |= QSPI_QMR_CPHA;
/* Hardcode bit length to 8 bit per transter */
dev->qmr |= QSPI_QMR_BITS_8;
/* Set QMR[MSTR] to enable QSPI as master */
dev->qmr |= QSPI_QMR_MSTR;
/*
* Set QCR and QWR to default values for spi flash operation.
* If more custom QCR and QRW are needed, overload mode variable
*/
dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE);
if (!(mode & SPI_CS_HIGH))
dev->qwr |= QSPI_QWR_CSIV;
return &dev->slave;
}
/* Transfer 8 bit at a time */
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
volatile qspi_t *qspi = dev->regs;
u8 *txbuf = (u8 *)dout;
u8 *rxbuf = (u8 *)din;
u32 count = DIV_ROUND_UP(bitlen, 8);
u32 n, i = 0;
/* Sanitize arguments */
if (slave == NULL) {
printf("%s: NULL slave ptr\n", __func__);
return -1;
}
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
/* There is something to send, lets process it. spi_xfer is also called
* just to toggle chip select, so bitlen of 0 is valid */
if (count > 0) {
/*
* NOTE: Since chip select is driven as a bit-bang-ed GPIO
* using spi_cs_activate() and spi_cs_deactivate(),
* the chip select settings inside the controller
* (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to
* keep the controller settings consistent with the actual
* operation of the bus.
*/
/* Write the slave device's settings for the controller.*/
write_qmr(qspi, dev->qmr);
write_qwr(qspi, dev->qwr);
/* Limit transfer to 16 at a time */
n = min(count, 16u);
do {
/* Setup queue end point */
write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK)
| QSPI_QWR_ENDQP((n-1))));
/* Write Command RAM */
write_qar(qspi, QSPI_QAR_CMD);
for (i = 0; i < n; ++i)
write_qdr(qspi, dev->qcr);
/* Write TxBuf, if none given, fill with ZEROes */
write_qar(qspi, QSPI_QAR_TRANS);
if (txbuf) {
for (i = 0; i < n; ++i)
write_qdr(qspi, *txbuf++);
} else {
for (i = 0; i < n; ++i)
write_qdr(qspi, 0);
}
/* Clear QIR[SPIF] by writing a 1 to it */
write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF);
/* Set QDLYR[SPE] to start sending */
write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE);
/* Poll QIR[SPIF] for transfer completion */
while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1)
udelay(1);
/* If given read RxBuf, load data to it */
if (rxbuf) {
write_qar(qspi, QSPI_QAR_RECV);
for (i = 0; i < n; ++i)
*rxbuf++ = read_qdr(qspi);
}
/* Decrement count */
count -= n;
} while (count);
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
return 0;
}
/* Each MCF CPU may have different pin assignments for chip selects. */
#if defined(CONFIG_M5271)
/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
{
debug("%s: bus %d cs %d cs_active_high %d\n",
__func__, bus, cs, cs_active_high);
switch (cs) {
case 0: /* QSPI_CS[0] = PQSPI[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
else
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
break;
case 1: /* QSPI_CS[1] = PQSPI[4] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
else
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
break;
case 2: /* QSPI_CS[2] = PTIMER[7] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
else
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
break;
case 3: /* QSPI_CS[3] = PTIMER[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
else
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
break;
}
}
/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
* direction set as IN to undrive the pin, external pullup/pulldown will bring
* bus to deassert state.
*/
void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
{
debug("%s: bus %d cs %d cs_active_high %d\n",
__func__, bus, cs, cs_active_high);
switch (cs) {
case 0: /* QSPI_CS[0] = PQSPI[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
else
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
break;
case 1: /* QSPI_CS[1] = PQSPI[4] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
else
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
break;
case 2: /* QSPI_CS[2] = PTIMER[7] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
else
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
break;
case 3: /* QSPI_CS[3] = PTIMER[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
else
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
break;
}
}
#endif /* CONFIG_M5271 */

4
drivers/spi/cf_spi.c
View file

@ -279,10 +279,6 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
}
#endif /* CONFIG_CF_DSPI */
#ifdef CONFIG_CF_QSPI
/* 52xx, 53xx */
#endif /* CONFIG_CF_QSPI */
#ifdef CONFIG_CMD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{

272
drivers/spi/ep93xx_spi.c
View file

@ -1,272 +0,0 @@
/*
* SPI Driver for EP93xx
*
* Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Inspired form linux kernel driver and atmel uboot driver
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/ep93xx.h>
#define SSPBASE SPI_BASE
#define SSPCR0 0x0000
#define SSPCR0_MODE_SHIFT 6
#define SSPCR0_SCR_SHIFT 8
#define SSPCR0_SPH BIT(7)
#define SSPCR0_SPO BIT(6)
#define SSPCR0_FRF_SPI 0
#define SSPCR0_DSS_8BIT 7
#define SSPCR1 0x0004
#define SSPCR1_RIE BIT(0)
#define SSPCR1_TIE BIT(1)
#define SSPCR1_RORIE BIT(2)
#define SSPCR1_LBM BIT(3)
#define SSPCR1_SSE BIT(4)
#define SSPCR1_MS BIT(5)
#define SSPCR1_SOD BIT(6)
#define SSPDR 0x0008
#define SSPSR 0x000c
#define SSPSR_TFE BIT(0)
#define SSPSR_TNF BIT(1)
#define SSPSR_RNE BIT(2)
#define SSPSR_RFF BIT(3)
#define SSPSR_BSY BIT(4)
#define SSPCPSR 0x0010
#define SSPIIR 0x0014
#define SSPIIR_RIS BIT(0)
#define SSPIIR_TIS BIT(1)
#define SSPIIR_RORIS BIT(2)
#define SSPICR SSPIIR
#define SSPCLOCK 14745600
#define SSP_MAX_RATE (SSPCLOCK / 2)
#define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
/* timeout in milliseconds */
#define SPI_TIMEOUT 5
/* maximum depth of RX/TX FIFO */
#define SPI_FIFO_SIZE 8
struct ep93xx_spi_slave {
struct spi_slave slave;
unsigned sspcr0;
unsigned sspcpsr;
};
static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
{
return container_of(slave, struct ep93xx_spi_slave, slave);
}
void spi_init()
{
}
static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
{
writel(value, (unsigned int *)(SSPBASE + reg));
}
static inline u8 ep93xx_spi_read_u8(u16 reg)
{
return readl((unsigned int *)(SSPBASE + reg));
}
static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
{
writel(value, (unsigned int *)(SSPBASE + reg));
}
static inline u16 ep93xx_spi_read_u16(u16 reg)
{
return (u16)readl((unsigned int *)(SSPBASE + reg));
}
static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
struct ep93xx_spi_slave *slave)
{
unsigned cpsr, scr;
if (rate > SSP_MAX_RATE)
rate = SSP_MAX_RATE;
if (rate < SSP_MIN_RATE)
return -1;
/* Calculate divisors so that we can get speed according the
* following formula:
* rate = spi_clock_rate / (cpsr * (1 + scr))
*
* cpsr must be even number and starts from 2, scr can be any number
* between 0 and 255.
*/
for (cpsr = 2; cpsr <= 254; cpsr += 2) {
for (scr = 0; scr <= 255; scr++) {
if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
/* Set CHPA and CPOL, SPI format and 8bit */
unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
if (mode & SPI_CPHA)
sspcr0 |= SSPCR0_SPH;
if (mode & SPI_CPOL)
sspcr0 |= SSPCR0_SPO;
slave->sspcr0 = sspcr0;
slave->sspcpsr = cpsr;
return 0;
}
}
}
return -1;
}
void spi_set_speed(struct spi_slave *slave, unsigned int hz)
{
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
unsigned int mode = 0;
if (as->sspcr0 & SSPCR0_SPH)
mode |= SPI_CPHA;
if (as->sspcr0 & SSPCR0_SPO)
mode |= SPI_CPOL;
ep93xx_spi_init_hw(hz, mode, as);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct ep93xx_spi_slave *as;
if (!spi_cs_is_valid(bus, cs))
return NULL;
as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
if (!as)
return NULL;
if (ep93xx_spi_init_hw(max_hz, mode, as)) {
free(as);
return NULL;
}
return &as->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
free(as);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
/* Enable the SPI hardware */
ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
slave->cs, as->sspcpsr, as->sspcr0);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
/* Disable the SPI hardware */
ep93xx_spi_write_u8(SSPCR1, 0);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
unsigned int len_tx;
unsigned int len_rx;
unsigned int len;
u32 status;
const u8 *txp = dout;
u8 *rxp = din;
u8 value;
debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;
if (bitlen % 8) {
/* Errors always terminate an ongoing transfer */
flags |= SPI_XFER_END;
goto out;
}
len = bitlen / 8;
if (flags & SPI_XFER_BEGIN) {
/* Empty RX FIFO */
while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
ep93xx_spi_read_u8(SSPDR);
spi_cs_activate(slave);
}
for (len_tx = 0, len_rx = 0; len_rx < len; ) {
status = ep93xx_spi_read_u8(SSPSR);
if ((len_tx < len) && (status & SSPSR_TNF)) {
if (txp)
value = *txp++;
else
value = 0xff;
ep93xx_spi_write_u8(SSPDR, value);
len_tx++;
}
if (status & SSPSR_RNE) {
value = ep93xx_spi_read_u8(SSPDR);
if (rxp)
*rxp++ = value;
len_rx++;
}
}
out:
if (flags & SPI_XFER_END) {
/*
* Wait until the transfer is completely done before
* we deactivate CS.
*/
do {
status = ep93xx_spi_read_u8(SSPSR);
} while (status & SSPSR_BSY);
spi_cs_deactivate(slave);
}
return 0;
}

10
include/configs/edb93xx.h
View file

@ -229,16 +229,6 @@
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/* Define to enable MMC on SPI support */
/* #define CONFIG_EP93XX_SPI_MMC */
#ifdef CONFIG_EP93XX_SPI_MMC
#define CONFIG_EP93XX_SPI
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
#endif
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_OHCI_EP93XX
#define CONFIG_SYS_USB_OHCI_CPU_INIT

5
scripts/config_whitelist.txt
View file

@ -440,7 +440,6 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
CONFIG_CF_ATASEL_DIS
CONFIG_CF_ATASEL_ENA
CONFIG_CF_DSPI
CONFIG_CF_QSPI
CONFIG_CF_SBF
CONFIG_CF_SPI
CONFIG_CF_V2
@ -1037,8 +1036,6 @@ CONFIG_EP9312
CONFIG_EP9315
CONFIG_EP93XX
CONFIG_EP93XX_NO_FLASH_CFG
CONFIG_EP93XX_SPI
CONFIG_EP93XX_SPI_MMC
CONFIG_EPH_POWER_EN
CONFIG_EPOLL
CONFIG_ESBC_ADDR_64BIT
@ -1983,8 +1980,6 @@ CONFIG_MMC_SPI_CRC_ON
CONFIG_MMC_SPI_CS
CONFIG_MMC_SPI_CS_EPGIO
CONFIG_MMC_SPI_MODE
CONFIG_MMC_SPI_NPOWER_EGPIO
CONFIG_MMC_SPI_POWER_EGPIO
CONFIG_MMC_SPI_SPEED
CONFIG_MMC_SUNXI
CONFIG_MMC_SUNXI_SLOT