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ARM: am3517_evm: Fix pin muxing to enable EHCI Host in the future
This patch enables the pinmuxing to support gpio_57 for phy reset and fixes the pinmuxing for the ECHI tranceiver. The clocks don't appear to by fully enabled yet, so OMAP-EHCI on am3517 is still not yet working, but we're one step closer. Signed-off-by: Adam Ford <aford173@gmail.com>
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parent
c94703483c
commit
02acbb9472
2 changed files with 15 additions and 13 deletions
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@ -111,7 +111,7 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) \
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
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@ -339,18 +339,18 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
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/* ETK (ES2 onwards) */\
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MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
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MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
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MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
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MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
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MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
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MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
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MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
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MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
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MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
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MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
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MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
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MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
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MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
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@ -28,6 +28,8 @@
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* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
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*/
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
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#ifdef CONFIG_USB_MUSB_AM35X
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#ifdef CONFIG_USB_MUSB_HOST
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