diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 1f95fba8cd..d36fcccafe 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -61,7 +61,7 @@ static inline u32 __get_sys_clk_index(void)
 		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
 	else {
 		/* SYS_CLKSEL - 1 to match the dpll param array indices */
-		ind = (readl(&prcm->cm_sys_clksel) &
+		ind = (readl((*prcm)->cm_sys_clksel) &
 			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
 	}
 	return ind;
@@ -76,7 +76,7 @@ u32 get_sys_clk_freq(void)
 	return sys_clk_array[index];
 }
 
-static inline void do_bypass_dpll(u32 *const base)
+static inline void do_bypass_dpll(u32 const base)
 {
 	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
 
@@ -86,17 +86,17 @@ static inline void do_bypass_dpll(u32 *const base)
 			CM_CLKMODE_DPLL_EN_SHIFT);
 }
 
-static inline void wait_for_bypass(u32 *const base)
+static inline void wait_for_bypass(u32 const base)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
 	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
 				LDELAY)) {
-		printf("Bypassing DPLL failed %p\n", base);
+		printf("Bypassing DPLL failed %x\n", base);
 	}
 }
 
-static inline void do_lock_dpll(u32 *const base)
+static inline void do_lock_dpll(u32 const base)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
@@ -105,18 +105,18 @@ static inline void do_lock_dpll(u32 *const base)
 		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
 }
 
-static inline void wait_for_lock(u32 *const base)
+static inline void wait_for_lock(u32 const base)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
 	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
 		&dpll_regs->cm_idlest_dpll, LDELAY)) {
-		printf("DPLL locking failed for %p\n", base);
+		printf("DPLL locking failed for %x\n", base);
 		hang();
 	}
 }
 
-inline u32 check_for_lock(u32 *const base)
+inline u32 check_for_lock(u32 const base)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 	u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
@@ -124,7 +124,7 @@ inline u32 check_for_lock(u32 *const base)
 	return lock;
 }
 
-static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 				u8 lock, char *dpll)
 {
 	u32 temp, M, N;
@@ -236,24 +236,24 @@ void configure_mpu_dpll(void)
 	 */
 	if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
 		mpu_dpll_regs =
-			(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
-		bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
-		clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
+		bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
+		clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
 			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
-		setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+		setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
 			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
 		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
 			CM_CLKSEL_DCC_EN_MASK);
 	}
 
-	setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+	setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
 		MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
-	setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+	setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
 		MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
 
 	params = get_mpu_dpll_params();
 
-	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
 	debug("MPU DPLL locked\n");
 }
 
@@ -277,12 +277,12 @@ static void setup_usb_dpll(void)
 	den = (params->n + 1) * 250 * 1000;
 	num += den - 1;
 	sd_div = num / den;
-	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+	clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
 			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
 			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
 
 	/* Now setup the dpll with the regular function */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
 }
 #endif
 
@@ -301,21 +301,21 @@ static void setup_dplls(void)
 	 * using the FREQ_UPDATE method(freq_update_core())
 	 */
 	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
-		do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
 							DPLL_NO_LOCK, "core");
 	else
-		do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
 							DPLL_LOCK, "core");
 	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
 	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
 	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
 	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
-	writel(temp, &prcm->cm_clksel_core);
+	writel(temp, (*prcm)->cm_clksel_core);
 	debug("Core DPLL configured\n");
 
 	/* lock PER dpll */
 	params = get_per_dpll_params();
-	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
 			params, DPLL_LOCK, "per");
 	debug("PER DPLL locked\n");
 
@@ -334,11 +334,11 @@ static void setup_non_essential_dplls(void)
 	const struct dpll_params *params;
 
 	/* IVA */
-	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+	clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
 		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
 
 	params = get_iva_dpll_params();
-	do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
 
 	/* Configure ABE dpll */
 	params = get_abe_dpll_params();
@@ -350,23 +350,23 @@ static void setup_non_essential_dplls(void)
 	 * We need to enable some additional options to achieve
 	 * 196.608MHz from 32768 Hz
 	 */
-	setbits_le32(&prcm->cm_clkmode_dpll_abe,
+	setbits_le32((*prcm)->cm_clkmode_dpll_abe,
 			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
 			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
 			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
 			CM_CLKMODE_DPLL_REGM4XEN_MASK);
 	/* Spend 4 REFCLK cycles at each stage */
-	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+	clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
 			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
 			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
 #endif
 
 	/* Select the right reference clk */
-	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+	clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
 			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
 			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
 	/* Lock the dpll */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
 }
 #endif
 
@@ -417,14 +417,14 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
 		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
 }
 
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
 {
 	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
 			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
-	debug("Enable clock domain - %p\n", clkctrl_reg);
+	debug("Enable clock domain - %x\n", clkctrl_reg);
 }
 
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
 {
 	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
 	u32 bound = LDELAY;
@@ -436,19 +436,19 @@ static inline void wait_for_clk_enable(u32 *clkctrl_addr)
 		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
 			 MODULE_CLKCTRL_IDLEST_SHIFT;
 		if (--bound == 0) {
-			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			printf("Clock enable failed for 0x%x idlest 0x%x\n",
 				clkctrl_addr, clkctrl);
 			return;
 		}
 	}
 }
 
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
 				u32 wait_for_enable)
 {
 	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
 			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
-	debug("Enable clock module - %p\n", clkctrl_addr);
+	debug("Enable clock module - %x\n", clkctrl_addr);
 	if (wait_for_enable)
 		wait_for_clk_enable(clkctrl_addr);
 }
@@ -461,10 +461,10 @@ void freq_update_core(void)
 
 	core_dpll_params = get_core_dpll_params();
 	/* Put EMIF clock domain in sw wakeup mode */
-	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+	enable_clock_domain((*prcm)->cm_memif_clkstctrl,
 				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
-	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+	wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
 
 	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
 	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
@@ -476,9 +476,9 @@ void freq_update_core(void)
 			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
 			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
 
-	writel(freq_config1, &prcm->cm_shadow_freq_config1);
+	writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
 	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
-				&prcm->cm_shadow_freq_config1, LDELAY)) {
+			(u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
 		puts("FREQ UPDATE procedure failed!!");
 		hang();
 	}
@@ -490,20 +490,20 @@ void freq_update_core(void)
 	 */
 	if (omap_rev != OMAP5430_ES1_0) {
 		/* Put EMIF clock domain back in hw auto mode */
-		enable_clock_domain(&prcm->cm_memif_clkstctrl,
+		enable_clock_domain((*prcm)->cm_memif_clkstctrl,
 					CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-		wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-		wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+		wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+		wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
 	}
 }
 
-void bypass_dpll(u32 *const base)
+void bypass_dpll(u32 const base)
 {
 	do_bypass_dpll(base);
 	wait_for_bypass(base);
 }
 
-void lock_dpll(u32 *const base)
+void lock_dpll(u32 const base)
 {
 	do_lock_dpll(base);
 	wait_for_lock(base);
@@ -512,39 +512,39 @@ void lock_dpll(u32 *const base)
 void setup_clocks_for_console(void)
 {
 	/* Do not add any spl_debug prints in this function */
-	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 			CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
 	/* Enable all UARTs - console will be on one of them */
-	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+	clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
-	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+	clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
-	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+	clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
-	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+	clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
-	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
 			CD_CLKCTRL_CLKTRCTRL_SHIFT);
 }
 
-void do_enable_clocks(u32 *const *clk_domains,
-			    u32 *const *clk_modules_hw_auto,
-			    u32 *const *clk_modules_explicit_en,
+void do_enable_clocks(u32 const *clk_domains,
+			    u32 const *clk_modules_hw_auto,
+			    u32 const *clk_modules_explicit_en,
 			    u8 wait_for_enable)
 {
 	u32 i, max = 100;
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 8864abc16e..bb37cf314a 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1289,9 +1289,9 @@ void sdram_init(void)
 
 	if (!(in_sdram || warm_reset())) {
 		if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
-			bypass_dpll(&prcm->cm_clkmode_dpll_core);
+			bypass_dpll((*prcm)->cm_clkmode_dpll_core);
 		else
-			writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+			writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
 	}
 
 	if (!in_sdram)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 9ef10bdf2d..fff89da571 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -32,6 +32,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/emif.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -116,6 +117,8 @@ void spl_display_print(void)
 void s_init(void)
 {
 	init_omap_revision();
+	hw_data_init();
+
 #ifdef CONFIG_SPL_BUILD
 	if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
 		force_emif_self_refresh();
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c
index a045b77180..e6e5f7893c 100644
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -81,13 +81,13 @@ void omap_vc_init(u16 speed_khz)
 	cycles_low -= 7;
 	val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
 	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
-	writel(val, &prcm->prm_vc_cfg_i2c_clk);
+	writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
 
 	val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
 		PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
 	/* No HS mode for now */
 	val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
-	writel(val, &prcm->prm_vc_cfg_i2c_mode);
+	writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
 }
 
 /**
@@ -113,14 +113,15 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
 	reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
 	    reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
 	    reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
-	writel(reg_val, &prcm->prm_vc_val_bypass);
+	writel(reg_val, (*prcm)->prm_vc_val_bypass);
 
 	/* Signal VC to send data */
-	writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
+	writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
+				(*prcm)->prm_vc_val_bypass);
 
 	/* Wait on VC to complete transmission */
 	do {
-		reg_val = readl(&prcm->prm_vc_val_bypass) &
+		reg_val = readl((*prcm)->prm_vc_val_bypass) &
 				PRM_VC_VAL_BYPASS_VALID_BIT;
 		if (!reg_val)
 			break;
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 83160a28f3..0365148958 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -29,6 +29,8 @@ COBJS	+= sdram_elpida.o
 COBJS	+= hwinit.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
+COBJS	+= prcm-regs.o
+COBJS	+= hw_data.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 12c58033d2..9acceb0d45 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -46,8 +46,6 @@
 #define puts(s)
 #endif /* !CONFIG_SPL_BUILD */
 
-struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-
 const u32 sys_clk_array[8] = {
 	12000000,	       /* 12 MHz */
 	13000000,	       /* 13 MHz */
@@ -176,7 +174,7 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
 };
 
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
@@ -345,54 +343,54 @@ u32 get_offset_code(u32 offset)
  */
 void enable_basic_clocks(void)
 {
-	u32 *const clk_domains_essential[] = {
-		&prcm->cm_l4per_clkstctrl,
-		&prcm->cm_l3init_clkstctrl,
-		&prcm->cm_memif_clkstctrl,
-		&prcm->cm_l4cfg_clkstctrl,
+	u32 const clk_domains_essential[] = {
+		(*prcm)->cm_l4per_clkstctrl,
+		(*prcm)->cm_l3init_clkstctrl,
+		(*prcm)->cm_memif_clkstctrl,
+		(*prcm)->cm_l4cfg_clkstctrl,
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_essential[] = {
-		&prcm->cm_l3_2_gpmc_clkctrl,
-		&prcm->cm_memif_emif_1_clkctrl,
-		&prcm->cm_memif_emif_2_clkctrl,
-		&prcm->cm_l4cfg_l4_cfg_clkctrl,
-		&prcm->cm_wkup_gpio1_clkctrl,
-		&prcm->cm_l4per_gpio2_clkctrl,
-		&prcm->cm_l4per_gpio3_clkctrl,
-		&prcm->cm_l4per_gpio4_clkctrl,
-		&prcm->cm_l4per_gpio5_clkctrl,
-		&prcm->cm_l4per_gpio6_clkctrl,
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3_2_gpmc_clkctrl,
+		(*prcm)->cm_memif_emif_1_clkctrl,
+		(*prcm)->cm_memif_emif_2_clkctrl,
+		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+		(*prcm)->cm_wkup_gpio1_clkctrl,
+		(*prcm)->cm_l4per_gpio2_clkctrl,
+		(*prcm)->cm_l4per_gpio3_clkctrl,
+		(*prcm)->cm_l4per_gpio4_clkctrl,
+		(*prcm)->cm_l4per_gpio5_clkctrl,
+		(*prcm)->cm_l4per_gpio6_clkctrl,
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_essential[] = {
-		&prcm->cm_wkup_gptimer1_clkctrl,
-		&prcm->cm_l3init_hsmmc1_clkctrl,
-		&prcm->cm_l3init_hsmmc2_clkctrl,
-		&prcm->cm_l4per_gptimer2_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_l4per_uart3_clkctrl,
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_wkup_gptimer1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc2_clkctrl,
+		(*prcm)->cm_l4per_gptimer2_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_l4per_uart3_clkctrl,
 		0
 	};
 
 	/* Enable optional additional functional clock for GPIO4 */
-	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
 	/* Enable 96 MHz clock for MMC1 & MMC2 */
-	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
-	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
 	/* Select 32KHz clock as the source of GPTIMER1 */
-	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
 
 	/* Enable optional 48M functional clock for USB  PHY */
-	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
 			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
 
 	do_enable_clocks(clk_domains_essential,
@@ -403,26 +401,26 @@ void enable_basic_clocks(void)
 
 void enable_basic_uboot_clocks(void)
 {
-	u32 *const clk_domains_essential[] = {
+	u32 const clk_domains_essential[] = {
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_essential[] = {
-		&prcm->cm_l3init_hsusbotg_clkctrl,
-		&prcm->cm_l3init_usbphy_clkctrl,
-		&prcm->cm_l3init_usbphy_clkctrl,
-		&prcm->cm_clksel_usb_60mhz,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3init_hsusbotg_clkctrl,
+		(*prcm)->cm_l3init_usbphy_clkctrl,
+		(*prcm)->cm_l3init_usbphy_clkctrl,
+		(*prcm)->cm_clksel_usb_60mhz,
+		(*prcm)->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_essential[] = {
-		&prcm->cm_l4per_mcspi1_clkctrl,
-		&prcm->cm_l4per_i2c1_clkctrl,
-		&prcm->cm_l4per_i2c2_clkctrl,
-		&prcm->cm_l4per_i2c3_clkctrl,
-		&prcm->cm_l4per_i2c4_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_mcspi1_clkctrl,
+		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_i2c2_clkctrl,
+		(*prcm)->cm_l4per_i2c3_clkctrl,
+		(*prcm)->cm_l4per_i2c4_clkctrl,
+		(*prcm)->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
 
@@ -438,72 +436,72 @@ void enable_basic_uboot_clocks(void)
  */
 void enable_non_essential_clocks(void)
 {
-	u32 *const clk_domains_non_essential[] = {
-		&prcm->cm_mpu_m3_clkstctrl,
-		&prcm->cm_ivahd_clkstctrl,
-		&prcm->cm_dsp_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sgx_clkstctrl,
-		&prcm->cm1_abe_clkstctrl,
-		&prcm->cm_c2c_clkstctrl,
-		&prcm->cm_cam_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sdma_clkstctrl,
+	u32 const clk_domains_non_essential[] = {
+		(*prcm)->cm_mpu_m3_clkstctrl,
+		(*prcm)->cm_ivahd_clkstctrl,
+		(*prcm)->cm_dsp_clkstctrl,
+		(*prcm)->cm_dss_clkstctrl,
+		(*prcm)->cm_sgx_clkstctrl,
+		(*prcm)->cm1_abe_clkstctrl,
+		(*prcm)->cm_c2c_clkstctrl,
+		(*prcm)->cm_cam_clkstctrl,
+		(*prcm)->cm_dss_clkstctrl,
+		(*prcm)->cm_sdma_clkstctrl,
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_non_essential[] = {
-		&prcm->cm_l3instr_l3_3_clkctrl,
-		&prcm->cm_l3instr_l3_instr_clkctrl,
-		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
-		&prcm->cm_l3init_hsi_clkctrl,
+	u32 const clk_modules_hw_auto_non_essential[] = {
+		(*prcm)->cm_l3instr_l3_3_clkctrl,
+		(*prcm)->cm_l3instr_l3_instr_clkctrl,
+		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+		(*prcm)->cm_l3init_hsi_clkctrl,
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_non_essential[] = {
-		&prcm->cm1_abe_aess_clkctrl,
-		&prcm->cm1_abe_pdm_clkctrl,
-		&prcm->cm1_abe_dmic_clkctrl,
-		&prcm->cm1_abe_mcasp_clkctrl,
-		&prcm->cm1_abe_mcbsp1_clkctrl,
-		&prcm->cm1_abe_mcbsp2_clkctrl,
-		&prcm->cm1_abe_mcbsp3_clkctrl,
-		&prcm->cm1_abe_slimbus_clkctrl,
-		&prcm->cm1_abe_timer5_clkctrl,
-		&prcm->cm1_abe_timer6_clkctrl,
-		&prcm->cm1_abe_timer7_clkctrl,
-		&prcm->cm1_abe_timer8_clkctrl,
-		&prcm->cm1_abe_wdt3_clkctrl,
-		&prcm->cm_l4per_gptimer9_clkctrl,
-		&prcm->cm_l4per_gptimer10_clkctrl,
-		&prcm->cm_l4per_gptimer11_clkctrl,
-		&prcm->cm_l4per_gptimer3_clkctrl,
-		&prcm->cm_l4per_gptimer4_clkctrl,
-		&prcm->cm_l4per_hdq1w_clkctrl,
-		&prcm->cm_l4per_mcbsp4_clkctrl,
-		&prcm->cm_l4per_mcspi2_clkctrl,
-		&prcm->cm_l4per_mcspi3_clkctrl,
-		&prcm->cm_l4per_mcspi4_clkctrl,
-		&prcm->cm_l4per_mmcsd3_clkctrl,
-		&prcm->cm_l4per_mmcsd4_clkctrl,
-		&prcm->cm_l4per_mmcsd5_clkctrl,
-		&prcm->cm_l4per_uart1_clkctrl,
-		&prcm->cm_l4per_uart2_clkctrl,
-		&prcm->cm_l4per_uart4_clkctrl,
-		&prcm->cm_wkup_keyboard_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_cam_iss_clkctrl,
-		&prcm->cm_cam_fdif_clkctrl,
-		&prcm->cm_dss_dss_clkctrl,
-		&prcm->cm_sgx_sgx_clkctrl,
+	u32 const clk_modules_explicit_en_non_essential[] = {
+		(*prcm)->cm1_abe_aess_clkctrl,
+		(*prcm)->cm1_abe_pdm_clkctrl,
+		(*prcm)->cm1_abe_dmic_clkctrl,
+		(*prcm)->cm1_abe_mcasp_clkctrl,
+		(*prcm)->cm1_abe_mcbsp1_clkctrl,
+		(*prcm)->cm1_abe_mcbsp2_clkctrl,
+		(*prcm)->cm1_abe_mcbsp3_clkctrl,
+		(*prcm)->cm1_abe_slimbus_clkctrl,
+		(*prcm)->cm1_abe_timer5_clkctrl,
+		(*prcm)->cm1_abe_timer6_clkctrl,
+		(*prcm)->cm1_abe_timer7_clkctrl,
+		(*prcm)->cm1_abe_timer8_clkctrl,
+		(*prcm)->cm1_abe_wdt3_clkctrl,
+		(*prcm)->cm_l4per_gptimer9_clkctrl,
+		(*prcm)->cm_l4per_gptimer10_clkctrl,
+		(*prcm)->cm_l4per_gptimer11_clkctrl,
+		(*prcm)->cm_l4per_gptimer3_clkctrl,
+		(*prcm)->cm_l4per_gptimer4_clkctrl,
+		(*prcm)->cm_l4per_hdq1w_clkctrl,
+		(*prcm)->cm_l4per_mcbsp4_clkctrl,
+		(*prcm)->cm_l4per_mcspi2_clkctrl,
+		(*prcm)->cm_l4per_mcspi3_clkctrl,
+		(*prcm)->cm_l4per_mcspi4_clkctrl,
+		(*prcm)->cm_l4per_mmcsd3_clkctrl,
+		(*prcm)->cm_l4per_mmcsd4_clkctrl,
+		(*prcm)->cm_l4per_mmcsd5_clkctrl,
+		(*prcm)->cm_l4per_uart1_clkctrl,
+		(*prcm)->cm_l4per_uart2_clkctrl,
+		(*prcm)->cm_l4per_uart4_clkctrl,
+		(*prcm)->cm_wkup_keyboard_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_cam_iss_clkctrl,
+		(*prcm)->cm_cam_fdif_clkctrl,
+		(*prcm)->cm_dss_dss_clkctrl,
+		(*prcm)->cm_sgx_sgx_clkctrl,
 		0
 	};
 
 	/* Enable optional functional clock for ISS */
-	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 
 	/* Enable all optional functional clocks of DSS */
-	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 
 	do_enable_clocks(clk_domains_non_essential,
 			 clk_modules_hw_auto_non_essential,
@@ -511,7 +509,8 @@ void enable_non_essential_clocks(void)
 			 0);
 
 	/* Put camera module in no sleep mode */
-	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
 			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
new file mode 100644
index 0000000000..3174cc3262
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -0,0 +1,38 @@
+/*
+ *
+ * HW data initialization for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct prcm_regs const **prcm =
+			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+
+void hw_data_init(void)
+{
+	*prcm = &omap4_prcm;
+}
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
new file mode 100644
index 0000000000..815b9d2086
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -0,0 +1,295 @@
+/*
+ *
+ * HW regs data for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap4_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core  = 0x4a004100,
+	.cm_clksel_abe = 0x4a004108,
+	.cm_dll_ctrl = 0x4a004110,
+	.cm_clkmode_dpll_core = 0x4a004120,
+	.cm_idlest_dpll_core = 0x4a004124,
+	.cm_autoidle_dpll_core = 0x4a004128,
+	.cm_clksel_dpll_core = 0x4a00412c,
+	.cm_div_m2_dpll_core = 0x4a004130,
+	.cm_div_m3_dpll_core = 0x4a004134,
+	.cm_div_m4_dpll_core = 0x4a004138,
+	.cm_div_m5_dpll_core = 0x4a00413c,
+	.cm_div_m6_dpll_core = 0x4a004140,
+	.cm_div_m7_dpll_core = 0x4a004144,
+	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
+	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+	.cm_emu_override_dpll_core = 0x4a004150,
+	.cm_clkmode_dpll_mpu = 0x4a004160,
+	.cm_idlest_dpll_mpu = 0x4a004164,
+	.cm_autoidle_dpll_mpu = 0x4a004168,
+	.cm_clksel_dpll_mpu = 0x4a00416c,
+	.cm_div_m2_dpll_mpu = 0x4a004170,
+	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+	.cm_bypclk_dpll_mpu = 0x4a00419c,
+	.cm_clkmode_dpll_iva = 0x4a0041a0,
+	.cm_idlest_dpll_iva = 0x4a0041a4,
+	.cm_autoidle_dpll_iva = 0x4a0041a8,
+	.cm_clksel_dpll_iva = 0x4a0041ac,
+	.cm_div_m4_dpll_iva = 0x4a0041b8,
+	.cm_div_m5_dpll_iva = 0x4a0041bc,
+	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+	.cm_bypclk_dpll_iva = 0x4a0041dc,
+	.cm_clkmode_dpll_abe = 0x4a0041e0,
+	.cm_idlest_dpll_abe = 0x4a0041e4,
+	.cm_autoidle_dpll_abe = 0x4a0041e8,
+	.cm_clksel_dpll_abe = 0x4a0041ec,
+	.cm_div_m2_dpll_abe = 0x4a0041f0,
+	.cm_div_m3_dpll_abe = 0x4a0041f4,
+	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+	.cm_clkmode_dpll_ddrphy = 0x4a004220,
+	.cm_idlest_dpll_ddrphy = 0x4a004224,
+	.cm_autoidle_dpll_ddrphy = 0x4a004228,
+	.cm_clksel_dpll_ddrphy = 0x4a00422c,
+	.cm_div_m2_dpll_ddrphy = 0x4a004230,
+	.cm_div_m4_dpll_ddrphy = 0x4a004238,
+	.cm_div_m5_dpll_ddrphy = 0x4a00423c,
+	.cm_div_m6_dpll_ddrphy = 0x4a004240,
+	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+	.cm_shadow_freq_config1 = 0x4a004260,
+	.cm_mpu_mpu_clkctrl = 0x4a004320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl = 0x4a004400,
+	.cm_dsp_dsp_clkctrl = 0x4a004420,
+
+	/* cm1.abe */
+	.cm1_abe_clkstctrl = 0x4a004500,
+	.cm1_abe_l4abe_clkctrl = 0x4a004520,
+	.cm1_abe_aess_clkctrl = 0x4a004528,
+	.cm1_abe_pdm_clkctrl = 0x4a004530,
+	.cm1_abe_dmic_clkctrl = 0x4a004538,
+	.cm1_abe_mcasp_clkctrl = 0x4a004540,
+	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+	.cm1_abe_slimbus_clkctrl = 0x4a004560,
+	.cm1_abe_timer5_clkctrl = 0x4a004568,
+	.cm1_abe_timer6_clkctrl = 0x4a004570,
+	.cm1_abe_timer7_clkctrl = 0x4a004578,
+	.cm1_abe_timer8_clkctrl = 0x4a004580,
+	.cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+	/* cm2.ckgen */
+	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
+	.cm_clksel_usb_60mhz = 0x4a008104,
+	.cm_scale_fclk = 0x4a008108,
+	.cm_core_dvfs_perf1 = 0x4a008110,
+	.cm_core_dvfs_perf2 = 0x4a008114,
+	.cm_core_dvfs_perf3 = 0x4a008118,
+	.cm_core_dvfs_perf4 = 0x4a00811c,
+	.cm_core_dvfs_current = 0x4a008124,
+	.cm_iva_dvfs_perf_tesla = 0x4a008128,
+	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+	.cm_iva_dvfs_perf_abe = 0x4a008130,
+	.cm_iva_dvfs_current = 0x4a008138,
+	.cm_clkmode_dpll_per = 0x4a008140,
+	.cm_idlest_dpll_per = 0x4a008144,
+	.cm_autoidle_dpll_per = 0x4a008148,
+	.cm_clksel_dpll_per = 0x4a00814c,
+	.cm_div_m2_dpll_per = 0x4a008150,
+	.cm_div_m3_dpll_per = 0x4a008154,
+	.cm_div_m4_dpll_per = 0x4a008158,
+	.cm_div_m5_dpll_per = 0x4a00815c,
+	.cm_div_m6_dpll_per = 0x4a008160,
+	.cm_div_m7_dpll_per = 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+	.cm_emu_override_dpll_per = 0x4a008170,
+	.cm_clkmode_dpll_usb = 0x4a008180,
+	.cm_idlest_dpll_usb = 0x4a008184,
+	.cm_autoidle_dpll_usb = 0x4a008188,
+	.cm_clksel_dpll_usb = 0x4a00818c,
+	.cm_div_m2_dpll_usb = 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+	.cm_clkmode_dpll_unipro = 0x4a0081c0,
+	.cm_idlest_dpll_unipro = 0x4a0081c4,
+	.cm_autoidle_dpll_unipro = 0x4a0081c8,
+	.cm_clksel_dpll_unipro = 0x4a0081cc,
+	.cm_div_m2_dpll_unipro = 0x4a0081d0,
+	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+	/* cm2.core */
+	.cm_l3_1_clkstctrl = 0x4a008700,
+	.cm_l3_1_dynamicdep = 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
+	.cm_l3_2_clkstctrl = 0x4a008800,
+	.cm_l3_2_dynamicdep = 0x4a008808,
+	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
+	.cm_l3_2_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+	.cm_mpu_m3_clkstctrl = 0x4a008900,
+	.cm_mpu_m3_staticdep = 0x4a008904,
+	.cm_mpu_m3_dynamicdep = 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+	.cm_sdma_clkstctrl = 0x4a008a00,
+	.cm_sdma_staticdep = 0x4a008a04,
+	.cm_sdma_dynamicdep = 0x4a008a08,
+	.cm_sdma_sdma_clkctrl = 0x4a008a20,
+	.cm_memif_clkstctrl = 0x4a008b00,
+	.cm_memif_dmm_clkctrl = 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
+	.cm_memif_emif_1_clkctrl = 0x4a008b30,
+	.cm_memif_emif_2_clkctrl = 0x4a008b38,
+	.cm_memif_dll_clkctrl = 0x4a008b40,
+	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
+	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
+	.cm_memif_dll_h_clkctrl = 0x4a008b60,
+	.cm_c2c_clkstctrl = 0x4a008c00,
+	.cm_c2c_staticdep = 0x4a008c04,
+	.cm_c2c_dynamicdep = 0x4a008c08,
+	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
+	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+	.cm_l4cfg_clkstctrl = 0x4a008d00,
+	.cm_l4cfg_dynamicdep = 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+	.cm_l3instr_clkstctrl = 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
+	.cm_ivahd_clkstctrl = 0x4a008f00,
+
+	/* cm2.ivahd */
+	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl = 0x4a009000,
+	.cm_cam_iss_clkctrl = 0x4a009020,
+	.cm_cam_fdif_clkctrl = 0x4a009028,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl = 0x4a009100,
+	.cm_dss_dss_clkctrl = 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl = 0x4a009200,
+	.cm_sgx_sgx_clkctrl = 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl = 0x4a009300,
+	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+	.cm_l3init_hsi_clkctrl = 0x4a009338,
+	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+	.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl = 0x4a009400,
+	.cm_l4per_dynamicdep = 0x4a009408,
+	.cm_l4per_adc_clkctrl = 0x4a009420,
+	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
+	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
+	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
+	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
+	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
+	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
+	.cm_l4per_elm_clkctrl = 0x4a009458,
+	.cm_l4per_gpio2_clkctrl = 0x4a009460,
+	.cm_l4per_gpio3_clkctrl = 0x4a009468,
+	.cm_l4per_gpio4_clkctrl = 0x4a009470,
+	.cm_l4per_gpio5_clkctrl = 0x4a009478,
+	.cm_l4per_gpio6_clkctrl = 0x4a009480,
+	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
+	.cm_l4per_hecc1_clkctrl = 0x4a009490,
+	.cm_l4per_hecc2_clkctrl = 0x4a009498,
+	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
+	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+	.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
+	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
+	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
+	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
+	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+	.cm_l4per_msprohg_clkctrl = 0x4a009530,
+	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
+	.cm_l4per_uart1_clkctrl = 0x4a009540,
+	.cm_l4per_uart2_clkctrl = 0x4a009548,
+	.cm_l4per_uart3_clkctrl = 0x4a009550,
+	.cm_l4per_uart4_clkctrl = 0x4a009558,
+	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+	.cm_l4per_i2c5_clkctrl = 0x4a009568,
+	.cm_l4sec_clkstctrl = 0x4a009580,
+	.cm_l4sec_staticdep = 0x4a009584,
+	.cm_l4sec_dynamicdep = 0x4a009588,
+	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
+	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel = 0x4a30610c,
+	.cm_sys_clksel = 0x4a306110,
+	.cm_wkup_clkstctrl = 0x4a307800,
+	.cm_wkup_l4wkup_clkctrl = 0x4a307820,
+	.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
+	.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
+	.cm_wkup_gpio1_clkctrl = 0x4a307838,
+	.cm_wkup_gptimer1_clkctrl = 0x4a307840,
+	.cm_wkup_gptimer12_clkctrl = 0x4a307848,
+	.cm_wkup_synctimer_clkctrl = 0x4a307850,
+	.cm_wkup_usim_clkctrl = 0x4a307858,
+	.cm_wkup_sarram_clkctrl = 0x4a307860,
+	.cm_wkup_keyboard_clkctrl = 0x4a307878,
+	.cm_wkup_rtc_clkctrl = 0x4a307880,
+	.cm_wkup_bandgap_clkctrl = 0x4a307888,
+	.prm_vc_val_bypass = 0x4a307ba0,
+	.prm_vc_cfg_channel = 0x4a307ba4,
+	.prm_vc_cfg_i2c_mode = 0x4a307ba8,
+	.prm_vc_cfg_i2c_clk = 0x4a307bac,
+};
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index 9b261c4df2..81625f6e68 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -29,6 +29,8 @@ COBJS	+= hwinit.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
 COBJS	+= sdram.o
+COBJS	+= prcm-regs.o
+COBJS	+= hw_data.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index 1f3369268d..a90f9222ca 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -47,8 +47,6 @@
 #define puts(s)
 #endif
 
-struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
-
 const u32 sys_clk_array[8] = {
 	12000000,	       /* 12 MHz */
 	0,		       /* NA */
@@ -188,7 +186,7 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
 {
 	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
@@ -282,9 +280,9 @@ void scale_vcores(void)
 
 	if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
 		/* Configure LDO SRAM "magic" bits */
-		writel(2, &prcm->prm_sldo_core_setup);
-		writel(2, &prcm->prm_sldo_mpu_setup);
-		writel(2, &prcm->prm_sldo_mm_setup);
+		writel(2, (*prcm)->prm_sldo_core_setup);
+		writel(2, (*prcm)->prm_sldo_mpu_setup);
+		writel(2, (*prcm)->prm_sldo_mm_setup);
 	}
 }
 
@@ -309,57 +307,57 @@ u32 get_offset_code(u32 volt_offset)
  */
 void enable_basic_clocks(void)
 {
-	u32 *const clk_domains_essential[] = {
-		&prcm->cm_l4per_clkstctrl,
-		&prcm->cm_l3init_clkstctrl,
-		&prcm->cm_memif_clkstctrl,
-		&prcm->cm_l4cfg_clkstctrl,
+	u32 const clk_domains_essential[] = {
+		(*prcm)->cm_l4per_clkstctrl,
+		(*prcm)->cm_l3init_clkstctrl,
+		(*prcm)->cm_memif_clkstctrl,
+		(*prcm)->cm_l4cfg_clkstctrl,
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_essential[] = {
-		&prcm->cm_l3_2_gpmc_clkctrl,
-		&prcm->cm_memif_emif_1_clkctrl,
-		&prcm->cm_memif_emif_2_clkctrl,
-		&prcm->cm_l4cfg_l4_cfg_clkctrl,
-		&prcm->cm_wkup_gpio1_clkctrl,
-		&prcm->cm_l4per_gpio2_clkctrl,
-		&prcm->cm_l4per_gpio3_clkctrl,
-		&prcm->cm_l4per_gpio4_clkctrl,
-		&prcm->cm_l4per_gpio5_clkctrl,
-		&prcm->cm_l4per_gpio6_clkctrl,
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3_2_gpmc_clkctrl,
+		(*prcm)->cm_memif_emif_1_clkctrl,
+		(*prcm)->cm_memif_emif_2_clkctrl,
+		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+		(*prcm)->cm_wkup_gpio1_clkctrl,
+		(*prcm)->cm_l4per_gpio2_clkctrl,
+		(*prcm)->cm_l4per_gpio3_clkctrl,
+		(*prcm)->cm_l4per_gpio4_clkctrl,
+		(*prcm)->cm_l4per_gpio5_clkctrl,
+		(*prcm)->cm_l4per_gpio6_clkctrl,
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_essential[] = {
-		&prcm->cm_wkup_gptimer1_clkctrl,
-		&prcm->cm_l3init_hsmmc1_clkctrl,
-		&prcm->cm_l3init_hsmmc2_clkctrl,
-		&prcm->cm_l4per_gptimer2_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_l4per_uart3_clkctrl,
-		&prcm->cm_l4per_i2c1_clkctrl,
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_wkup_gptimer1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc2_clkctrl,
+		(*prcm)->cm_l4per_gptimer2_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_l4per_uart3_clkctrl,
+		(*prcm)->cm_l4per_i2c1_clkctrl,
 		0
 	};
 
 	/* Enable optional additional functional clock for GPIO4 */
-	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
 	/* Enable 96 MHz clock for MMC1 & MMC2 */
-	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
-	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
 	/* Set the correct clock dividers for mmc */
-	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 
 	/* Select 32KHz clock as the source of GPTIMER1 */
-	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
 
 	do_enable_clocks(clk_domains_essential,
@@ -368,36 +366,36 @@ void enable_basic_clocks(void)
 			 1);
 
 	/* Select 384Mhz for GPU as its the POR for ES1.0 */
-	setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
+	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
 			CLKSEL_GPU_HYD_GCLK_MASK);
-	setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
+	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
 			CLKSEL_GPU_CORE_GCLK_MASK);
 
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
-	setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
+	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);
-	setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
+	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_CORE_MASK);
 }
 
 void enable_basic_uboot_clocks(void)
 {
-	u32 *const clk_domains_essential[] = {
+	u32 const clk_domains_essential[] = {
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_essential[] = {
+	u32 const clk_modules_hw_auto_essential[] = {
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_essential[] = {
-		&prcm->cm_l4per_mcspi1_clkctrl,
-		&prcm->cm_l4per_i2c2_clkctrl,
-		&prcm->cm_l4per_i2c3_clkctrl,
-		&prcm->cm_l4per_i2c4_clkctrl,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
-		&prcm->cm_l3init_fsusb_clkctrl,
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_mcspi1_clkctrl,
+		(*prcm)->cm_l4per_i2c2_clkctrl,
+		(*prcm)->cm_l4per_i2c3_clkctrl,
+		(*prcm)->cm_l4per_i2c4_clkctrl,
+		(*prcm)->cm_l3init_hsusbtll_clkctrl,
+		(*prcm)->cm_l3init_hsusbhost_clkctrl,
+		(*prcm)->cm_l3init_fsusb_clkctrl,
 		0
 	};
 
@@ -413,75 +411,75 @@ void enable_basic_uboot_clocks(void)
  */
 void enable_non_essential_clocks(void)
 {
-	u32 *const clk_domains_non_essential[] = {
-		&prcm->cm_mpu_m3_clkstctrl,
-		&prcm->cm_ivahd_clkstctrl,
-		&prcm->cm_dsp_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sgx_clkstctrl,
-		&prcm->cm1_abe_clkstctrl,
-		&prcm->cm_c2c_clkstctrl,
-		&prcm->cm_cam_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sdma_clkstctrl,
+	u32 const clk_domains_non_essential[] = {
+		(*prcm)->cm_mpu_m3_clkstctrl,
+		(*prcm)->cm_ivahd_clkstctrl,
+		(*prcm)->cm_dsp_clkstctrl,
+		(*prcm)->cm_dss_clkstctrl,
+		(*prcm)->cm_sgx_clkstctrl,
+		(*prcm)->cm1_abe_clkstctrl,
+		(*prcm)->cm_c2c_clkstctrl,
+		(*prcm)->cm_cam_clkstctrl,
+		(*prcm)->cm_dss_clkstctrl,
+		(*prcm)->cm_sdma_clkstctrl,
 		0
 	};
 
-	u32 *const clk_modules_hw_auto_non_essential[] = {
-		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
-		&prcm->cm_ivahd_ivahd_clkctrl,
-		&prcm->cm_ivahd_sl2_clkctrl,
-		&prcm->cm_dsp_dsp_clkctrl,
-		&prcm->cm_l3instr_l3_3_clkctrl,
-		&prcm->cm_l3instr_l3_instr_clkctrl,
-		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
-		&prcm->cm_l3init_hsi_clkctrl,
-		&prcm->cm_l4per_hdq1w_clkctrl,
+	u32 const clk_modules_hw_auto_non_essential[] = {
+		(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
+		(*prcm)->cm_ivahd_ivahd_clkctrl,
+		(*prcm)->cm_ivahd_sl2_clkctrl,
+		(*prcm)->cm_dsp_dsp_clkctrl,
+		(*prcm)->cm_l3instr_l3_3_clkctrl,
+		(*prcm)->cm_l3instr_l3_instr_clkctrl,
+		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+		(*prcm)->cm_l3init_hsi_clkctrl,
+		(*prcm)->cm_l4per_hdq1w_clkctrl,
 		0
 	};
 
-	u32 *const clk_modules_explicit_en_non_essential[] = {
-		&prcm->cm1_abe_aess_clkctrl,
-		&prcm->cm1_abe_pdm_clkctrl,
-		&prcm->cm1_abe_dmic_clkctrl,
-		&prcm->cm1_abe_mcasp_clkctrl,
-		&prcm->cm1_abe_mcbsp1_clkctrl,
-		&prcm->cm1_abe_mcbsp2_clkctrl,
-		&prcm->cm1_abe_mcbsp3_clkctrl,
-		&prcm->cm1_abe_slimbus_clkctrl,
-		&prcm->cm1_abe_timer5_clkctrl,
-		&prcm->cm1_abe_timer6_clkctrl,
-		&prcm->cm1_abe_timer7_clkctrl,
-		&prcm->cm1_abe_timer8_clkctrl,
-		&prcm->cm1_abe_wdt3_clkctrl,
-		&prcm->cm_l4per_gptimer9_clkctrl,
-		&prcm->cm_l4per_gptimer10_clkctrl,
-		&prcm->cm_l4per_gptimer11_clkctrl,
-		&prcm->cm_l4per_gptimer3_clkctrl,
-		&prcm->cm_l4per_gptimer4_clkctrl,
-		&prcm->cm_l4per_mcspi2_clkctrl,
-		&prcm->cm_l4per_mcspi3_clkctrl,
-		&prcm->cm_l4per_mcspi4_clkctrl,
-		&prcm->cm_l4per_mmcsd3_clkctrl,
-		&prcm->cm_l4per_mmcsd4_clkctrl,
-		&prcm->cm_l4per_mmcsd5_clkctrl,
-		&prcm->cm_l4per_uart1_clkctrl,
-		&prcm->cm_l4per_uart2_clkctrl,
-		&prcm->cm_l4per_uart4_clkctrl,
-		&prcm->cm_wkup_keyboard_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_cam_iss_clkctrl,
-		&prcm->cm_cam_fdif_clkctrl,
-		&prcm->cm_dss_dss_clkctrl,
-		&prcm->cm_sgx_sgx_clkctrl,
+	u32 const clk_modules_explicit_en_non_essential[] = {
+		(*prcm)->cm1_abe_aess_clkctrl,
+		(*prcm)->cm1_abe_pdm_clkctrl,
+		(*prcm)->cm1_abe_dmic_clkctrl,
+		(*prcm)->cm1_abe_mcasp_clkctrl,
+		(*prcm)->cm1_abe_mcbsp1_clkctrl,
+		(*prcm)->cm1_abe_mcbsp2_clkctrl,
+		(*prcm)->cm1_abe_mcbsp3_clkctrl,
+		(*prcm)->cm1_abe_slimbus_clkctrl,
+		(*prcm)->cm1_abe_timer5_clkctrl,
+		(*prcm)->cm1_abe_timer6_clkctrl,
+		(*prcm)->cm1_abe_timer7_clkctrl,
+		(*prcm)->cm1_abe_timer8_clkctrl,
+		(*prcm)->cm1_abe_wdt3_clkctrl,
+		(*prcm)->cm_l4per_gptimer9_clkctrl,
+		(*prcm)->cm_l4per_gptimer10_clkctrl,
+		(*prcm)->cm_l4per_gptimer11_clkctrl,
+		(*prcm)->cm_l4per_gptimer3_clkctrl,
+		(*prcm)->cm_l4per_gptimer4_clkctrl,
+		(*prcm)->cm_l4per_mcspi2_clkctrl,
+		(*prcm)->cm_l4per_mcspi3_clkctrl,
+		(*prcm)->cm_l4per_mcspi4_clkctrl,
+		(*prcm)->cm_l4per_mmcsd3_clkctrl,
+		(*prcm)->cm_l4per_mmcsd4_clkctrl,
+		(*prcm)->cm_l4per_mmcsd5_clkctrl,
+		(*prcm)->cm_l4per_uart1_clkctrl,
+		(*prcm)->cm_l4per_uart2_clkctrl,
+		(*prcm)->cm_l4per_uart4_clkctrl,
+		(*prcm)->cm_wkup_keyboard_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_cam_iss_clkctrl,
+		(*prcm)->cm_cam_fdif_clkctrl,
+		(*prcm)->cm_dss_dss_clkctrl,
+		(*prcm)->cm_sgx_sgx_clkctrl,
 		0
 	};
 
 	/* Enable optional functional clock for ISS */
-	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 
 	/* Enable all optional functional clocks of DSS */
-	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 
 	do_enable_clocks(clk_domains_non_essential,
 			 clk_modules_hw_auto_non_essential,
@@ -489,7 +487,8 @@ void enable_non_essential_clocks(void)
 			 0);
 
 	/* Put camera module in no sleep mode */
-	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
 			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
new file mode 100644
index 0000000000..0f1234c1eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -0,0 +1,38 @@
+/*
+ *
+ * HW data initialization for OMAP5
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct prcm_regs const **prcm =
+			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+
+void hw_data_init(void)
+{
+	*prcm = &omap5_es1_prcm;
+}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
new file mode 100644
index 0000000000..cdc4864919
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -0,0 +1,306 @@
+/*
+ *
+ * HW regs data for OMAP5 Soc
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap5_es1_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core = 0x4a004100,
+	.cm_clksel_abe = 0x4a004108,
+	.cm_dll_ctrl = 0x4a004110,
+	.cm_clkmode_dpll_core = 0x4a004120,
+	.cm_idlest_dpll_core = 0x4a004124,
+	.cm_autoidle_dpll_core = 0x4a004128,
+	.cm_clksel_dpll_core = 0x4a00412c,
+	.cm_div_m2_dpll_core = 0x4a004130,
+	.cm_div_m3_dpll_core = 0x4a004134,
+	.cm_div_h11_dpll_core = 0x4a004138,
+	.cm_div_h12_dpll_core = 0x4a00413c,
+	.cm_div_h13_dpll_core = 0x4a004140,
+	.cm_div_h14_dpll_core = 0x4a004144,
+	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
+	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+	.cm_emu_override_dpll_core = 0x4a004150,
+	.cm_div_h22_dpllcore = 0x4a004154,
+	.cm_div_h23_dpll_core = 0x4a004158,
+	.cm_clkmode_dpll_mpu = 0x4a004160,
+	.cm_idlest_dpll_mpu = 0x4a004164,
+	.cm_autoidle_dpll_mpu = 0x4a004168,
+	.cm_clksel_dpll_mpu = 0x4a00416c,
+	.cm_div_m2_dpll_mpu = 0x4a004170,
+	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+	.cm_bypclk_dpll_mpu = 0x4a00419c,
+	.cm_clkmode_dpll_iva = 0x4a0041a0,
+	.cm_idlest_dpll_iva = 0x4a0041a4,
+	.cm_autoidle_dpll_iva = 0x4a0041a8,
+	.cm_clksel_dpll_iva = 0x4a0041ac,
+	.cm_div_h11_dpll_iva = 0x4a0041b8,
+	.cm_div_h12_dpll_iva = 0x4a0041bc,
+	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+	.cm_bypclk_dpll_iva = 0x4a0041dc,
+	.cm_clkmode_dpll_abe = 0x4a0041e0,
+	.cm_idlest_dpll_abe = 0x4a0041e4,
+	.cm_autoidle_dpll_abe = 0x4a0041e8,
+	.cm_clksel_dpll_abe = 0x4a0041ec,
+	.cm_div_m2_dpll_abe = 0x4a0041f0,
+	.cm_div_m3_dpll_abe = 0x4a0041f4,
+	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+	.cm_clkmode_dpll_ddrphy = 0x4a004220,
+	.cm_idlest_dpll_ddrphy = 0x4a004224,
+	.cm_autoidle_dpll_ddrphy = 0x4a004228,
+	.cm_clksel_dpll_ddrphy = 0x4a00422c,
+	.cm_div_m2_dpll_ddrphy = 0x4a004230,
+	.cm_div_h11_dpll_ddrphy = 0x4a004238,
+	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
+	.cm_div_h13_dpll_ddrphy = 0x4a004240,
+	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+	.cm_shadow_freq_config1 = 0x4a004260,
+	.cm_mpu_mpu_clkctrl = 0x4a004320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl = 0x4a004400,
+	.cm_dsp_dsp_clkctrl = 0x4a004420,
+
+	/* cm1.abe */
+	.cm1_abe_clkstctrl = 0x4a004500,
+	.cm1_abe_l4abe_clkctrl = 0x4a004520,
+	.cm1_abe_aess_clkctrl = 0x4a004528,
+	.cm1_abe_pdm_clkctrl = 0x4a004530,
+	.cm1_abe_dmic_clkctrl = 0x4a004538,
+	.cm1_abe_mcasp_clkctrl = 0x4a004540,
+	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+	.cm1_abe_slimbus_clkctrl = 0x4a004560,
+	.cm1_abe_timer5_clkctrl = 0x4a004568,
+	.cm1_abe_timer6_clkctrl = 0x4a004570,
+	.cm1_abe_timer7_clkctrl = 0x4a004578,
+	.cm1_abe_timer8_clkctrl = 0x4a004580,
+	.cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+	/* cm2.ckgen */
+	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
+	.cm_clksel_usb_60mhz = 0x4a008104,
+	.cm_scale_fclk = 0x4a008108,
+	.cm_core_dvfs_perf1 = 0x4a008110,
+	.cm_core_dvfs_perf2 = 0x4a008114,
+	.cm_core_dvfs_perf3 = 0x4a008118,
+	.cm_core_dvfs_perf4 = 0x4a00811c,
+	.cm_core_dvfs_current = 0x4a008124,
+	.cm_iva_dvfs_perf_tesla = 0x4a008128,
+	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+	.cm_iva_dvfs_perf_abe = 0x4a008130,
+	.cm_iva_dvfs_current = 0x4a008138,
+	.cm_clkmode_dpll_per = 0x4a008140,
+	.cm_idlest_dpll_per = 0x4a008144,
+	.cm_autoidle_dpll_per = 0x4a008148,
+	.cm_clksel_dpll_per = 0x4a00814c,
+	.cm_div_m2_dpll_per = 0x4a008150,
+	.cm_div_m3_dpll_per = 0x4a008154,
+	.cm_div_h11_dpll_per = 0x4a008158,
+	.cm_div_h12_dpll_per = 0x4a00815c,
+	.cm_div_h14_dpll_per = 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+	.cm_emu_override_dpll_per = 0x4a008170,
+	.cm_clkmode_dpll_usb = 0x4a008180,
+	.cm_idlest_dpll_usb = 0x4a008184,
+	.cm_autoidle_dpll_usb = 0x4a008188,
+	.cm_clksel_dpll_usb = 0x4a00818c,
+	.cm_div_m2_dpll_usb = 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+	.cm_clkmode_dpll_unipro = 0x4a0081c0,
+	.cm_idlest_dpll_unipro = 0x4a0081c4,
+	.cm_autoidle_dpll_unipro = 0x4a0081c8,
+	.cm_clksel_dpll_unipro = 0x4a0081cc,
+	.cm_div_m2_dpll_unipro = 0x4a0081d0,
+	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+	/* cm2.core */
+	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
+	.cm_l3_1_clkstctrl = 0x4a008700,
+	.cm_l3_1_dynamicdep = 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
+	.cm_l3_2_clkstctrl = 0x4a008800,
+	.cm_l3_2_dynamicdep = 0x4a008808,
+	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
+	.cm_l3_2_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+	.cm_mpu_m3_clkstctrl = 0x4a008900,
+	.cm_mpu_m3_staticdep = 0x4a008904,
+	.cm_mpu_m3_dynamicdep = 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+	.cm_sdma_clkstctrl = 0x4a008a00,
+	.cm_sdma_staticdep = 0x4a008a04,
+	.cm_sdma_dynamicdep = 0x4a008a08,
+	.cm_sdma_sdma_clkctrl = 0x4a008a20,
+	.cm_memif_clkstctrl = 0x4a008b00,
+	.cm_memif_dmm_clkctrl = 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
+	.cm_memif_emif_1_clkctrl = 0x4a008b30,
+	.cm_memif_emif_2_clkctrl = 0x4a008b38,
+	.cm_memif_dll_clkctrl = 0x4a008b40,
+	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
+	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
+	.cm_memif_dll_h_clkctrl = 0x4a008b60,
+	.cm_c2c_clkstctrl = 0x4a008c00,
+	.cm_c2c_staticdep = 0x4a008c04,
+	.cm_c2c_dynamicdep = 0x4a008c08,
+	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
+	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+	.cm_l4cfg_clkstctrl = 0x4a008d00,
+	.cm_l4cfg_dynamicdep = 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+	.cm_l3instr_clkstctrl = 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+	/* cm2.ivahd */
+	.cm_ivahd_clkstctrl = 0x4a008f00,
+	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl = 0x4a009000,
+	.cm_cam_iss_clkctrl = 0x4a009020,
+	.cm_cam_fdif_clkctrl = 0x4a009028,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl = 0x4a009100,
+	.cm_dss_dss_clkctrl = 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl = 0x4a009200,
+	.cm_sgx_sgx_clkctrl = 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl = 0x4a009300,
+	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+	.cm_l3init_hsi_clkctrl = 0x4a009338,
+	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl = 0x4a009400,
+	.cm_l4per_dynamicdep = 0x4a009408,
+	.cm_l4per_adc_clkctrl = 0x4a009420,
+	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
+	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
+	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
+	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
+	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
+	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
+	.cm_l4per_elm_clkctrl = 0x4a009458,
+	.cm_l4per_gpio2_clkctrl = 0x4a009460,
+	.cm_l4per_gpio3_clkctrl = 0x4a009468,
+	.cm_l4per_gpio4_clkctrl = 0x4a009470,
+	.cm_l4per_gpio5_clkctrl = 0x4a009478,
+	.cm_l4per_gpio6_clkctrl = 0x4a009480,
+	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
+	.cm_l4per_hecc1_clkctrl = 0x4a009490,
+	.cm_l4per_hecc2_clkctrl = 0x4a009498,
+	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
+	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
+	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
+	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
+	.cm_l4per_gpio7_clkctrl = 0x4a009510,
+	.cm_l4per_gpio8_clkctrl = 0x4a009518,
+	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+	.cm_l4per_msprohg_clkctrl = 0x4a009530,
+	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
+	.cm_l4per_uart1_clkctrl = 0x4a009540,
+	.cm_l4per_uart2_clkctrl = 0x4a009548,
+	.cm_l4per_uart3_clkctrl = 0x4a009550,
+	.cm_l4per_uart4_clkctrl = 0x4a009558,
+	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+	.cm_l4per_i2c5_clkctrl = 0x4a009568,
+	.cm_l4per_uart5_clkctrl = 0x4a009570,
+	.cm_l4per_uart6_clkctrl = 0x4a009578,
+	.cm_l4sec_clkstctrl = 0x4a009580,
+	.cm_l4sec_staticdep = 0x4a009584,
+	.cm_l4sec_dynamicdep = 0x4a009588,
+	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
+	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel = 0x4ae0610c,
+	.cm_sys_clksel = 0x4ae06110,
+	.cm_wkup_clkstctrl = 0x4ae07800,
+	.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+	.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+	.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+	.cm_wkup_gpio1_clkctrl = 0x4ae07838,
+	.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+	.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+	.cm_wkup_synctimer_clkctrl = 0x4ae07850,
+	.cm_wkup_usim_clkctrl = 0x4ae07858,
+	.cm_wkup_sarram_clkctrl = 0x4ae07860,
+	.cm_wkup_keyboard_clkctrl = 0x4ae07878,
+	.cm_wkup_rtc_clkctrl = 0x4ae07880,
+	.cm_wkup_bandgap_clkctrl = 0x4ae07888,
+	.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+	.prm_vc_val_bypass = 0x4ae07ba0,
+	.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
+	.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
+	.prm_sldo_core_setup = 0x4ae07bc4,
+	.prm_sldo_core_ctrl = 0x4ae07bc8,
+	.prm_sldo_mpu_setup = 0x4ae07bcc,
+	.prm_sldo_mpu_ctrl = 0x4ae07bd0,
+	.prm_sldo_mm_setup = 0x4ae07bd4,
+	.prm_sldo_mm_ctrl = 0x4ae07bd8,
+};
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index be20fc0ce6..4710d88b4d 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -25,6 +25,7 @@
 #ifndef _CLOCKS_OMAP4_H_
 #define _CLOCKS_OMAP4_H_
 #include <common.h>
+#include <asm/omap_common.h>
 
 /*
  * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@@ -38,479 +39,6 @@
 #define CM_CLKMODE_DPLL_MPU		0x4A004160
 #define CM_CLKSEL_CORE			0x4A004100
 
-struct omap4_prcm_regs {
-	/* cm1.ckgen */
-	u32 cm_clksel_core;
-	u32 pad001[1];
-	u32 cm_clksel_abe;
-	u32 pad002[1];
-	u32 cm_dll_ctrl;
-	u32 pad003[3];
-	u32 cm_clkmode_dpll_core;
-	u32 cm_idlest_dpll_core;
-	u32 cm_autoidle_dpll_core;
-	u32 cm_clksel_dpll_core;
-	u32 cm_div_m2_dpll_core;
-	u32 cm_div_m3_dpll_core;
-	u32 cm_div_m4_dpll_core;
-	u32 cm_div_m5_dpll_core;
-	u32 cm_div_m6_dpll_core;
-	u32 cm_div_m7_dpll_core;
-	u32 cm_ssc_deltamstep_dpll_core;
-	u32 cm_ssc_modfreqdiv_dpll_core;
-	u32 cm_emu_override_dpll_core;
-	u32 pad004[3];
-	u32 cm_clkmode_dpll_mpu;
-	u32 cm_idlest_dpll_mpu;
-	u32 cm_autoidle_dpll_mpu;
-	u32 cm_clksel_dpll_mpu;
-	u32 cm_div_m2_dpll_mpu;
-	u32 pad005[5];
-	u32 cm_ssc_deltamstep_dpll_mpu;
-	u32 cm_ssc_modfreqdiv_dpll_mpu;
-	u32 pad006[3];
-	u32 cm_bypclk_dpll_mpu;
-	u32 cm_clkmode_dpll_iva;
-	u32 cm_idlest_dpll_iva;
-	u32 cm_autoidle_dpll_iva;
-	u32 cm_clksel_dpll_iva;
-	u32 pad007[2];
-	u32 cm_div_m4_dpll_iva;
-	u32 cm_div_m5_dpll_iva;
-	u32 pad008[2];
-	u32 cm_ssc_deltamstep_dpll_iva;
-	u32 cm_ssc_modfreqdiv_dpll_iva;
-	u32 pad009[3];
-	u32 cm_bypclk_dpll_iva;
-	u32 cm_clkmode_dpll_abe;
-	u32 cm_idlest_dpll_abe;
-	u32 cm_autoidle_dpll_abe;
-	u32 cm_clksel_dpll_abe;
-	u32 cm_div_m2_dpll_abe;
-	u32 cm_div_m3_dpll_abe;
-	u32 pad010[4];
-	u32 cm_ssc_deltamstep_dpll_abe;
-	u32 cm_ssc_modfreqdiv_dpll_abe;
-	u32 pad011[4];
-	u32 cm_clkmode_dpll_ddrphy;
-	u32 cm_idlest_dpll_ddrphy;
-	u32 cm_autoidle_dpll_ddrphy;
-	u32 cm_clksel_dpll_ddrphy;
-	u32 cm_div_m2_dpll_ddrphy;
-	u32 pad012[1];
-	u32 cm_div_m4_dpll_ddrphy;
-	u32 cm_div_m5_dpll_ddrphy;
-	u32 cm_div_m6_dpll_ddrphy;
-	u32 pad013[1];
-	u32 cm_ssc_deltamstep_dpll_ddrphy;
-	u32 pad014[5];
-	u32 cm_shadow_freq_config1;
-	u32 pad0141[47];
-	u32 cm_mpu_mpu_clkctrl;
-
-	/* cm1.dsp */
-	u32 pad015[55];
-	u32 cm_dsp_clkstctrl;
-	u32 pad016[7];
-	u32 cm_dsp_dsp_clkctrl;
-
-	/* cm1.abe */
-	u32 pad017[55];
-	u32 cm1_abe_clkstctrl;
-	u32 pad018[7];
-	u32 cm1_abe_l4abe_clkctrl;
-	u32 pad019[1];
-	u32 cm1_abe_aess_clkctrl;
-	u32 pad020[1];
-	u32 cm1_abe_pdm_clkctrl;
-	u32 pad021[1];
-	u32 cm1_abe_dmic_clkctrl;
-	u32 pad022[1];
-	u32 cm1_abe_mcasp_clkctrl;
-	u32 pad023[1];
-	u32 cm1_abe_mcbsp1_clkctrl;
-	u32 pad024[1];
-	u32 cm1_abe_mcbsp2_clkctrl;
-	u32 pad025[1];
-	u32 cm1_abe_mcbsp3_clkctrl;
-	u32 pad026[1];
-	u32 cm1_abe_slimbus_clkctrl;
-	u32 pad027[1];
-	u32 cm1_abe_timer5_clkctrl;
-	u32 pad028[1];
-	u32 cm1_abe_timer6_clkctrl;
-	u32 pad029[1];
-	u32 cm1_abe_timer7_clkctrl;
-	u32 pad030[1];
-	u32 cm1_abe_timer8_clkctrl;
-	u32 pad031[1];
-	u32 cm1_abe_wdt3_clkctrl;
-
-	/* cm2.ckgen */
-	u32 pad032[3805];
-	u32 cm_clksel_mpu_m3_iss_root;
-	u32 cm_clksel_usb_60mhz;
-	u32 cm_scale_fclk;
-	u32 pad033[1];
-	u32 cm_core_dvfs_perf1;
-	u32 cm_core_dvfs_perf2;
-	u32 cm_core_dvfs_perf3;
-	u32 cm_core_dvfs_perf4;
-	u32 pad034[1];
-	u32 cm_core_dvfs_current;
-	u32 cm_iva_dvfs_perf_tesla;
-	u32 cm_iva_dvfs_perf_ivahd;
-	u32 cm_iva_dvfs_perf_abe;
-	u32 pad035[1];
-	u32 cm_iva_dvfs_current;
-	u32 pad036[1];
-	u32 cm_clkmode_dpll_per;
-	u32 cm_idlest_dpll_per;
-	u32 cm_autoidle_dpll_per;
-	u32 cm_clksel_dpll_per;
-	u32 cm_div_m2_dpll_per;
-	u32 cm_div_m3_dpll_per;
-	u32 cm_div_m4_dpll_per;
-	u32 cm_div_m5_dpll_per;
-	u32 cm_div_m6_dpll_per;
-	u32 cm_div_m7_dpll_per;
-	u32 cm_ssc_deltamstep_dpll_per;
-	u32 cm_ssc_modfreqdiv_dpll_per;
-	u32 cm_emu_override_dpll_per;
-	u32 pad037[3];
-	u32 cm_clkmode_dpll_usb;
-	u32 cm_idlest_dpll_usb;
-	u32 cm_autoidle_dpll_usb;
-	u32 cm_clksel_dpll_usb;
-	u32 cm_div_m2_dpll_usb;
-	u32 pad038[5];
-	u32 cm_ssc_deltamstep_dpll_usb;
-	u32 cm_ssc_modfreqdiv_dpll_usb;
-	u32 pad039[1];
-	u32 cm_clkdcoldo_dpll_usb;
-	u32 pad040[2];
-	u32 cm_clkmode_dpll_unipro;
-	u32 cm_idlest_dpll_unipro;
-	u32 cm_autoidle_dpll_unipro;
-	u32 cm_clksel_dpll_unipro;
-	u32 cm_div_m2_dpll_unipro;
-	u32 pad041[5];
-	u32 cm_ssc_deltamstep_dpll_unipro;
-	u32 cm_ssc_modfreqdiv_dpll_unipro;
-
-	/* cm2.core */
-	u32 pad0411[324];
-	u32 cm_l3_1_clkstctrl;
-	u32 pad042[1];
-	u32 cm_l3_1_dynamicdep;
-	u32 pad043[5];
-	u32 cm_l3_1_l3_1_clkctrl;
-	u32 pad044[55];
-	u32 cm_l3_2_clkstctrl;
-	u32 pad045[1];
-	u32 cm_l3_2_dynamicdep;
-	u32 pad046[5];
-	u32 cm_l3_2_l3_2_clkctrl;
-	u32 pad047[1];
-	u32 cm_l3_2_gpmc_clkctrl;
-	u32 pad048[1];
-	u32 cm_l3_2_ocmc_ram_clkctrl;
-	u32 pad049[51];
-	u32 cm_mpu_m3_clkstctrl;
-	u32 cm_mpu_m3_staticdep;
-	u32 cm_mpu_m3_dynamicdep;
-	u32 pad050[5];
-	u32 cm_mpu_m3_mpu_m3_clkctrl;
-	u32 pad051[55];
-	u32 cm_sdma_clkstctrl;
-	u32 cm_sdma_staticdep;
-	u32 cm_sdma_dynamicdep;
-	u32 pad052[5];
-	u32 cm_sdma_sdma_clkctrl;
-	u32 pad053[55];
-	u32 cm_memif_clkstctrl;
-	u32 pad054[7];
-	u32 cm_memif_dmm_clkctrl;
-	u32 pad055[1];
-	u32 cm_memif_emif_fw_clkctrl;
-	u32 pad056[1];
-	u32 cm_memif_emif_1_clkctrl;
-	u32 pad057[1];
-	u32 cm_memif_emif_2_clkctrl;
-	u32 pad058[1];
-	u32 cm_memif_dll_clkctrl;
-	u32 pad059[3];
-	u32 cm_memif_emif_h1_clkctrl;
-	u32 pad060[1];
-	u32 cm_memif_emif_h2_clkctrl;
-	u32 pad061[1];
-	u32 cm_memif_dll_h_clkctrl;
-	u32 pad062[39];
-	u32 cm_c2c_clkstctrl;
-	u32 cm_c2c_staticdep;
-	u32 cm_c2c_dynamicdep;
-	u32 pad063[5];
-	u32 cm_c2c_sad2d_clkctrl;
-	u32 pad064[1];
-	u32 cm_c2c_modem_icr_clkctrl;
-	u32 pad065[1];
-	u32 cm_c2c_sad2d_fw_clkctrl;
-	u32 pad066[51];
-	u32 cm_l4cfg_clkstctrl;
-	u32 pad067[1];
-	u32 cm_l4cfg_dynamicdep;
-	u32 pad068[5];
-	u32 cm_l4cfg_l4_cfg_clkctrl;
-	u32 pad069[1];
-	u32 cm_l4cfg_hw_sem_clkctrl;
-	u32 pad070[1];
-	u32 cm_l4cfg_mailbox_clkctrl;
-	u32 pad071[1];
-	u32 cm_l4cfg_sar_rom_clkctrl;
-	u32 pad072[49];
-	u32 cm_l3instr_clkstctrl;
-	u32 pad073[7];
-	u32 cm_l3instr_l3_3_clkctrl;
-	u32 pad074[1];
-	u32 cm_l3instr_l3_instr_clkctrl;
-	u32 pad075[5];
-	u32 cm_l3instr_intrconn_wp1_clkctrl;
-
-
-	/* cm2.ivahd */
-	u32 pad076[47];
-	u32 cm_ivahd_clkstctrl;
-	u32 pad077[7];
-	u32 cm_ivahd_ivahd_clkctrl;
-	u32 pad078[1];
-	u32 cm_ivahd_sl2_clkctrl;
-
-	/* cm2.cam */
-	u32 pad079[53];
-	u32 cm_cam_clkstctrl;
-	u32 pad080[7];
-	u32 cm_cam_iss_clkctrl;
-	u32 pad081[1];
-	u32 cm_cam_fdif_clkctrl;
-
-	/* cm2.dss */
-	u32 pad082[53];
-	u32 cm_dss_clkstctrl;
-	u32 pad083[7];
-	u32 cm_dss_dss_clkctrl;
-
-	/* cm2.sgx */
-	u32 pad084[55];
-	u32 cm_sgx_clkstctrl;
-	u32 pad085[7];
-	u32 cm_sgx_sgx_clkctrl;
-
-	/* cm2.l3init */
-	u32 pad086[55];
-	u32 cm_l3init_clkstctrl;
-
-	/* cm2.l3init */
-	u32 pad087[9];
-	u32 cm_l3init_hsmmc1_clkctrl;
-	u32 pad088[1];
-	u32 cm_l3init_hsmmc2_clkctrl;
-	u32 pad089[1];
-	u32 cm_l3init_hsi_clkctrl;
-	u32 pad090[7];
-	u32 cm_l3init_hsusbhost_clkctrl;
-	u32 pad091[1];
-	u32 cm_l3init_hsusbotg_clkctrl;
-	u32 pad092[1];
-	u32 cm_l3init_hsusbtll_clkctrl;
-	u32 pad093[3];
-	u32 cm_l3init_p1500_clkctrl;
-	u32 pad094[21];
-	u32 cm_l3init_fsusb_clkctrl;
-	u32 pad095[3];
-	u32 cm_l3init_usbphy_clkctrl;
-
-	/* cm2.l4per */
-	u32 pad096[7];
-	u32 cm_l4per_clkstctrl;
-	u32 pad097[1];
-	u32 cm_l4per_dynamicdep;
-	u32 pad098[5];
-	u32 cm_l4per_adc_clkctrl;
-	u32 pad100[1];
-	u32 cm_l4per_gptimer10_clkctrl;
-	u32 pad101[1];
-	u32 cm_l4per_gptimer11_clkctrl;
-	u32 pad102[1];
-	u32 cm_l4per_gptimer2_clkctrl;
-	u32 pad103[1];
-	u32 cm_l4per_gptimer3_clkctrl;
-	u32 pad104[1];
-	u32 cm_l4per_gptimer4_clkctrl;
-	u32 pad105[1];
-	u32 cm_l4per_gptimer9_clkctrl;
-	u32 pad106[1];
-	u32 cm_l4per_elm_clkctrl;
-	u32 pad107[1];
-	u32 cm_l4per_gpio2_clkctrl;
-	u32 pad108[1];
-	u32 cm_l4per_gpio3_clkctrl;
-	u32 pad109[1];
-	u32 cm_l4per_gpio4_clkctrl;
-	u32 pad110[1];
-	u32 cm_l4per_gpio5_clkctrl;
-	u32 pad111[1];
-	u32 cm_l4per_gpio6_clkctrl;
-	u32 pad112[1];
-	u32 cm_l4per_hdq1w_clkctrl;
-	u32 pad113[1];
-	u32 cm_l4per_hecc1_clkctrl;
-	u32 pad114[1];
-	u32 cm_l4per_hecc2_clkctrl;
-	u32 pad115[1];
-	u32 cm_l4per_i2c1_clkctrl;
-	u32 pad116[1];
-	u32 cm_l4per_i2c2_clkctrl;
-	u32 pad117[1];
-	u32 cm_l4per_i2c3_clkctrl;
-	u32 pad118[1];
-	u32 cm_l4per_i2c4_clkctrl;
-	u32 pad119[1];
-	u32 cm_l4per_l4per_clkctrl;
-	u32 pad1191[3];
-	u32 cm_l4per_mcasp2_clkctrl;
-	u32 pad120[1];
-	u32 cm_l4per_mcasp3_clkctrl;
-	u32 pad121[1];
-	u32 cm_l4per_mcbsp4_clkctrl;
-	u32 pad122[1];
-	u32 cm_l4per_mgate_clkctrl;
-	u32 pad123[1];
-	u32 cm_l4per_mcspi1_clkctrl;
-	u32 pad124[1];
-	u32 cm_l4per_mcspi2_clkctrl;
-	u32 pad125[1];
-	u32 cm_l4per_mcspi3_clkctrl;
-	u32 pad126[1];
-	u32 cm_l4per_mcspi4_clkctrl;
-	u32 pad127[5];
-	u32 cm_l4per_mmcsd3_clkctrl;
-	u32 pad128[1];
-	u32 cm_l4per_mmcsd4_clkctrl;
-	u32 pad129[1];
-	u32 cm_l4per_msprohg_clkctrl;
-	u32 pad130[1];
-	u32 cm_l4per_slimbus2_clkctrl;
-	u32 pad131[1];
-	u32 cm_l4per_uart1_clkctrl;
-	u32 pad132[1];
-	u32 cm_l4per_uart2_clkctrl;
-	u32 pad133[1];
-	u32 cm_l4per_uart3_clkctrl;
-	u32 pad134[1];
-	u32 cm_l4per_uart4_clkctrl;
-	u32 pad135[1];
-	u32 cm_l4per_mmcsd5_clkctrl;
-	u32 pad136[1];
-	u32 cm_l4per_i2c5_clkctrl;
-	u32 pad137[5];
-	u32 cm_l4sec_clkstctrl;
-	u32 cm_l4sec_staticdep;
-	u32 cm_l4sec_dynamicdep;
-	u32 pad138[5];
-	u32 cm_l4sec_aes1_clkctrl;
-	u32 pad139[1];
-	u32 cm_l4sec_aes2_clkctrl;
-	u32 pad140[1];
-	u32 cm_l4sec_des3des_clkctrl;
-	u32 pad141[1];
-	u32 cm_l4sec_pkaeip29_clkctrl;
-	u32 pad142[1];
-	u32 cm_l4sec_rng_clkctrl;
-	u32 pad143[1];
-	u32 cm_l4sec_sha2md51_clkctrl;
-	u32 pad144[3];
-	u32 cm_l4sec_cryptodma_clkctrl;
-	u32 pad145[776841];
-
-	/* l4 wkup regs */
-	u32 pad201[6211];
-	u32 cm_abe_pll_ref_clksel;
-	u32 cm_sys_clksel;
-	u32 pad202[1467];
-	u32 cm_wkup_clkstctrl;
-	u32 pad203[7];
-	u32 cm_wkup_l4wkup_clkctrl;
-	u32 pad204;
-	u32 cm_wkup_wdtimer1_clkctrl;
-	u32 pad205;
-	u32 cm_wkup_wdtimer2_clkctrl;
-	u32 pad206;
-	u32 cm_wkup_gpio1_clkctrl;
-	u32 pad207;
-	u32 cm_wkup_gptimer1_clkctrl;
-	u32 pad208;
-	u32 cm_wkup_gptimer12_clkctrl;
-	u32 pad209;
-	u32 cm_wkup_synctimer_clkctrl;
-	u32 pad210;
-	u32 cm_wkup_usim_clkctrl;
-	u32 pad211;
-	u32 cm_wkup_sarram_clkctrl;
-	u32 pad212[5];
-	u32 cm_wkup_keyboard_clkctrl;
-	u32 pad213;
-	u32 cm_wkup_rtc_clkctrl;
-	u32 pad214;
-	u32 cm_wkup_bandgap_clkctrl;
-	u32 pad215[197];
-	u32 prm_vc_val_bypass;
-	u32 prm_vc_cfg_channel;
-	u32 prm_vc_cfg_i2c_mode;
-	u32 prm_vc_cfg_i2c_clk;
-
-};
-
-struct omap4_scrm_regs {
-	u32 revision;		/* 0x0000 */
-	u32 pad00[63];
-	u32 clksetuptime;	/* 0x0100 */
-	u32 pmicsetuptime;	/* 0x0104 */
-	u32 pad01[2];
-	u32 altclksrc;		/* 0x0110 */
-	u32 pad02[2];
-	u32 c2cclkm;		/* 0x011c */
-	u32 pad03[56];
-	u32 extclkreq;		/* 0x0200 */
-	u32 accclkreq;		/* 0x0204 */
-	u32 pwrreq;		/* 0x0208 */
-	u32 pad04[1];
-	u32 auxclkreq0;		/* 0x0210 */
-	u32 auxclkreq1;		/* 0x0214 */
-	u32 auxclkreq2;		/* 0x0218 */
-	u32 auxclkreq3;		/* 0x021c */
-	u32 auxclkreq4;		/* 0x0220 */
-	u32 auxclkreq5;		/* 0x0224 */
-	u32 pad05[3];
-	u32 c2cclkreq;		/* 0x0234 */
-	u32 pad06[54];
-	u32 auxclk0;		/* 0x0310 */
-	u32 auxclk1;		/* 0x0314 */
-	u32 auxclk2;		/* 0x0318 */
-	u32 auxclk3;		/* 0x031c */
-	u32 auxclk4;		/* 0x0320 */
-	u32 auxclk5;		/* 0x0324 */
-	u32 pad07[54];
-	u32 rsttime_reg;	/* 0x0400 */
-	u32 pad08[6];
-	u32 c2crstctrl;		/* 0x041c */
-	u32 extpwronrstctrl;	/* 0x0420 */
-	u32 pad09[59];
-	u32 extwarmrstst_reg;	/* 0x0510 */
-	u32 apewarmrstst_reg;	/* 0x0514 */
-	u32 pad10[1];
-	u32 c2cwarmrstst_reg;	/* 0x051C */
-};
-
 /* DPLL register offsets */
 #define CM_CLKMODE_DPLL		0
 #define CM_IDLEST_DPLL		0x4
@@ -741,7 +269,6 @@ struct dpll_params {
 	s8 m7;
 };
 
-extern struct omap4_prcm_regs *const prcm;
 extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
@@ -749,14 +276,14 @@ void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
 u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+void setup_post_dividers(u32 const base, const struct dpll_params *params);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
 void enable_non_essential_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
-		      u32 *const *clk_modules_hw_auto,
-		      u32 *const *clk_modules_explicit_en,
+void do_enable_clocks(u32 const *clk_domains,
+		      u32 const *clk_modules_hw_auto,
+		      u32 const *clk_modules_explicit_en,
 		      u8 wait_for_enable);
 const struct dpll_params *get_mpu_dpll_params(void);
 const struct dpll_params *get_core_dpll_params(void);
@@ -764,4 +291,45 @@ const struct dpll_params *get_per_dpll_params(void);
 const struct dpll_params *get_iva_dpll_params(void);
 const struct dpll_params *get_usb_dpll_params(void);
 const struct dpll_params *get_abe_dpll_params(void);
+
+struct omap4_scrm_regs {
+	u32 revision;           /* 0x0000 */
+	u32 pad00[63];
+	u32 clksetuptime;       /* 0x0100 */
+	u32 pmicsetuptime;      /* 0x0104 */
+	u32 pad01[2];
+	u32 altclksrc;          /* 0x0110 */
+	u32 pad02[2];
+	u32 c2cclkm;            /* 0x011c */
+	u32 pad03[56];
+	u32 extclkreq;          /* 0x0200 */
+	u32 accclkreq;          /* 0x0204 */
+	u32 pwrreq;             /* 0x0208 */
+	u32 pad04[1];
+	u32 auxclkreq0;         /* 0x0210 */
+	u32 auxclkreq1;         /* 0x0214 */
+	u32 auxclkreq2;         /* 0x0218 */
+	u32 auxclkreq3;         /* 0x021c */
+	u32 auxclkreq4;         /* 0x0220 */
+	u32 auxclkreq5;         /* 0x0224 */
+	u32 pad05[3];
+	u32 c2cclkreq;          /* 0x0234 */
+	u32 pad06[54];
+	u32 auxclk0;            /* 0x0310 */
+	u32 auxclk1;            /* 0x0314 */
+	u32 auxclk2;            /* 0x0318 */
+	u32 auxclk3;            /* 0x031c */
+	u32 auxclk4;            /* 0x0320 */
+	u32 auxclk5;            /* 0x0324 */
+	u32 pad07[54];
+	u32 rsttime_reg;        /* 0x0400 */
+	u32 pad08[6];
+	u32 c2crstctrl;         /* 0x041c */
+	u32 extpwronrstctrl;    /* 0x0420 */
+	u32 pad09[59];
+	u32 extwarmrstst_reg;   /* 0x0510 */
+	u32 apewarmrstst_reg;   /* 0x0514 */
+	u32 pad10[1];
+	u32 c2cwarmrstst_reg;   /* 0x051C */
+};
 #endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index d4b5076108..86ba3359ec 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -178,7 +178,8 @@ struct control_lpddr2io_regs {
 #define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
 #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x18)
 
 /* ROM code defines */
 /* Boot device */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b48f81dc33..d5f1868eee 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,7 +44,7 @@ void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 5f1a7aa770..67e74ca402 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -26,6 +26,7 @@
 #ifndef _CLOCKS_OMAP5_H_
 #define _CLOCKS_OMAP5_H_
 #include <common.h>
+#include <asm/omap_common.h>
 
 /*
  * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@@ -39,456 +40,6 @@
 #define CM_CLKMODE_DPLL_MPU		(OMAP54XX_L4_CORE_BASE + 0x4160)
 #define CM_CLKSEL_CORE			(OMAP54XX_L4_CORE_BASE + 0x4100)
 
-struct omap5_prcm_regs {
-	/* cm1.ckgen */
-	u32 cm_clksel_core;			/* 4a004100 */
-	u32 pad001[1];				/* 4a004104 */
-	u32 cm_clksel_abe;			/* 4a004108 */
-	u32 pad002[1];				/* 4a00410c */
-	u32 cm_dll_ctrl;			/* 4a004110 */
-	u32 pad003[3];				/* 4a004114 */
-	u32 cm_clkmode_dpll_core;		/* 4a004120 */
-	u32 cm_idlest_dpll_core;		/* 4a004124 */
-	u32 cm_autoidle_dpll_core;		/* 4a004128 */
-	u32 cm_clksel_dpll_core;		/* 4a00412c */
-	u32 cm_div_m2_dpll_core;		/* 4a004130 */
-	u32 cm_div_m3_dpll_core;		/* 4a004134 */
-	u32 cm_div_h11_dpll_core;		/* 4a004138 */
-	u32 cm_div_h12_dpll_core;		/* 4a00413c */
-	u32 cm_div_h13_dpll_core;		/* 4a004140 */
-	u32 cm_div_h14_dpll_core;		/* 4a004144 */
-	u32 cm_ssc_deltamstep_dpll_core;	/* 4a004148 */
-	u32 cm_ssc_modfreqdiv_dpll_core;	/* 4a00414c */
-	u32 cm_emu_override_dpll_core;		/* 4a004150 */
-
-	u32 cm_div_h22_dpllcore;		/* 4a004154 */
-	u32 cm_div_h23_dpll_core;		/* 4a004158 */
-	u32 pad0041[1];				/* 4a00415c */
-	u32 cm_clkmode_dpll_mpu;		/* 4a004160 */
-	u32 cm_idlest_dpll_mpu;			/* 4a004164 */
-	u32 cm_autoidle_dpll_mpu;		/* 4a004168 */
-	u32 cm_clksel_dpll_mpu;			/* 4a00416c */
-	u32 cm_div_m2_dpll_mpu;			/* 4a004170 */
-	u32 pad005[5];				/* 4a004174 */
-	u32 cm_ssc_deltamstep_dpll_mpu;		/* 4a004188 */
-	u32 cm_ssc_modfreqdiv_dpll_mpu;		/* 4a00418c */
-	u32 pad006[3];				/* 4a004190 */
-	u32 cm_bypclk_dpll_mpu;			/* 4a00419c */
-	u32 cm_clkmode_dpll_iva;		/* 4a0041a0 */
-	u32 cm_idlest_dpll_iva;			/* 4a0041a4 */
-	u32 cm_autoidle_dpll_iva;		/* 4a0041a8 */
-	u32 cm_clksel_dpll_iva;			/* 4a0041ac */
-	u32 pad007[2];				/* 4a0041b0 */
-	u32 cm_div_h11_dpll_iva;		/* 4a0041b8 */
-	u32 cm_div_h12_dpll_iva;		/* 4a0041bc */
-	u32 pad008[2];				/* 4a0041c0 */
-	u32 cm_ssc_deltamstep_dpll_iva;		/* 4a0041c8 */
-	u32 cm_ssc_modfreqdiv_dpll_iva;		/* 4a0041cc */
-	u32 pad009[3];				/* 4a0041d0 */
-	u32 cm_bypclk_dpll_iva;			/* 4a0041dc */
-	u32 cm_clkmode_dpll_abe;		/* 4a0041e0 */
-	u32 cm_idlest_dpll_abe;			/* 4a0041e4 */
-	u32 cm_autoidle_dpll_abe;		/* 4a0041e8 */
-	u32 cm_clksel_dpll_abe;			/* 4a0041ec */
-	u32 cm_div_m2_dpll_abe;			/* 4a0041f0 */
-	u32 cm_div_m3_dpll_abe;			/* 4a0041f4 */
-	u32 pad010[4];				/* 4a0041f8 */
-	u32 cm_ssc_deltamstep_dpll_abe;		/* 4a004208 */
-	u32 cm_ssc_modfreqdiv_dpll_abe;		/* 4a00420c */
-	u32 pad011[4];				/* 4a004210 */
-	u32 cm_clkmode_dpll_ddrphy;		/* 4a004220 */
-	u32 cm_idlest_dpll_ddrphy;		/* 4a004224 */
-	u32 cm_autoidle_dpll_ddrphy;		/* 4a004228 */
-	u32 cm_clksel_dpll_ddrphy;		/* 4a00422c */
-	u32 cm_div_m2_dpll_ddrphy;		/* 4a004230 */
-	u32 pad012[1];				/* 4a004234 */
-	u32 cm_div_h11_dpll_ddrphy;		/* 4a004238 */
-	u32 cm_div_h12_dpll_ddrphy;		/* 4a00423c */
-	u32 cm_div_h13_dpll_ddrphy;		/* 4a004240 */
-	u32 pad013[1];				/* 4a004244 */
-	u32 cm_ssc_deltamstep_dpll_ddrphy;	/* 4a004248 */
-	u32 pad014[5];				/* 4a00424c */
-	u32 cm_shadow_freq_config1;		/* 4a004260 */
-	u32 pad0141[47];			/* 4a004264 */
-	u32 cm_mpu_mpu_clkctrl;			/* 4a004320 */
-
-
-	/* cm1.dsp */
-	u32 pad015[55];				/* 4a004324 */
-	u32 cm_dsp_clkstctrl;			/* 4a004400 */
-	u32 pad016[7];				/* 4a004404 */
-	u32 cm_dsp_dsp_clkctrl;			/* 4a004420 */
-
-	/* cm1.abe */
-	u32 pad017[55];				/* 4a004424 */
-	u32 cm1_abe_clkstctrl;			/* 4a004500 */
-	u32 pad018[7];				/* 4a004504 */
-	u32 cm1_abe_l4abe_clkctrl;		/* 4a004520 */
-	u32 pad019[1];				/* 4a004524 */
-	u32 cm1_abe_aess_clkctrl;		/* 4a004528 */
-	u32 pad020[1];				/* 4a00452c */
-	u32 cm1_abe_pdm_clkctrl;		/* 4a004530 */
-	u32 pad021[1];				/* 4a004534 */
-	u32 cm1_abe_dmic_clkctrl;		/* 4a004538 */
-	u32 pad022[1];				/* 4a00453c */
-	u32 cm1_abe_mcasp_clkctrl;		/* 4a004540 */
-	u32 pad023[1];				/* 4a004544 */
-	u32 cm1_abe_mcbsp1_clkctrl;		/* 4a004548 */
-	u32 pad024[1];				/* 4a00454c */
-	u32 cm1_abe_mcbsp2_clkctrl;		/* 4a004550 */
-	u32 pad025[1];				/* 4a004554 */
-	u32 cm1_abe_mcbsp3_clkctrl;		/* 4a004558 */
-	u32 pad026[1];				/* 4a00455c */
-	u32 cm1_abe_slimbus_clkctrl;		/* 4a004560 */
-	u32 pad027[1];				/* 4a004564 */
-	u32 cm1_abe_timer5_clkctrl;		/* 4a004568 */
-	u32 pad028[1];				/* 4a00456c */
-	u32 cm1_abe_timer6_clkctrl;		/* 4a004570 */
-	u32 pad029[1];				/* 4a004574 */
-	u32 cm1_abe_timer7_clkctrl;		/* 4a004578 */
-	u32 pad030[1];				/* 4a00457c */
-	u32 cm1_abe_timer8_clkctrl;		/* 4a004580 */
-	u32 pad031[1];				/* 4a004584 */
-	u32 cm1_abe_wdt3_clkctrl;		/* 4a004588 */
-
-	/* cm2.ckgen */
-	u32 pad032[3805];			/* 4a00458c */
-	u32 cm_clksel_mpu_m3_iss_root;		/* 4a008100 */
-	u32 cm_clksel_usb_60mhz;		/* 4a008104 */
-	u32 cm_scale_fclk;			/* 4a008108 */
-	u32 pad033[1];				/* 4a00810c */
-	u32 cm_core_dvfs_perf1;			/* 4a008110 */
-	u32 cm_core_dvfs_perf2;			/* 4a008114 */
-	u32 cm_core_dvfs_perf3;			/* 4a008118 */
-	u32 cm_core_dvfs_perf4;			/* 4a00811c */
-	u32 pad034[1];				/* 4a008120 */
-	u32 cm_core_dvfs_current;		/* 4a008124 */
-	u32 cm_iva_dvfs_perf_tesla;		/* 4a008128 */
-	u32 cm_iva_dvfs_perf_ivahd;		/* 4a00812c */
-	u32 cm_iva_dvfs_perf_abe;		/* 4a008130 */
-	u32 pad035[1];				/* 4a008134 */
-	u32 cm_iva_dvfs_current;		/* 4a008138 */
-	u32 pad036[1];				/* 4a00813c */
-	u32 cm_clkmode_dpll_per;		/* 4a008140 */
-	u32 cm_idlest_dpll_per;			/* 4a008144 */
-	u32 cm_autoidle_dpll_per;		/* 4a008148 */
-	u32 cm_clksel_dpll_per;			/* 4a00814c */
-	u32 cm_div_m2_dpll_per;			/* 4a008150 */
-	u32 cm_div_m3_dpll_per;			/* 4a008154 */
-	u32 cm_div_h11_dpll_per;		/* 4a008158 */
-	u32 cm_div_h12_dpll_per;		/* 4a00815c */
-	u32 pad0361[1];				/* 4a008160 */
-	u32 cm_div_h14_dpll_per;		/* 4a008164 */
-	u32 cm_ssc_deltamstep_dpll_per;		/* 4a008168 */
-	u32 cm_ssc_modfreqdiv_dpll_per;		/* 4a00816c */
-	u32 cm_emu_override_dpll_per;		/* 4a008170 */
-	u32 pad037[3];				/* 4a008174 */
-	u32 cm_clkmode_dpll_usb;		/* 4a008180 */
-	u32 cm_idlest_dpll_usb;			/* 4a008184 */
-	u32 cm_autoidle_dpll_usb;		/* 4a008188 */
-	u32 cm_clksel_dpll_usb;			/* 4a00818c */
-	u32 cm_div_m2_dpll_usb;			/* 4a008190 */
-	u32 pad038[5];				/* 4a008194 */
-	u32 cm_ssc_deltamstep_dpll_usb;		/* 4a0081a8 */
-	u32 cm_ssc_modfreqdiv_dpll_usb;		/* 4a0081ac */
-	u32 pad039[1];				/* 4a0081b0 */
-	u32 cm_clkdcoldo_dpll_usb;		/* 4a0081b4 */
-	u32 pad040[2];				/* 4a0081b8 */
-	u32 cm_clkmode_dpll_unipro;		/* 4a0081c0 */
-	u32 cm_idlest_dpll_unipro;		/* 4a0081c4 */
-	u32 cm_autoidle_dpll_unipro;		/* 4a0081c8 */
-	u32 cm_clksel_dpll_unipro;		/* 4a0081cc */
-	u32 cm_div_m2_dpll_unipro;		/* 4a0081d0 */
-	u32 pad041[5];				/* 4a0081d4 */
-	u32 cm_ssc_deltamstep_dpll_unipro;	/* 4a0081e8 */
-	u32 cm_ssc_modfreqdiv_dpll_unipro;	/* 4a0081ec */
-
-	/* cm2.core */
-	u32 pad0411[324];			/* 4a0081f0 */
-	u32 cm_l3_1_clkstctrl;			/* 4a008700 */
-	u32 pad042[1];				/* 4a008704 */
-	u32 cm_l3_1_dynamicdep;			/* 4a008708 */
-	u32 pad043[5];				/* 4a00870c */
-	u32 cm_l3_1_l3_1_clkctrl;		/* 4a008720 */
-	u32 pad044[55];				/* 4a008724 */
-	u32 cm_l3_2_clkstctrl;			/* 4a008800 */
-	u32 pad045[1];				/* 4a008804 */
-	u32 cm_l3_2_dynamicdep;			/* 4a008808 */
-	u32 pad046[5];				/* 4a00880c */
-	u32 cm_l3_2_l3_2_clkctrl;		/* 4a008820 */
-	u32 pad047[1];				/* 4a008824 */
-	u32 cm_l3_2_gpmc_clkctrl;		/* 4a008828 */
-	u32 pad048[1];				/* 4a00882c */
-	u32 cm_l3_2_ocmc_ram_clkctrl;		/* 4a008830 */
-	u32 pad049[51];				/* 4a008834 */
-	u32 cm_mpu_m3_clkstctrl;		/* 4a008900 */
-	u32 cm_mpu_m3_staticdep;		/* 4a008904 */
-	u32 cm_mpu_m3_dynamicdep;		/* 4a008908 */
-	u32 pad050[5];				/* 4a00890c */
-	u32 cm_mpu_m3_mpu_m3_clkctrl;		/* 4a008920 */
-	u32 pad051[55];				/* 4a008924 */
-	u32 cm_sdma_clkstctrl;			/* 4a008a00 */
-	u32 cm_sdma_staticdep;			/* 4a008a04 */
-	u32 cm_sdma_dynamicdep;			/* 4a008a08 */
-	u32 pad052[5];				/* 4a008a0c */
-	u32 cm_sdma_sdma_clkctrl;		/* 4a008a20 */
-	u32 pad053[55];				/* 4a008a24 */
-	u32 cm_memif_clkstctrl;			/* 4a008b00 */
-	u32 pad054[7];				/* 4a008b04 */
-	u32 cm_memif_dmm_clkctrl;		/* 4a008b20 */
-	u32 pad055[1];				/* 4a008b24 */
-	u32 cm_memif_emif_fw_clkctrl;		/* 4a008b28 */
-	u32 pad056[1];				/* 4a008b2c */
-	u32 cm_memif_emif_1_clkctrl;		/* 4a008b30 */
-	u32 pad057[1];				/* 4a008b34 */
-	u32 cm_memif_emif_2_clkctrl;		/* 4a008b38 */
-	u32 pad058[1];				/* 4a008b3c */
-	u32 cm_memif_dll_clkctrl;		/* 4a008b40 */
-	u32 pad059[3];				/* 4a008b44 */
-	u32 cm_memif_emif_h1_clkctrl;		/* 4a008b50 */
-	u32 pad060[1];				/* 4a008b54 */
-	u32 cm_memif_emif_h2_clkctrl;		/* 4a008b58 */
-	u32 pad061[1];				/* 4a008b5c */
-	u32 cm_memif_dll_h_clkctrl;		/* 4a008b60 */
-	u32 pad062[39];				/* 4a008b64 */
-	u32 cm_c2c_clkstctrl;			/* 4a008c00 */
-	u32 cm_c2c_staticdep;			/* 4a008c04 */
-	u32 cm_c2c_dynamicdep;			/* 4a008c08 */
-	u32 pad063[5];				/* 4a008c0c */
-	u32 cm_c2c_sad2d_clkctrl;		/* 4a008c20 */
-	u32 pad064[1];				/* 4a008c24 */
-	u32 cm_c2c_modem_icr_clkctrl;		/* 4a008c28 */
-	u32 pad065[1];				/* 4a008c2c */
-	u32 cm_c2c_sad2d_fw_clkctrl;		/* 4a008c30 */
-	u32 pad066[51];				/* 4a008c34 */
-	u32 cm_l4cfg_clkstctrl;			/* 4a008d00 */
-	u32 pad067[1];				/* 4a008d04 */
-	u32 cm_l4cfg_dynamicdep;		/* 4a008d08 */
-	u32 pad068[5];				/* 4a008d0c */
-	u32 cm_l4cfg_l4_cfg_clkctrl;		/* 4a008d20 */
-	u32 pad069[1];				/* 4a008d24 */
-	u32 cm_l4cfg_hw_sem_clkctrl;		/* 4a008d28 */
-	u32 pad070[1];				/* 4a008d2c */
-	u32 cm_l4cfg_mailbox_clkctrl;		/* 4a008d30 */
-	u32 pad071[1];				/* 4a008d34 */
-	u32 cm_l4cfg_sar_rom_clkctrl;		/* 4a008d38 */
-	u32 pad072[49];				/* 4a008d3c */
-	u32 cm_l3instr_clkstctrl;		/* 4a008e00 */
-	u32 pad073[7];				/* 4a008e04 */
-	u32 cm_l3instr_l3_3_clkctrl;		/* 4a008e20 */
-	u32 pad074[1];				/* 4a008e24 */
-	u32 cm_l3instr_l3_instr_clkctrl;	/* 4a008e28 */
-	u32 pad075[5];				/* 4a008e2c */
-	u32 cm_l3instr_intrconn_wp1_clkctrl;	/* 4a008e40 */
-
-
-	/* cm2.ivahd */
-	u32 pad076[47];				/* 4a008e44 */
-	u32 cm_ivahd_clkstctrl;			/* 4a008f00 */
-	u32 pad077[7];				/* 4a008f04 */
-	u32 cm_ivahd_ivahd_clkctrl;		/* 4a008f20 */
-	u32 pad078[1];				/* 4a008f24 */
-	u32 cm_ivahd_sl2_clkctrl;		/* 4a008f28 */
-
-	/* cm2.cam */
-	u32 pad079[53];				/* 4a008f2c */
-	u32 cm_cam_clkstctrl;			/* 4a009000 */
-	u32 pad080[7];				/* 4a009004 */
-	u32 cm_cam_iss_clkctrl;			/* 4a009020 */
-	u32 pad081[1];				/* 4a009024 */
-	u32 cm_cam_fdif_clkctrl;		/* 4a009028 */
-
-	/* cm2.dss */
-	u32 pad082[53];				/* 4a00902c */
-	u32 cm_dss_clkstctrl;			/* 4a009100 */
-	u32 pad083[7];				/* 4a009104 */
-	u32 cm_dss_dss_clkctrl;			/* 4a009120 */
-
-	/* cm2.sgx */
-	u32 pad084[55];				/* 4a009124 */
-	u32 cm_sgx_clkstctrl;			/* 4a009200 */
-	u32 pad085[7];				/* 4a009204 */
-	u32 cm_sgx_sgx_clkctrl;			/* 4a009220 */
-
-	/* cm2.l3init */
-	u32 pad086[55];				/* 4a009224 */
-	u32 cm_l3init_clkstctrl;		/* 4a009300 */
-
-	/* cm2.l3init */
-	u32 pad087[9];				/* 4a009304 */
-	u32 cm_l3init_hsmmc1_clkctrl;		/* 4a009328 */
-	u32 pad088[1];				/* 4a00932c */
-	u32 cm_l3init_hsmmc2_clkctrl;		/* 4a009330 */
-	u32 pad089[1];				/* 4a009334 */
-	u32 cm_l3init_hsi_clkctrl;		/* 4a009338 */
-	u32 pad090[7];				/* 4a00933c */
-	u32 cm_l3init_hsusbhost_clkctrl;	/* 4a009358 */
-	u32 pad091[1];				/* 4a00935c */
-	u32 cm_l3init_hsusbotg_clkctrl;		/* 4a009360 */
-	u32 pad092[1];				/* 4a009364 */
-	u32 cm_l3init_hsusbtll_clkctrl;		/* 4a009368 */
-	u32 pad093[3];				/* 4a00936c */
-	u32 cm_l3init_p1500_clkctrl;		/* 4a009378 */
-	u32 pad094[21];				/* 4a00937c */
-	u32 cm_l3init_fsusb_clkctrl;		/* 4a0093d0 */
-	u32 pad095[3];				/* 4a0093d4 */
-	u32 cm_l3init_ocp2scp1_clkctrl;
-
-	/* cm2.l4per */
-	u32 pad096[7];				/* 4a0093e4 */
-	u32 cm_l4per_clkstctrl;			/* 4a009400 */
-	u32 pad097[1];				/* 4a009404 */
-	u32 cm_l4per_dynamicdep;		/* 4a009408 */
-	u32 pad098[5];				/* 4a00940c */
-	u32 cm_l4per_adc_clkctrl;		/* 4a009420 */
-	u32 pad100[1];				/* 4a009424 */
-	u32 cm_l4per_gptimer10_clkctrl;		/* 4a009428 */
-	u32 pad101[1];				/* 4a00942c */
-	u32 cm_l4per_gptimer11_clkctrl;		/* 4a009430 */
-	u32 pad102[1];				/* 4a009434 */
-	u32 cm_l4per_gptimer2_clkctrl;		/* 4a009438 */
-	u32 pad103[1];				/* 4a00943c */
-	u32 cm_l4per_gptimer3_clkctrl;		/* 4a009440 */
-	u32 pad104[1];				/* 4a009444 */
-	u32 cm_l4per_gptimer4_clkctrl;		/* 4a009448 */
-	u32 pad105[1];				/* 4a00944c */
-	u32 cm_l4per_gptimer9_clkctrl;		/* 4a009450 */
-	u32 pad106[1];				/* 4a009454 */
-	u32 cm_l4per_elm_clkctrl;		/* 4a009458 */
-	u32 pad107[1];				/* 4a00945c */
-	u32 cm_l4per_gpio2_clkctrl;		/* 4a009460 */
-	u32 pad108[1];				/* 4a009464 */
-	u32 cm_l4per_gpio3_clkctrl;		/* 4a009468 */
-	u32 pad109[1];				/* 4a00946c */
-	u32 cm_l4per_gpio4_clkctrl;		/* 4a009470 */
-	u32 pad110[1];				/* 4a009474 */
-	u32 cm_l4per_gpio5_clkctrl;		/* 4a009478 */
-	u32 pad111[1];				/* 4a00947c */
-	u32 cm_l4per_gpio6_clkctrl;		/* 4a009480 */
-	u32 pad112[1];				/* 4a009484 */
-	u32 cm_l4per_hdq1w_clkctrl;		/* 4a009488 */
-	u32 pad113[1];				/* 4a00948c */
-	u32 cm_l4per_hecc1_clkctrl;		/* 4a009490 */
-	u32 pad114[1];				/* 4a009494 */
-	u32 cm_l4per_hecc2_clkctrl;		/* 4a009498 */
-	u32 pad115[1];				/* 4a00949c */
-	u32 cm_l4per_i2c1_clkctrl;		/* 4a0094a0 */
-	u32 pad116[1];				/* 4a0094a4 */
-	u32 cm_l4per_i2c2_clkctrl;		/* 4a0094a8 */
-	u32 pad117[1];				/* 4a0094ac */
-	u32 cm_l4per_i2c3_clkctrl;		/* 4a0094b0 */
-	u32 pad118[1];				/* 4a0094b4 */
-	u32 cm_l4per_i2c4_clkctrl;		/* 4a0094b8 */
-	u32 pad119[1];				/* 4a0094bc */
-	u32 cm_l4per_l4per_clkctrl;		/* 4a0094c0 */
-	u32 pad1191[3];				/* 4a0094c4 */
-	u32 cm_l4per_mcasp2_clkctrl;		/* 4a0094d0 */
-	u32 pad120[1];				/* 4a0094d4 */
-	u32 cm_l4per_mcasp3_clkctrl;		/* 4a0094d8 */
-	u32 pad121[3];				/* 4a0094dc */
-	u32 cm_l4per_mgate_clkctrl;		/* 4a0094e8 */
-	u32 pad123[1];				/* 4a0094ec */
-	u32 cm_l4per_mcspi1_clkctrl;		/* 4a0094f0 */
-	u32 pad124[1];				/* 4a0094f4 */
-	u32 cm_l4per_mcspi2_clkctrl;		/* 4a0094f8 */
-	u32 pad125[1];				/* 4a0094fc */
-	u32 cm_l4per_mcspi3_clkctrl;		/* 4a009500 */
-	u32 pad126[1];				/* 4a009504 */
-	u32 cm_l4per_mcspi4_clkctrl;		/* 4a009508 */
-	u32 pad127[1];				/* 4a00950c */
-	u32 cm_l4per_gpio7_clkctrl;		/* 4a009510 */
-	u32 pad1271[1];				/* 4a009514 */
-	u32 cm_l4per_gpio8_clkctrl;		/* 4a009518 */
-	u32 pad1272[1];				/* 4a00951c */
-	u32 cm_l4per_mmcsd3_clkctrl;		/* 4a009520 */
-	u32 pad128[1];				/* 4a009524 */
-	u32 cm_l4per_mmcsd4_clkctrl;		/* 4a009528 */
-	u32 pad129[1];				/* 4a00952c */
-	u32 cm_l4per_msprohg_clkctrl;		/* 4a009530 */
-	u32 pad130[1];				/* 4a009534 */
-	u32 cm_l4per_slimbus2_clkctrl;		/* 4a009538 */
-	u32 pad131[1];				/* 4a00953c */
-	u32 cm_l4per_uart1_clkctrl;		/* 4a009540 */
-	u32 pad132[1];				/* 4a009544 */
-	u32 cm_l4per_uart2_clkctrl;		/* 4a009548 */
-	u32 pad133[1];				/* 4a00954c */
-	u32 cm_l4per_uart3_clkctrl;		/* 4a009550 */
-	u32 pad134[1];				/* 4a009554 */
-	u32 cm_l4per_uart4_clkctrl;		/* 4a009558 */
-	u32 pad135[1];				/* 4a00955c */
-	u32 cm_l4per_mmcsd5_clkctrl;		/* 4a009560 */
-	u32 pad136[1];				/* 4a009564 */
-	u32 cm_l4per_i2c5_clkctrl;		/* 4a009568 */
-	u32 pad1371[1];				/* 4a00956c */
-	u32 cm_l4per_uart5_clkctrl;		/* 4a009570 */
-	u32 pad1372[1];				/* 4a009574 */
-	u32 cm_l4per_uart6_clkctrl;		/* 4a009578 */
-	u32 pad1374[1];				/* 4a00957c */
-	u32 cm_l4sec_clkstctrl;			/* 4a009580 */
-	u32 cm_l4sec_staticdep;			/* 4a009584 */
-	u32 cm_l4sec_dynamicdep;		/* 4a009588 */
-	u32 pad138[5];				/* 4a00958c */
-	u32 cm_l4sec_aes1_clkctrl;		/* 4a0095a0 */
-	u32 pad139[1];				/* 4a0095a4 */
-	u32 cm_l4sec_aes2_clkctrl;		/* 4a0095a8 */
-	u32 pad140[1];				/* 4a0095ac */
-	u32 cm_l4sec_des3des_clkctrl;		/* 4a0095b0 */
-	u32 pad141[1];				/* 4a0095b4 */
-	u32 cm_l4sec_pkaeip29_clkctrl;		/* 4a0095b8 */
-	u32 pad142[1];				/* 4a0095bc */
-	u32 cm_l4sec_rng_clkctrl;		/* 4a0095c0 */
-	u32 pad143[1];				/* 4a0095c4 */
-	u32 cm_l4sec_sha2md51_clkctrl;		/* 4a0095c8 */
-	u32 pad144[3];				/* 4a0095cc */
-	u32 cm_l4sec_cryptodma_clkctrl;		/* 4a0095d8 */
-	u32 pad145[3660425];			/* 4a0095dc */
-
-	/* l4 wkup regs */
-	u32 pad201[6211];			/* 4ae00000 */
-	u32 cm_abe_pll_ref_clksel;		/* 4ae0610c */
-	u32 cm_sys_clksel;			/* 4ae06110 */
-	u32 pad202[1467];			/* 4ae06114 */
-	u32 cm_wkup_clkstctrl;			/* 4ae07800 */
-	u32 pad203[7];				/* 4ae07804 */
-	u32 cm_wkup_l4wkup_clkctrl;		/* 4ae07820 */
-	u32 pad204;				/* 4ae07824 */
-	u32 cm_wkup_wdtimer1_clkctrl;		/* 4ae07828 */
-	u32 pad205;				/* 4ae0782c */
-	u32 cm_wkup_wdtimer2_clkctrl;		/* 4ae07830 */
-	u32 pad206;				/* 4ae07834 */
-	u32 cm_wkup_gpio1_clkctrl;		/* 4ae07838 */
-	u32 pad207;				/* 4ae0783c */
-	u32 cm_wkup_gptimer1_clkctrl;		/* 4ae07840 */
-	u32 pad208;				/* 4ae07844 */
-	u32 cm_wkup_gptimer12_clkctrl;		/* 4ae07848 */
-	u32 pad209;				/* 4ae0784c */
-	u32 cm_wkup_synctimer_clkctrl;		/* 4ae07850 */
-	u32 pad210;				/* 4ae07854 */
-	u32 cm_wkup_usim_clkctrl;		/* 4ae07858 */
-	u32 pad211;				/* 4ae0785c */
-	u32 cm_wkup_sarram_clkctrl;		/* 4ae07860 */
-	u32 pad212[5];				/* 4ae07864 */
-	u32 cm_wkup_keyboard_clkctrl;		/* 4ae07878 */
-	u32 pad213;				/* 4ae0787c */
-	u32 cm_wkup_rtc_clkctrl;		/* 4ae07880 */
-	u32 pad214;				/* 4ae07884 */
-	u32 cm_wkup_bandgap_clkctrl;		/* 4ae07888 */
-	u32 pad215[1];				/* 4ae0788c */
-	u32 cm_wkupaon_scrm_clkctrl;		/* 4ae07890 */
-	u32 pad216[195];
-	u32 prm_vc_val_bypass;			/* 4ae07ba0 */
-	u32 pad217[4];
-	u32 prm_vc_cfg_i2c_mode;		/* 4ae07bb4 */
-	u32 prm_vc_cfg_i2c_clk;			/* 4ae07bb8 */
-	u32 pad218[2];
-	u32 prm_sldo_core_setup;		/* 4ae07bc4 */
-	u32 prm_sldo_core_ctrl;			/* 4ae07bc8 */
-	u32 prm_sldo_mpu_setup;			/* 4ae07bcc */
-	u32 prm_sldo_mpu_ctrl;			/* 4ae07bd0 */
-	u32 prm_sldo_mm_setup;			/* 4ae07bd4 */
-	u32 prm_sldo_mm_ctrl;			/* 4ae07bd8 */
-};
-
 /* DPLL register offsets */
 #define CM_CLKMODE_DPLL		0
 #define CM_IDLEST_DPLL		0x4
@@ -715,7 +266,6 @@ struct dpll_params {
 	s8 h23;
 };
 
-extern struct omap5_prcm_regs *const prcm;
 extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
@@ -723,14 +273,14 @@ void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
 u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+void setup_post_dividers(u32 const base, const struct dpll_params *params);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_non_essential_clocks(void);
 void enable_basic_uboot_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
-		      u32 *const *clk_modules_hw_auto,
-		      u32 *const *clk_modules_explicit_en,
+void do_enable_clocks(u32 const *clk_domains,
+		      u32 const *clk_modules_hw_auto,
+		      u32 const *clk_modules_explicit_en,
 		      u8 wait_for_enable);
 const struct dpll_params *get_mpu_dpll_params(void);
 const struct dpll_params *get_core_dpll_params(void);
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 9dce49ac4b..50e055ec67 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -271,7 +271,8 @@ struct omap_sys_ctrl_regs {
 #define OMAP5_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
 #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
 #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x18)
 
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 72e9df7881..2b3a071d2b 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -44,7 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void setup_clocks_for_console(void);
 void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap5_ddr_clk(void);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2a40b898e3..fcf9ce50d6 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,310 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+#include <common.h>
+
+struct prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 cm_clksel_abe;
+	u32 cm_dll_ctrl;
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_h11_dpll_core;
+	u32 cm_div_h12_dpll_core;
+	u32 cm_div_h13_dpll_core;
+	u32 cm_div_h14_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 cm_div_h22_dpllcore;
+	u32 cm_div_h23_dpll_core;
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 cm_div_h11_dpll_iva;
+	u32 cm_div_h12_dpll_iva;
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 cm_div_h11_dpll_ddrphy;
+	u32 cm_div_h12_dpll_ddrphy;
+	u32 cm_div_h13_dpll_ddrphy;
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 cm_shadow_freq_config1;
+	u32 cm_mpu_mpu_clkctrl;
+
+	/* cm1.dsp */
+	u32 cm_dsp_clkstctrl;
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 cm1_abe_clkstctrl;
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 cm1_abe_aess_clkctrl;
+	u32 cm1_abe_pdm_clkctrl;
+	u32 cm1_abe_dmic_clkctrl;
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 cm1_abe_timer5_clkctrl;
+	u32 cm1_abe_timer6_clkctrl;
+	u32 cm1_abe_timer7_clkctrl;
+	u32 cm1_abe_timer8_clkctrl;
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 cm_iva_dvfs_current;
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_h11_dpll_per;
+	u32 cm_div_h12_dpll_per;
+	u32 cm_div_h14_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+	/* cm2.core */
+	u32 cm_coreaon_bandgap_clkctrl;
+	u32 cm_l3_1_clkstctrl;
+	u32 cm_l3_1_dynamicdep;
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 cm_l3_2_clkstctrl;
+	u32 cm_l3_2_dynamicdep;
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 cm_l3_2_gpmc_clkctrl;
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 cm_sdma_sdma_clkctrl;
+	u32 cm_memif_clkstctrl;
+	u32 cm_memif_dmm_clkctrl;
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 cm_memif_emif_1_clkctrl;
+	u32 cm_memif_emif_2_clkctrl;
+	u32 cm_memif_dll_clkctrl;
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 cm_memif_dll_h_clkctrl;
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 cm_l4cfg_clkstctrl;
+	u32 cm_l4cfg_dynamicdep;
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 cm_l3instr_clkstctrl;
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+	/* cm2.ivahd */
+	u32 cm_ivahd_clkstctrl;
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 cm_cam_clkstctrl;
+	u32 cm_cam_iss_clkctrl;
+	u32 cm_cam_fdif_clkctrl;
+
+	/* cm2.dss */
+	u32 cm_dss_clkstctrl;
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 cm_sgx_clkstctrl;
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 cm_l3init_hsi_clkctrl;
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 cm_l3init_ocp2scp1_clkctrl;
+
+	/* cm2.l4per */
+	u32 cm_l4per_clkstctrl;
+	u32 cm_l4per_dynamicdep;
+	u32 cm_l4per_adc_clkctrl;
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 cm_l4per_elm_clkctrl;
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 cm_l4per_l4per_clkctrl;
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 cm_l4per_mgate_clkctrl;
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 cm_l4per_gpio7_clkctrl;
+	u32 cm_l4per_gpio8_clkctrl;
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_uart1_clkctrl;
+	u32 cm_l4per_uart2_clkctrl;
+	u32 cm_l4per_uart3_clkctrl;
+	u32 cm_l4per_uart4_clkctrl;
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 cm_l4per_uart5_clkctrl;
+	u32 cm_l4per_uart6_clkctrl;
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 cm_l4sec_rng_clkctrl;
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 cm_l4sec_cryptodma_clkctrl;
+
+	/* l4 wkup regs */
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 cm_wkup_clkstctrl;
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 cm_wkup_usim_clkctrl;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 cm_wkupaon_scrm_clkctrl;
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+	u32 prm_sldo_core_setup;
+	u32 prm_sldo_core_ctrl;
+	u32 prm_sldo_mpu_setup;
+	u32 prm_sldo_mpu_ctrl;
+	u32 prm_sldo_mm_setup;
+	u32 prm_sldo_mm_ctrl;
+
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_l3instr_intrconn_wp1_clkct;
+	u32 cm_l3init_usbphy_clkctrl;
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 prm_vc_cfg_channel;
+};
+
+extern struct prcm_regs const **prcm;
+extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap4_prcm;
+
+void hw_data_init(void);
 /* Max value for DPLL multiplier M */
 #define OMAP_DPLL_MAX_N	127