mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 15:12:04 +00:00
Merge branch '2023-05-04-assorted-TI-updates'
- Clean up / merge some defconfigs, update DDR timings and a few more assorted fixes.
This commit is contained in:
Tom Rini
commit
0160d58218
25 changed files with 181 additions and 913 deletions
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@ -1494,12 +1494,8 @@ F: configs/k2g_hs_evm_defconfig
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F: configs/k2l_hs_evm_defconfig
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F: configs/am65x_hs_evm_r5_defconfig
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F: configs/am65x_hs_evm_a53_defconfig
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F: configs/j7200_hs_evm_a72_defconfig
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F: configs/j7200_hs_evm_r5_defconfig
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F: configs/j721e_hs_evm_a72_defconfig
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F: configs/j721e_hs_evm_r5_defconfig
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F: configs/j721s2_hs_evm_a72_defconfig
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F: configs/j721s2_hs_evm_r5_defconfig
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TPM DRIVERS
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M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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@ -49,5 +49,3 @@
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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};
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#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
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@ -11,9 +11,6 @@
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#include "k3-am65-iot2050-common.dtsi"
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#include "k3-am65-iot2050-common-u-boot.dtsi"
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#include "k3-am65-iot2050-boot-image.dtsi"
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/ {
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memory@80000000 {
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device_type = "memory";
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11
arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi
Normal file
11
arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi
Normal file
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@ -0,0 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) Siemens AG, 2023
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*/
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#include "k3-am65-iot2050-common-u-boot.dtsi"
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#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
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#include "k3-am65-iot2050-boot-image.dtsi"
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10
arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi
Normal file
10
arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi
Normal file
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@ -0,0 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) Siemens AG, 2023
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*/
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#include "k3-am65-iot2050-common-u-boot.dtsi"
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#include "k3-am65-iot2050-boot-image.dtsi"
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@ -13,9 +13,6 @@
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#include "k3-am65-iot2050-common.dtsi"
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#include "k3-am65-iot2050-common-u-boot.dtsi"
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#include "k3-am65-iot2050-boot-image.dtsi"
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/ {
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memory@80000000 {
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device_type = "memory";
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1
arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi
Symbolic link
1
arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi
Symbolic link
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@ -0,0 +1 @@
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k3-am6528-iot2050-basic-pg2-u-boot.dtsi
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1
arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi
Symbolic link
1
arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi
Symbolic link
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@ -0,0 +1 @@
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k3-am6528-iot2050-basic-pg2-u-boot.dtsi
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1
arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi
Symbolic link
1
arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi
Symbolic link
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@ -0,0 +1 @@
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k3-am6528-iot2050-basic-u-boot.dtsi
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@ -1,12 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
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* This file was generated on 08/07/2020
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* Includes hand-edits
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*/
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* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
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* This file was generated on 06/01/2021
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*/
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#define DDRSS_PLL_FHS_CNT 10
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#define DDRSS_PLL_FREQUENCY_0 27500000
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#define DDRSS_PLL_FREQUENCY_1 666500000
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#define DDRSS_PLL_FREQUENCY_2 666500000
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@ -17,10 +17,10 @@
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#define DDRSS_CTL_04_DATA 0x00000000
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#define DDRSS_CTL_05_DATA 0x00000000
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#define DDRSS_CTL_06_DATA 0x00000000
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#define DDRSS_CTL_07_DATA 0x00002710
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#define DDRSS_CTL_08_DATA 0x000186A0
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#define DDRSS_CTL_07_DATA 0x00002AF8
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#define DDRSS_CTL_08_DATA 0x0001ADAF
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#define DDRSS_CTL_09_DATA 0x00000005
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#define DDRSS_CTL_10_DATA 0x00000064
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#define DDRSS_CTL_10_DATA 0x0000006E
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#define DDRSS_CTL_11_DATA 0x000411AB
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#define DDRSS_CTL_12_DATA 0x0028B0AB
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#define DDRSS_CTL_13_DATA 0x00000005
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@ -33,11 +33,11 @@
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#define DDRSS_CTL_20_DATA 0x02011001
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#define DDRSS_CTL_21_DATA 0x02010000
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#define DDRSS_CTL_22_DATA 0x00020100
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#define DDRSS_CTL_23_DATA 0x0000000A
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#define DDRSS_CTL_24_DATA 0x00000019
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#define DDRSS_CTL_23_DATA 0x0000000B
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#define DDRSS_CTL_24_DATA 0x0000001C
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#define DDRSS_CTL_25_DATA 0x00000000
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#define DDRSS_CTL_26_DATA 0x00000000
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#define DDRSS_CTL_27_DATA 0x02020200
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#define DDRSS_CTL_27_DATA 0x03020200
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#define DDRSS_CTL_28_DATA 0x00003636
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#define DDRSS_CTL_29_DATA 0x00100000
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#define DDRSS_CTL_30_DATA 0x00000000
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@ -54,7 +54,7 @@
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#define DDRSS_CTL_41_DATA 0x113C0057
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#define DDRSS_CTL_42_DATA 0x2000291B
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#define DDRSS_CTL_43_DATA 0x000A0A09
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#define DDRSS_CTL_44_DATA 0x040006DB
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#define DDRSS_CTL_44_DATA 0x0400078A
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#define DDRSS_CTL_45_DATA 0x130E0B04
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#define DDRSS_CTL_46_DATA 0x0A00B6D0
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#define DDRSS_CTL_47_DATA 0x130E0B0A
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@ -62,7 +62,7 @@
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#define DDRSS_CTL_49_DATA 0x0203040A
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#define DDRSS_CTL_50_DATA 0x1C040500
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#define DDRSS_CTL_51_DATA 0x081D1C1D
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#define DDRSS_CTL_52_DATA 0x14000D0A
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#define DDRSS_CTL_52_DATA 0x14000E0A
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#define DDRSS_CTL_53_DATA 0x02010A0A
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#define DDRSS_CTL_54_DATA 0x01010002
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#define DDRSS_CTL_55_DATA 0x04383808
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@ -70,15 +70,15 @@
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#define DDRSS_CTL_57_DATA 0x00001F1F
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#define DDRSS_CTL_58_DATA 0x00010100
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#define DDRSS_CTL_59_DATA 0x03010000
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#define DDRSS_CTL_60_DATA 0x00000E08
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#define DDRSS_CTL_61_DATA 0x000000BB
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#define DDRSS_CTL_60_DATA 0x00001008
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#define DDRSS_CTL_61_DATA 0x000000CE
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#define DDRSS_CTL_62_DATA 0x00000176
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#define DDRSS_CTL_63_DATA 0x00001448
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#define DDRSS_CTL_64_DATA 0x00000176
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#define DDRSS_CTL_65_DATA 0x00001448
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#define DDRSS_CTL_66_DATA 0x00000005
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#define DDRSS_CTL_67_DATA 0x00030000
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#define DDRSS_CTL_68_DATA 0x005D0010
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#define DDRSS_CTL_67_DATA 0x00040000
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#define DDRSS_CTL_68_DATA 0x005D0012
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#define DDRSS_CTL_69_DATA 0x005D0282
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#define DDRSS_CTL_70_DATA 0x00400282
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#define DDRSS_CTL_71_DATA 0x00120103
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@ -89,7 +89,7 @@
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#define DDRSS_CTL_76_DATA 0x03130A07
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#define DDRSS_CTL_77_DATA 0x0A070301
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#define DDRSS_CTL_78_DATA 0x00010313
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#define DDRSS_CTL_79_DATA 0x000F000F
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#define DDRSS_CTL_79_DATA 0x00100010
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#define DDRSS_CTL_80_DATA 0x01800180
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#define DDRSS_CTL_81_DATA 0x01800180
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#define DDRSS_CTL_82_DATA 0x03050505
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@ -112,13 +112,13 @@
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#define DDRSS_CTL_99_DATA 0x00000000
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#define DDRSS_CTL_100_DATA 0x00040005
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#define DDRSS_CTL_101_DATA 0x00000000
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#define DDRSS_CTL_102_DATA 0x00002EC0
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#define DDRSS_CTL_103_DATA 0x00002EC0
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#define DDRSS_CTL_104_DATA 0x00002EC0
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#define DDRSS_CTL_105_DATA 0x00002EC0
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#define DDRSS_CTL_106_DATA 0x00002EC0
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#define DDRSS_CTL_102_DATA 0x00003380
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#define DDRSS_CTL_103_DATA 0x00003380
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#define DDRSS_CTL_104_DATA 0x00003380
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#define DDRSS_CTL_105_DATA 0x00003380
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#define DDRSS_CTL_106_DATA 0x00003380
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#define DDRSS_CTL_107_DATA 0x00000000
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#define DDRSS_CTL_108_DATA 0x0000051D
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#define DDRSS_CTL_108_DATA 0x000005A2
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#define DDRSS_CTL_109_DATA 0x00051200
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#define DDRSS_CTL_110_DATA 0x00051200
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#define DDRSS_CTL_111_DATA 0x00051200
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@ -174,9 +174,9 @@
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#define DDRSS_CTL_161_DATA 0x00000000
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#define DDRSS_CTL_162_DATA 0x00000000
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#define DDRSS_CTL_163_DATA 0x00000000
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#define DDRSS_CTL_164_DATA 0x000A0000
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#define DDRSS_CTL_165_DATA 0x000D0005
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#define DDRSS_CTL_166_DATA 0x000D0404
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#define DDRSS_CTL_164_DATA 0x000B0000
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#define DDRSS_CTL_165_DATA 0x000E0006
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#define DDRSS_CTL_166_DATA 0x000E0404
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#define DDRSS_CTL_167_DATA 0x0086010B
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#define DDRSS_CTL_168_DATA 0x0A0A014E
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#define DDRSS_CTL_169_DATA 0x010B014E
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@ -191,7 +191,7 @@
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#define DDRSS_CTL_178_DATA 0x36000000
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#define DDRSS_CTL_179_DATA 0x27270036
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#define DDRSS_CTL_180_DATA 0x0F0F0000
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#define DDRSS_CTL_181_DATA 0x00000000
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#define DDRSS_CTL_181_DATA 0x15000000
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#define DDRSS_CTL_182_DATA 0x00841515
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#define DDRSS_CTL_183_DATA 0x24C424C4
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#define DDRSS_CTL_184_DATA 0x2B2B2B00
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@ -199,7 +199,7 @@
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#define DDRSS_CTL_186_DATA 0x00363600
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#define DDRSS_CTL_187_DATA 0x00002727
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#define DDRSS_CTL_188_DATA 0x00000F0F
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#define DDRSS_CTL_189_DATA 0x15150000
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#define DDRSS_CTL_189_DATA 0x15151500
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#define DDRSS_CTL_190_DATA 0x00000020
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#define DDRSS_CTL_191_DATA 0x00000000
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#define DDRSS_CTL_192_DATA 0x00000001
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@ -268,7 +268,7 @@
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#define DDRSS_CTL_255_DATA 0x00000000
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#define DDRSS_CTL_256_DATA 0x00000000
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#define DDRSS_CTL_257_DATA 0x01000200
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#define DDRSS_CTL_258_DATA 0x00320040
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#define DDRSS_CTL_258_DATA 0x00370040
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#define DDRSS_CTL_259_DATA 0x00020008
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#define DDRSS_CTL_260_DATA 0x00400100
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#define DDRSS_CTL_261_DATA 0x00280536
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@ -399,13 +399,13 @@
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#define DDRSS_CTL_386_DATA 0x00000000
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#define DDRSS_CTL_387_DATA 0x2E2E1B00
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#define DDRSS_CTL_388_DATA 0x000A0000
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#define DDRSS_CTL_389_DATA 0x00000176
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#define DDRSS_CTL_389_DATA 0x0000019C
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#define DDRSS_CTL_390_DATA 0x00000200
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#define DDRSS_CTL_391_DATA 0x00000200
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#define DDRSS_CTL_392_DATA 0x00000200
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#define DDRSS_CTL_393_DATA 0x00000200
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#define DDRSS_CTL_394_DATA 0x00000462
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#define DDRSS_CTL_395_DATA 0x00000E9C
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#define DDRSS_CTL_394_DATA 0x000004D4
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#define DDRSS_CTL_395_DATA 0x00001018
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#define DDRSS_CTL_396_DATA 0x00000204
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#define DDRSS_CTL_397_DATA 0x00002890
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#define DDRSS_CTL_398_DATA 0x00000200
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@ -432,7 +432,7 @@
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#define DDRSS_CTL_419_DATA 0x00000000
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#define DDRSS_CTL_420_DATA 0x00000000
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#define DDRSS_CTL_421_DATA 0x00030000
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#define DDRSS_CTL_422_DATA 0x0006001E
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#define DDRSS_CTL_422_DATA 0x0007001F
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#define DDRSS_CTL_423_DATA 0x0013002B
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#define DDRSS_CTL_424_DATA 0x0013002B
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#define DDRSS_CTL_425_DATA 0x00000000
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@ -633,14 +633,14 @@
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#define DDRSS_PI_160_DATA 0x00000000
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#define DDRSS_PI_161_DATA 0x00010000
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#define DDRSS_PI_162_DATA 0x00000000
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#define DDRSS_PI_163_DATA 0x1B1B0100
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#define DDRSS_PI_163_DATA 0x1B1B0200
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#define DDRSS_PI_164_DATA 0x00000034
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#define DDRSS_PI_165_DATA 0x00000051
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#define DDRSS_PI_166_DATA 0x00020051
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#define DDRSS_PI_167_DATA 0x02000200
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#define DDRSS_PI_168_DATA 0x300C0C04
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#define DDRSS_PI_169_DATA 0x000E300C
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#define DDRSS_PI_170_DATA 0x000000BB
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#define DDRSS_PI_169_DATA 0x0010300C
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#define DDRSS_PI_170_DATA 0x000000CE
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#define DDRSS_PI_171_DATA 0x00000176
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#define DDRSS_PI_172_DATA 0x00001448
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#define DDRSS_PI_173_DATA 0x00000176
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@ -658,14 +658,14 @@
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#define DDRSS_PI_185_DATA 0x0E040100
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#define DDRSS_PI_186_DATA 0x0808020E
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#define DDRSS_PI_187_DATA 0x00040402
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#define DDRSS_PI_188_DATA 0x000C8034
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#define DDRSS_PI_188_DATA 0x000D0035
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#define DDRSS_PI_189_DATA 0x00198041
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#define DDRSS_PI_190_DATA 0x00198041
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#define DDRSS_PI_191_DATA 0x01010101
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#define DDRSS_PI_192_DATA 0x0002000D
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#define DDRSS_PI_192_DATA 0x0002000E
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#define DDRSS_PI_193_DATA 0x0002014E
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#define DDRSS_PI_194_DATA 0x0100014E
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#define DDRSS_PI_195_DATA 0x000E000E
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#define DDRSS_PI_195_DATA 0x000F000F
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#define DDRSS_PI_196_DATA 0x014F0100
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#define DDRSS_PI_197_DATA 0x0100014F
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#define DDRSS_PI_198_DATA 0x014F014F
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@ -678,7 +678,7 @@
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#define DDRSS_PI_205_DATA 0x00C01000
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#define DDRSS_PI_206_DATA 0x00C01000
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#define DDRSS_PI_207_DATA 0x00021000
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#define DDRSS_PI_208_DATA 0x001C000D
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#define DDRSS_PI_208_DATA 0x001C000E
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#define DDRSS_PI_209_DATA 0x001C014E
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#define DDRSS_PI_210_DATA 0x0011014E
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#define DDRSS_PI_211_DATA 0x32000056
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@ -689,7 +689,7 @@
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#define DDRSS_PI_216_DATA 0x3212005A
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#define DDRSS_PI_217_DATA 0x09000301
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#define DDRSS_PI_218_DATA 0x04010504
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#define DDRSS_PI_219_DATA 0x0400062B
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#define DDRSS_PI_219_DATA 0x040006C9
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#define DDRSS_PI_220_DATA 0x0A032001
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#define DDRSS_PI_221_DATA 0x1C1F0B0A
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#define DDRSS_PI_222_DATA 0x00001D12
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@ -699,43 +699,43 @@
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#define DDRSS_PI_226_DATA 0x00001D12
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#define DDRSS_PI_227_DATA 0x3C00A488
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#define DDRSS_PI_228_DATA 0x13142005
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#define DDRSS_PI_229_DATA 0x0001760E
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#define DDRSS_PI_230_DATA 0x00000E9C
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#define DDRSS_PI_229_DATA 0x00019C0E
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#define DDRSS_PI_230_DATA 0x00001018
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#define DDRSS_PI_231_DATA 0x00002890
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#define DDRSS_PI_232_DATA 0x000195A0
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#define DDRSS_PI_233_DATA 0x00002890
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#define DDRSS_PI_234_DATA 0x000195A0
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#define DDRSS_PI_235_DATA 0x0180000F
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#define DDRSS_PI_235_DATA 0x01800010
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#define DDRSS_PI_236_DATA 0x03030180
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#define DDRSS_PI_237_DATA 0x00271003
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#define DDRSS_PI_238_DATA 0x000186A0
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#define DDRSS_PI_237_DATA 0x002AF803
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#define DDRSS_PI_238_DATA 0x0001ADAF
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#define DDRSS_PI_239_DATA 0x00000005
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#define DDRSS_PI_240_DATA 0x00000064
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#define DDRSS_PI_241_DATA 0x0000000F
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#define DDRSS_PI_240_DATA 0x0000006E
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#define DDRSS_PI_241_DATA 0x00000010
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#define DDRSS_PI_242_DATA 0x000411AB
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#define DDRSS_PI_243_DATA 0x000186A0
|
||||
#define DDRSS_PI_243_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_244_DATA 0x00000005
|
||||
#define DDRSS_PI_245_DATA 0x00000A6B
|
||||
#define DDRSS_PI_246_DATA 0x00000180
|
||||
#define DDRSS_PI_247_DATA 0x000411AB
|
||||
#define DDRSS_PI_248_DATA 0x000186A0
|
||||
#define DDRSS_PI_248_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_249_DATA 0x00000005
|
||||
#define DDRSS_PI_250_DATA 0x00000A6B
|
||||
#define DDRSS_PI_251_DATA 0x01000180
|
||||
#define DDRSS_PI_252_DATA 0x00320040
|
||||
#define DDRSS_PI_252_DATA 0x00370040
|
||||
#define DDRSS_PI_253_DATA 0x00010008
|
||||
#define DDRSS_PI_254_DATA 0x05360040
|
||||
#define DDRSS_PI_255_DATA 0x00010028
|
||||
#define DDRSS_PI_256_DATA 0x05360040
|
||||
#define DDRSS_PI_257_DATA 0x00000328
|
||||
#define DDRSS_PI_258_DATA 0x00430043
|
||||
#define DDRSS_PI_259_DATA 0x00040404
|
||||
#define DDRSS_PI_259_DATA 0x08040404
|
||||
#define DDRSS_PI_260_DATA 0x00000055
|
||||
#define DDRSS_PI_261_DATA 0x55003C5A
|
||||
#define DDRSS_PI_261_DATA 0x55083C5A
|
||||
#define DDRSS_PI_262_DATA 0x5A000000
|
||||
#define DDRSS_PI_263_DATA 0x0055003C
|
||||
#define DDRSS_PI_263_DATA 0x0055083C
|
||||
#define DDRSS_PI_264_DATA 0x3C5A0000
|
||||
#define DDRSS_PI_265_DATA 0x00005500
|
||||
#define DDRSS_PI_265_DATA 0x00005508
|
||||
#define DDRSS_PI_266_DATA 0x0C3C5A00
|
||||
#define DDRSS_PI_267_DATA 0x080F0E0D
|
||||
#define DDRSS_PI_268_DATA 0x000B0A09
|
||||
|
|
@ -879,7 +879,7 @@
|
|||
#define DDRSS_PHY_105_DATA 0x0F0C2701
|
||||
#define DDRSS_PHY_106_DATA 0x01000140
|
||||
#define DDRSS_PHY_107_DATA 0x04000420
|
||||
#define DDRSS_PHY_108_DATA 0x00000255
|
||||
#define DDRSS_PHY_108_DATA 0x00000198
|
||||
#define DDRSS_PHY_109_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_110_DATA 0x00030200
|
||||
#define DDRSS_PHY_111_DATA 0x02800000
|
||||
|
|
@ -1135,7 +1135,7 @@
|
|||
#define DDRSS_PHY_361_DATA 0x0F0C2701
|
||||
#define DDRSS_PHY_362_DATA 0x01000140
|
||||
#define DDRSS_PHY_363_DATA 0x04000420
|
||||
#define DDRSS_PHY_364_DATA 0x00000255
|
||||
#define DDRSS_PHY_364_DATA 0x00000198
|
||||
#define DDRSS_PHY_365_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_366_DATA 0x00030200
|
||||
#define DDRSS_PHY_367_DATA 0x02800000
|
||||
|
|
@ -1391,7 +1391,7 @@
|
|||
#define DDRSS_PHY_617_DATA 0x0F0C2701
|
||||
#define DDRSS_PHY_618_DATA 0x01000140
|
||||
#define DDRSS_PHY_619_DATA 0x04000420
|
||||
#define DDRSS_PHY_620_DATA 0x00000255
|
||||
#define DDRSS_PHY_620_DATA 0x00000198
|
||||
#define DDRSS_PHY_621_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_622_DATA 0x00030200
|
||||
#define DDRSS_PHY_623_DATA 0x02800000
|
||||
|
|
@ -1647,7 +1647,7 @@
|
|||
#define DDRSS_PHY_873_DATA 0x0F0C2701
|
||||
#define DDRSS_PHY_874_DATA 0x01000140
|
||||
#define DDRSS_PHY_875_DATA 0x04000420
|
||||
#define DDRSS_PHY_876_DATA 0x00000255
|
||||
#define DDRSS_PHY_876_DATA 0x00000198
|
||||
#define DDRSS_PHY_877_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_878_DATA 0x00030200
|
||||
#define DDRSS_PHY_879_DATA 0x02800000
|
||||
|
|
@ -2081,7 +2081,7 @@
|
|||
#define DDRSS_PHY_1307_DATA 0x01200F02
|
||||
#define DDRSS_PHY_1308_DATA 0x00194280
|
||||
#define DDRSS_PHY_1309_DATA 0x00000004
|
||||
#define DDRSS_PHY_1310_DATA 0x00050000
|
||||
#define DDRSS_PHY_1310_DATA 0x00052000
|
||||
#define DDRSS_PHY_1311_DATA 0x00000000
|
||||
#define DDRSS_PHY_1312_DATA 0x00000000
|
||||
#define DDRSS_PHY_1313_DATA 0x00000000
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
|
||||
* This file was generated on 09/25/2020
|
||||
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
|
||||
* This file was generated on 07/17/2022
|
||||
*/
|
||||
|
||||
#define DDRSS_PLL_FHS_CNT 10
|
||||
#define DDRSS_PLL_FREQUENCY_0 27500000
|
||||
#define DDRSS_PLL_FREQUENCY_1 1066500000
|
||||
#define DDRSS_PLL_FREQUENCY_2 1066500000
|
||||
|
||||
|
|
@ -16,10 +17,10 @@
|
|||
#define DDRSS_CTL_04_DATA 0x00000000
|
||||
#define DDRSS_CTL_05_DATA 0x00000000
|
||||
#define DDRSS_CTL_06_DATA 0x00000000
|
||||
#define DDRSS_CTL_07_DATA 0x00002710
|
||||
#define DDRSS_CTL_08_DATA 0x000186A0
|
||||
#define DDRSS_CTL_07_DATA 0x00002AF8
|
||||
#define DDRSS_CTL_08_DATA 0x0001ADAF
|
||||
#define DDRSS_CTL_09_DATA 0x00000005
|
||||
#define DDRSS_CTL_10_DATA 0x00000064
|
||||
#define DDRSS_CTL_10_DATA 0x0000006E
|
||||
#define DDRSS_CTL_11_DATA 0x000681C8
|
||||
#define DDRSS_CTL_12_DATA 0x004111C9
|
||||
#define DDRSS_CTL_13_DATA 0x00000005
|
||||
|
|
@ -32,11 +33,11 @@
|
|||
#define DDRSS_CTL_20_DATA 0x02011001
|
||||
#define DDRSS_CTL_21_DATA 0x02010000
|
||||
#define DDRSS_CTL_22_DATA 0x00020100
|
||||
#define DDRSS_CTL_23_DATA 0x0000000A
|
||||
#define DDRSS_CTL_24_DATA 0x00000019
|
||||
#define DDRSS_CTL_23_DATA 0x0000000B
|
||||
#define DDRSS_CTL_24_DATA 0x0000001C
|
||||
#define DDRSS_CTL_25_DATA 0x00000000
|
||||
#define DDRSS_CTL_26_DATA 0x00000000
|
||||
#define DDRSS_CTL_27_DATA 0x02020200
|
||||
#define DDRSS_CTL_27_DATA 0x03020200
|
||||
#define DDRSS_CTL_28_DATA 0x00005656
|
||||
#define DDRSS_CTL_29_DATA 0x00100000
|
||||
#define DDRSS_CTL_30_DATA 0x00000000
|
||||
|
|
@ -53,7 +54,7 @@
|
|||
#define DDRSS_CTL_41_DATA 0x1B60008B
|
||||
#define DDRSS_CTL_42_DATA 0x2000422B
|
||||
#define DDRSS_CTL_43_DATA 0x000A0A09
|
||||
#define DDRSS_CTL_44_DATA 0x040006DB
|
||||
#define DDRSS_CTL_44_DATA 0x0400078A
|
||||
#define DDRSS_CTL_45_DATA 0x1E161104
|
||||
#define DDRSS_CTL_46_DATA 0x10012458
|
||||
#define DDRSS_CTL_47_DATA 0x1E161110
|
||||
|
|
@ -61,7 +62,7 @@
|
|||
#define DDRSS_CTL_49_DATA 0x02030410
|
||||
#define DDRSS_CTL_50_DATA 0x2C040500
|
||||
#define DDRSS_CTL_51_DATA 0x082D2C2D
|
||||
#define DDRSS_CTL_52_DATA 0x14000D0A
|
||||
#define DDRSS_CTL_52_DATA 0x14000E0A
|
||||
#define DDRSS_CTL_53_DATA 0x04010A0A
|
||||
#define DDRSS_CTL_54_DATA 0x01010004
|
||||
#define DDRSS_CTL_55_DATA 0x04585808
|
||||
|
|
@ -69,15 +70,15 @@
|
|||
#define DDRSS_CTL_57_DATA 0x00003131
|
||||
#define DDRSS_CTL_58_DATA 0x00010100
|
||||
#define DDRSS_CTL_59_DATA 0x03010000
|
||||
#define DDRSS_CTL_60_DATA 0x00000E08
|
||||
#define DDRSS_CTL_61_DATA 0x000000BB
|
||||
#define DDRSS_CTL_60_DATA 0x00001008
|
||||
#define DDRSS_CTL_61_DATA 0x000000CE
|
||||
#define DDRSS_CTL_62_DATA 0x00000256
|
||||
#define DDRSS_CTL_63_DATA 0x00002073
|
||||
#define DDRSS_CTL_64_DATA 0x00000256
|
||||
#define DDRSS_CTL_65_DATA 0x00002073
|
||||
#define DDRSS_CTL_66_DATA 0x00000005
|
||||
#define DDRSS_CTL_67_DATA 0x00030000
|
||||
#define DDRSS_CTL_68_DATA 0x00950010
|
||||
#define DDRSS_CTL_67_DATA 0x00040000
|
||||
#define DDRSS_CTL_68_DATA 0x00950012
|
||||
#define DDRSS_CTL_69_DATA 0x00950408
|
||||
#define DDRSS_CTL_70_DATA 0x00400408
|
||||
#define DDRSS_CTL_71_DATA 0x00120103
|
||||
|
|
@ -88,7 +89,7 @@
|
|||
#define DDRSS_CTL_76_DATA 0x041E100B
|
||||
#define DDRSS_CTL_77_DATA 0x100B0401
|
||||
#define DDRSS_CTL_78_DATA 0x0001041E
|
||||
#define DDRSS_CTL_79_DATA 0x000F000F
|
||||
#define DDRSS_CTL_79_DATA 0x00100010
|
||||
#define DDRSS_CTL_80_DATA 0x02660266
|
||||
#define DDRSS_CTL_81_DATA 0x02660266
|
||||
#define DDRSS_CTL_82_DATA 0x03050505
|
||||
|
|
@ -111,13 +112,13 @@
|
|||
#define DDRSS_CTL_99_DATA 0x00000000
|
||||
#define DDRSS_CTL_100_DATA 0x00040005
|
||||
#define DDRSS_CTL_101_DATA 0x00000000
|
||||
#define DDRSS_CTL_102_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_103_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_104_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_105_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_106_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_102_DATA 0x00003380
|
||||
#define DDRSS_CTL_103_DATA 0x00003380
|
||||
#define DDRSS_CTL_104_DATA 0x00003380
|
||||
#define DDRSS_CTL_105_DATA 0x00003380
|
||||
#define DDRSS_CTL_106_DATA 0x00003380
|
||||
#define DDRSS_CTL_107_DATA 0x00000000
|
||||
#define DDRSS_CTL_108_DATA 0x0000051D
|
||||
#define DDRSS_CTL_108_DATA 0x000005A2
|
||||
#define DDRSS_CTL_109_DATA 0x00081CC0
|
||||
#define DDRSS_CTL_110_DATA 0x00081CC0
|
||||
#define DDRSS_CTL_111_DATA 0x00081CC0
|
||||
|
|
@ -173,9 +174,9 @@
|
|||
#define DDRSS_CTL_161_DATA 0x00000000
|
||||
#define DDRSS_CTL_162_DATA 0x00000000
|
||||
#define DDRSS_CTL_163_DATA 0x00000000
|
||||
#define DDRSS_CTL_164_DATA 0x000A0000
|
||||
#define DDRSS_CTL_165_DATA 0x000D0005
|
||||
#define DDRSS_CTL_166_DATA 0x000D0404
|
||||
#define DDRSS_CTL_164_DATA 0x000B0000
|
||||
#define DDRSS_CTL_165_DATA 0x000E0006
|
||||
#define DDRSS_CTL_166_DATA 0x000E0404
|
||||
#define DDRSS_CTL_167_DATA 0x00D601AB
|
||||
#define DDRSS_CTL_168_DATA 0x10100216
|
||||
#define DDRSS_CTL_169_DATA 0x01AB0216
|
||||
|
|
@ -190,15 +191,15 @@
|
|||
#define DDRSS_CTL_178_DATA 0x56000000
|
||||
#define DDRSS_CTL_179_DATA 0x27270056
|
||||
#define DDRSS_CTL_180_DATA 0x0F0F0000
|
||||
#define DDRSS_CTL_181_DATA 0x00000000
|
||||
#define DDRSS_CTL_182_DATA 0x00840606
|
||||
#define DDRSS_CTL_181_DATA 0x16000000
|
||||
#define DDRSS_CTL_182_DATA 0x00841616
|
||||
#define DDRSS_CTL_183_DATA 0x3FF43FF4
|
||||
#define DDRSS_CTL_184_DATA 0x33333300
|
||||
#define DDRSS_CTL_185_DATA 0x00000000
|
||||
#define DDRSS_CTL_186_DATA 0x00565600
|
||||
#define DDRSS_CTL_187_DATA 0x00002727
|
||||
#define DDRSS_CTL_188_DATA 0x00000F0F
|
||||
#define DDRSS_CTL_189_DATA 0x06060000
|
||||
#define DDRSS_CTL_189_DATA 0x16161600
|
||||
#define DDRSS_CTL_190_DATA 0x00000020
|
||||
#define DDRSS_CTL_191_DATA 0x00000000
|
||||
#define DDRSS_CTL_192_DATA 0x00000001
|
||||
|
|
@ -238,17 +239,17 @@
|
|||
#define DDRSS_CTL_226_DATA 0x00000000
|
||||
#define DDRSS_CTL_227_DATA 0x15110000
|
||||
#define DDRSS_CTL_228_DATA 0x00040C18
|
||||
#define DDRSS_CTL_229_DATA 0x00000000
|
||||
#define DDRSS_CTL_230_DATA 0x00000000
|
||||
#define DDRSS_CTL_229_DATA 0xF000C000
|
||||
#define DDRSS_CTL_230_DATA 0x0000F000
|
||||
#define DDRSS_CTL_231_DATA 0x00000000
|
||||
#define DDRSS_CTL_232_DATA 0x00000000
|
||||
#define DDRSS_CTL_233_DATA 0x00000000
|
||||
#define DDRSS_CTL_234_DATA 0x00000000
|
||||
#define DDRSS_CTL_233_DATA 0xC0000000
|
||||
#define DDRSS_CTL_234_DATA 0xF000F000
|
||||
#define DDRSS_CTL_235_DATA 0x00000000
|
||||
#define DDRSS_CTL_236_DATA 0x00000000
|
||||
#define DDRSS_CTL_237_DATA 0x00000000
|
||||
#define DDRSS_CTL_238_DATA 0x00000000
|
||||
#define DDRSS_CTL_239_DATA 0x00000000
|
||||
#define DDRSS_CTL_238_DATA 0xF000C000
|
||||
#define DDRSS_CTL_239_DATA 0x0000F000
|
||||
#define DDRSS_CTL_240_DATA 0x00000000
|
||||
#define DDRSS_CTL_241_DATA 0x00000000
|
||||
#define DDRSS_CTL_242_DATA 0x00030000
|
||||
|
|
@ -267,7 +268,7 @@
|
|||
#define DDRSS_CTL_255_DATA 0x00000000
|
||||
#define DDRSS_CTL_256_DATA 0x00000000
|
||||
#define DDRSS_CTL_257_DATA 0x01000200
|
||||
#define DDRSS_CTL_258_DATA 0x00320040
|
||||
#define DDRSS_CTL_258_DATA 0x00370040
|
||||
#define DDRSS_CTL_259_DATA 0x00020008
|
||||
#define DDRSS_CTL_260_DATA 0x00400100
|
||||
#define DDRSS_CTL_261_DATA 0x00400855
|
||||
|
|
@ -276,7 +277,7 @@
|
|||
#define DDRSS_CTL_264_DATA 0x00000040
|
||||
#define DDRSS_CTL_265_DATA 0x006B0003
|
||||
#define DDRSS_CTL_266_DATA 0x0100006B
|
||||
#define DDRSS_CTL_267_DATA 0x00000000
|
||||
#define DDRSS_CTL_267_DATA 0x03030303
|
||||
#define DDRSS_CTL_268_DATA 0x01010000
|
||||
#define DDRSS_CTL_269_DATA 0x00000202
|
||||
#define DDRSS_CTL_270_DATA 0x00000FFF
|
||||
|
|
@ -398,13 +399,13 @@
|
|||
#define DDRSS_CTL_386_DATA 0x00000000
|
||||
#define DDRSS_CTL_387_DATA 0x3A3A1B00
|
||||
#define DDRSS_CTL_388_DATA 0x000A0000
|
||||
#define DDRSS_CTL_389_DATA 0x00000176
|
||||
#define DDRSS_CTL_389_DATA 0x0000019C
|
||||
#define DDRSS_CTL_390_DATA 0x00000200
|
||||
#define DDRSS_CTL_391_DATA 0x00000200
|
||||
#define DDRSS_CTL_392_DATA 0x00000200
|
||||
#define DDRSS_CTL_393_DATA 0x00000200
|
||||
#define DDRSS_CTL_394_DATA 0x00000462
|
||||
#define DDRSS_CTL_395_DATA 0x00000E9C
|
||||
#define DDRSS_CTL_394_DATA 0x000004D4
|
||||
#define DDRSS_CTL_395_DATA 0x00001018
|
||||
#define DDRSS_CTL_396_DATA 0x00000204
|
||||
#define DDRSS_CTL_397_DATA 0x000040E6
|
||||
#define DDRSS_CTL_398_DATA 0x00000200
|
||||
|
|
@ -431,7 +432,7 @@
|
|||
#define DDRSS_CTL_419_DATA 0x00000000
|
||||
#define DDRSS_CTL_420_DATA 0x00000000
|
||||
#define DDRSS_CTL_421_DATA 0x00030000
|
||||
#define DDRSS_CTL_422_DATA 0x0006001E
|
||||
#define DDRSS_CTL_422_DATA 0x0007001F
|
||||
#define DDRSS_CTL_423_DATA 0x001B0033
|
||||
#define DDRSS_CTL_424_DATA 0x001B0033
|
||||
#define DDRSS_CTL_425_DATA 0x00000000
|
||||
|
|
@ -632,14 +633,14 @@
|
|||
#define DDRSS_PI_160_DATA 0x00000000
|
||||
#define DDRSS_PI_161_DATA 0x00010000
|
||||
#define DDRSS_PI_162_DATA 0x00000000
|
||||
#define DDRSS_PI_163_DATA 0x2B2B0100
|
||||
#define DDRSS_PI_163_DATA 0x2B2B0200
|
||||
#define DDRSS_PI_164_DATA 0x00000034
|
||||
#define DDRSS_PI_165_DATA 0x00000064
|
||||
#define DDRSS_PI_166_DATA 0x00020064
|
||||
#define DDRSS_PI_167_DATA 0x02000200
|
||||
#define DDRSS_PI_168_DATA 0x48120C04
|
||||
#define DDRSS_PI_169_DATA 0x000E4812
|
||||
#define DDRSS_PI_170_DATA 0x000000BB
|
||||
#define DDRSS_PI_169_DATA 0x00104812
|
||||
#define DDRSS_PI_170_DATA 0x000000CE
|
||||
#define DDRSS_PI_171_DATA 0x00000256
|
||||
#define DDRSS_PI_172_DATA 0x00002073
|
||||
#define DDRSS_PI_173_DATA 0x00000256
|
||||
|
|
@ -657,14 +658,14 @@
|
|||
#define DDRSS_PI_185_DATA 0x15040000
|
||||
#define DDRSS_PI_186_DATA 0x0E0E0215
|
||||
#define DDRSS_PI_187_DATA 0x00040402
|
||||
#define DDRSS_PI_188_DATA 0x000C8034
|
||||
#define DDRSS_PI_188_DATA 0x000D0035
|
||||
#define DDRSS_PI_189_DATA 0x00218049
|
||||
#define DDRSS_PI_190_DATA 0x00218049
|
||||
#define DDRSS_PI_191_DATA 0x01010101
|
||||
#define DDRSS_PI_192_DATA 0x0004000D
|
||||
#define DDRSS_PI_192_DATA 0x0004000E
|
||||
#define DDRSS_PI_193_DATA 0x00040216
|
||||
#define DDRSS_PI_194_DATA 0x01000216
|
||||
#define DDRSS_PI_195_DATA 0x000E000E
|
||||
#define DDRSS_PI_195_DATA 0x000F000F
|
||||
#define DDRSS_PI_196_DATA 0x02170100
|
||||
#define DDRSS_PI_197_DATA 0x01000217
|
||||
#define DDRSS_PI_198_DATA 0x02170217
|
||||
|
|
@ -677,7 +678,7 @@
|
|||
#define DDRSS_PI_205_DATA 0x00C01000
|
||||
#define DDRSS_PI_206_DATA 0x00C01000
|
||||
#define DDRSS_PI_207_DATA 0x00021000
|
||||
#define DDRSS_PI_208_DATA 0x0024000D
|
||||
#define DDRSS_PI_208_DATA 0x0024000E
|
||||
#define DDRSS_PI_209_DATA 0x00240216
|
||||
#define DDRSS_PI_210_DATA 0x00110216
|
||||
#define DDRSS_PI_211_DATA 0x32000056
|
||||
|
|
@ -688,7 +689,7 @@
|
|||
#define DDRSS_PI_216_DATA 0x3212005B
|
||||
#define DDRSS_PI_217_DATA 0x09000301
|
||||
#define DDRSS_PI_218_DATA 0x04010504
|
||||
#define DDRSS_PI_219_DATA 0x0400062B
|
||||
#define DDRSS_PI_219_DATA 0x040006C9
|
||||
#define DDRSS_PI_220_DATA 0x0A032001
|
||||
#define DDRSS_PI_221_DATA 0x2C31110A
|
||||
#define DDRSS_PI_222_DATA 0x00002D1C
|
||||
|
|
@ -698,43 +699,43 @@
|
|||
#define DDRSS_PI_226_DATA 0x00002D1C
|
||||
#define DDRSS_PI_227_DATA 0x6001071C
|
||||
#define DDRSS_PI_228_DATA 0x1E202008
|
||||
#define DDRSS_PI_229_DATA 0x00017616
|
||||
#define DDRSS_PI_230_DATA 0x00000E9C
|
||||
#define DDRSS_PI_229_DATA 0x00019C16
|
||||
#define DDRSS_PI_230_DATA 0x00001018
|
||||
#define DDRSS_PI_231_DATA 0x000040E6
|
||||
#define DDRSS_PI_232_DATA 0x000288FC
|
||||
#define DDRSS_PI_233_DATA 0x000040E6
|
||||
#define DDRSS_PI_234_DATA 0x000288FC
|
||||
#define DDRSS_PI_235_DATA 0x0266000F
|
||||
#define DDRSS_PI_235_DATA 0x02660010
|
||||
#define DDRSS_PI_236_DATA 0x03030266
|
||||
#define DDRSS_PI_237_DATA 0x00271003
|
||||
#define DDRSS_PI_238_DATA 0x000186A0
|
||||
#define DDRSS_PI_237_DATA 0x002AF803
|
||||
#define DDRSS_PI_238_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_239_DATA 0x00000005
|
||||
#define DDRSS_PI_240_DATA 0x00000064
|
||||
#define DDRSS_PI_241_DATA 0x0000000F
|
||||
#define DDRSS_PI_240_DATA 0x0000006E
|
||||
#define DDRSS_PI_241_DATA 0x00000010
|
||||
#define DDRSS_PI_242_DATA 0x000681C8
|
||||
#define DDRSS_PI_243_DATA 0x000186A0
|
||||
#define DDRSS_PI_243_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_244_DATA 0x00000005
|
||||
#define DDRSS_PI_245_DATA 0x000010A9
|
||||
#define DDRSS_PI_246_DATA 0x00000266
|
||||
#define DDRSS_PI_247_DATA 0x000681C8
|
||||
#define DDRSS_PI_248_DATA 0x000186A0
|
||||
#define DDRSS_PI_248_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_249_DATA 0x00000005
|
||||
#define DDRSS_PI_250_DATA 0x000010A9
|
||||
#define DDRSS_PI_251_DATA 0x01000266
|
||||
#define DDRSS_PI_252_DATA 0x00320040
|
||||
#define DDRSS_PI_252_DATA 0x00370040
|
||||
#define DDRSS_PI_253_DATA 0x00010008
|
||||
#define DDRSS_PI_254_DATA 0x08550040
|
||||
#define DDRSS_PI_255_DATA 0x00010040
|
||||
#define DDRSS_PI_256_DATA 0x08550040
|
||||
#define DDRSS_PI_257_DATA 0x00000340
|
||||
#define DDRSS_PI_258_DATA 0x006B006B
|
||||
#define DDRSS_PI_259_DATA 0x00040404
|
||||
#define DDRSS_PI_259_DATA 0x08040404
|
||||
#define DDRSS_PI_260_DATA 0x00000055
|
||||
#define DDRSS_PI_261_DATA 0x55003C5A
|
||||
#define DDRSS_PI_261_DATA 0x55083C5A
|
||||
#define DDRSS_PI_262_DATA 0x5A000000
|
||||
#define DDRSS_PI_263_DATA 0x0055003C
|
||||
#define DDRSS_PI_263_DATA 0x0055083C
|
||||
#define DDRSS_PI_264_DATA 0x3C5A0000
|
||||
#define DDRSS_PI_265_DATA 0x00005500
|
||||
#define DDRSS_PI_265_DATA 0x00005508
|
||||
#define DDRSS_PI_266_DATA 0x0C3C5A00
|
||||
#define DDRSS_PI_267_DATA 0x080F0E0D
|
||||
#define DDRSS_PI_268_DATA 0x000B0A09
|
||||
|
|
@ -802,8 +803,8 @@
|
|||
#define DDRSS_PHY_29_DATA 0x00000808
|
||||
#define DDRSS_PHY_30_DATA 0x0F000000
|
||||
#define DDRSS_PHY_31_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_32_DATA 0x10200000
|
||||
#define DDRSS_PHY_33_DATA 0x0C002007
|
||||
#define DDRSS_PHY_32_DATA 0x10400000
|
||||
#define DDRSS_PHY_33_DATA 0x0C002006
|
||||
#define DDRSS_PHY_34_DATA 0x00000000
|
||||
#define DDRSS_PHY_35_DATA 0x00000000
|
||||
#define DDRSS_PHY_36_DATA 0x55555555
|
||||
|
|
@ -878,7 +879,7 @@
|
|||
#define DDRSS_PHY_105_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_106_DATA 0x01000140
|
||||
#define DDRSS_PHY_107_DATA 0x0C000420
|
||||
#define DDRSS_PHY_108_DATA 0x00000322
|
||||
#define DDRSS_PHY_108_DATA 0x00000198
|
||||
#define DDRSS_PHY_109_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_110_DATA 0x00030200
|
||||
#define DDRSS_PHY_111_DATA 0x02800000
|
||||
|
|
@ -1058,8 +1059,8 @@
|
|||
#define DDRSS_PHY_285_DATA 0x00000808
|
||||
#define DDRSS_PHY_286_DATA 0x0F000000
|
||||
#define DDRSS_PHY_287_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_288_DATA 0x10200000
|
||||
#define DDRSS_PHY_289_DATA 0x0C002007
|
||||
#define DDRSS_PHY_288_DATA 0x10400000
|
||||
#define DDRSS_PHY_289_DATA 0x0C002006
|
||||
#define DDRSS_PHY_290_DATA 0x00000000
|
||||
#define DDRSS_PHY_291_DATA 0x00000000
|
||||
#define DDRSS_PHY_292_DATA 0x55555555
|
||||
|
|
@ -1134,7 +1135,7 @@
|
|||
#define DDRSS_PHY_361_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_362_DATA 0x01000140
|
||||
#define DDRSS_PHY_363_DATA 0x0C000420
|
||||
#define DDRSS_PHY_364_DATA 0x00000322
|
||||
#define DDRSS_PHY_364_DATA 0x00000198
|
||||
#define DDRSS_PHY_365_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_366_DATA 0x00030200
|
||||
#define DDRSS_PHY_367_DATA 0x02800000
|
||||
|
|
@ -1314,8 +1315,8 @@
|
|||
#define DDRSS_PHY_541_DATA 0x00000808
|
||||
#define DDRSS_PHY_542_DATA 0x0F000000
|
||||
#define DDRSS_PHY_543_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_544_DATA 0x10200000
|
||||
#define DDRSS_PHY_545_DATA 0x0C002007
|
||||
#define DDRSS_PHY_544_DATA 0x10400000
|
||||
#define DDRSS_PHY_545_DATA 0x0C002006
|
||||
#define DDRSS_PHY_546_DATA 0x00000000
|
||||
#define DDRSS_PHY_547_DATA 0x00000000
|
||||
#define DDRSS_PHY_548_DATA 0x55555555
|
||||
|
|
@ -1390,7 +1391,7 @@
|
|||
#define DDRSS_PHY_617_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_618_DATA 0x01000140
|
||||
#define DDRSS_PHY_619_DATA 0x0C000420
|
||||
#define DDRSS_PHY_620_DATA 0x00000322
|
||||
#define DDRSS_PHY_620_DATA 0x00000198
|
||||
#define DDRSS_PHY_621_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_622_DATA 0x00030200
|
||||
#define DDRSS_PHY_623_DATA 0x02800000
|
||||
|
|
@ -1570,8 +1571,8 @@
|
|||
#define DDRSS_PHY_797_DATA 0x00000808
|
||||
#define DDRSS_PHY_798_DATA 0x0F000000
|
||||
#define DDRSS_PHY_799_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_800_DATA 0x10200000
|
||||
#define DDRSS_PHY_801_DATA 0x0C002007
|
||||
#define DDRSS_PHY_800_DATA 0x10400000
|
||||
#define DDRSS_PHY_801_DATA 0x0C002006
|
||||
#define DDRSS_PHY_802_DATA 0x00000000
|
||||
#define DDRSS_PHY_803_DATA 0x00000000
|
||||
#define DDRSS_PHY_804_DATA 0x55555555
|
||||
|
|
@ -1646,7 +1647,7 @@
|
|||
#define DDRSS_PHY_873_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_874_DATA 0x01000140
|
||||
#define DDRSS_PHY_875_DATA 0x0C000420
|
||||
#define DDRSS_PHY_876_DATA 0x00000322
|
||||
#define DDRSS_PHY_876_DATA 0x00000198
|
||||
#define DDRSS_PHY_877_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_878_DATA 0x00030200
|
||||
#define DDRSS_PHY_879_DATA 0x02800000
|
||||
|
|
@ -2080,7 +2081,7 @@
|
|||
#define DDRSS_PHY_1307_DATA 0x01200F02
|
||||
#define DDRSS_PHY_1308_DATA 0x00194280
|
||||
#define DDRSS_PHY_1309_DATA 0x00000004
|
||||
#define DDRSS_PHY_1310_DATA 0x00050000
|
||||
#define DDRSS_PHY_1310_DATA 0x00052000
|
||||
#define DDRSS_PHY_1311_DATA 0x00000000
|
||||
#define DDRSS_PHY_1312_DATA 0x00000000
|
||||
#define DDRSS_PHY_1313_DATA 0x00000000
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
|
|||
config SYS_K3_MCU_SCRATCHPAD_BASE
|
||||
hex
|
||||
default 0x40280000 if SOC_K3_AM654
|
||||
default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
|
||||
default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2
|
||||
help
|
||||
Describes the base address of MCU Scratchpad RAM.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x08000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x9000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_GPIO=y
|
||||
|
|
@ -34,7 +35,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x70000
|
||||
CONFIG_SPL_GPIO=y
|
||||
|
|
|
|||
|
|
@ -1,205 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SOC_K3_J721E=y
|
||||
CONFIG_TARGET_J7200_A72_EVM=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0x680000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_ENV_OFFSET_REDUND=0x6A0000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x80a00000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||
CONFIG_SPL_DMA=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
CONFIG_CMD_UFS=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_CCF=y
|
||||
CONFIG_CLK_TI_SCI=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
|
||||
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
|
||||
CONFIG_DMA_CHANNELS=y
|
||||
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_I2C_GPIO=y
|
||||
CONFIG_SYS_I2C_OMAP24XX=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ADMA=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_SHOW_PROGRESS=0
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_HBMC_AM654=y
|
||||
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MULTIPLEXER=y
|
||||
CONFIG_MUX_MMIO=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_TI_AM65_CPSW_NUSS=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_PHY_CADENCE_TORRENT=y
|
||||
CONFIG_PHY_J721E_WIZ=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_GENERIC is not set
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_REMOTEPROC_TI_K3_R5F=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_CADENCE_QSPI=y
|
||||
CONFIG_HAS_CQSPI_REF_CLK=y
|
||||
CONFIG_CQSPI_REF_CLK=133333333
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_TI_SCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_CDNS3=y
|
||||
CONFIG_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_CDNS3_HOST=y
|
||||
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
|
||||
CONFIG_UFS=y
|
||||
CONFIG_CADENCE_UFS=y
|
||||
CONFIG_TI_J721E_UFS=y
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x70000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SOC_K3_J721E=y
|
||||
CONFIG_K3_EARLY_CONS=y
|
||||
CONFIG_TARGET_J7200_R5_EVM=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
|
||||
CONFIG_SPL_TEXT_BASE=0x41c00000
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0xa000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
|
||||
CONFIG_SPL_EARLY_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
|
||||
CONFIG_SPL_DMA=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_REMOTEPROC=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_SPL_CLK_CCF=y
|
||||
CONFIG_SPL_CLK_K3_PLL=y
|
||||
CONFIG_SPL_CLK_K3=y
|
||||
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
|
||||
CONFIG_DMA_CHANNELS=y
|
||||
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||
CONFIG_SYS_I2C_OMAP24XX=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_FS_LOADER=y
|
||||
CONFIG_SPL_FS_LOADER=y
|
||||
CONFIG_K3_AVS0=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_SHOW_PROGRESS=0
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_HBMC_AM654=y
|
||||
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_GENERIC is not set
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_TI_POWER_DOMAIN=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_TPS65941=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_TPS65941=y
|
||||
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_CADENCE_QSPI=y
|
||||
CONFIG_HAS_CQSPI_REF_CLK=y
|
||||
CONFIG_CQSPI_REF_CLK=133333333
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_TI_SCI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_SPL_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_CDNS3=y
|
||||
CONFIG_USB_CDNS3_GADGET=y
|
||||
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_FS_EXT4=y
|
||||
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||
CONFIG_LIB_RATIONAL=y
|
||||
CONFIG_SPL_LIB_RATIONAL=y
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_GPIO=y
|
||||
|
|
@ -31,7 +32,7 @@ CONFIG_SPL_LOAD_FIT=y
|
|||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_SPL_GPIO=y
|
||||
|
|
|
|||
|
|
@ -1,212 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SOC_K3_J721S2=y
|
||||
CONFIG_TARGET_J721S2_A72_EVM=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0x680000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_ENV_OFFSET_REDUND=0x6A0000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x80a00000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||
CONFIG_SPL_DMA=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
|
||||
CONFIG_SPL_THERMAL=y
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
CONFIG_CMD_UFS=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_CCF=y
|
||||
CONFIG_CLK_TI_SCI=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
|
||||
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
|
||||
CONFIG_DMA_CHANNELS=y
|
||||
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_I2C_GPIO=y
|
||||
CONFIG_SYS_I2C_OMAP24XX=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ADMA=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_SHOW_PROGRESS=0
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_SOFT_RESET=y
|
||||
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MULTIPLEXER=y
|
||||
CONFIG_MUX_MMIO=y
|
||||
CONFIG_PHY_TI_DP83867=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_TI_AM65_CPSW_NUSS=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_PHY_CADENCE_TORRENT=y
|
||||
CONFIG_PHY_J721E_WIZ=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_GENERIC is not set
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_REMOTEPROC_TI_K3_DSP=y
|
||||
CONFIG_REMOTEPROC_TI_K3_R5F=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_CADENCE_QSPI=y
|
||||
CONFIG_HAS_CQSPI_REF_CLK=y
|
||||
CONFIG_CQSPI_REF_CLK=133333333
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_TI_SCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_CDNS3=y
|
||||
CONFIG_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_CDNS3_HOST=y
|
||||
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
|
||||
CONFIG_UFS=y
|
||||
CONFIG_CADENCE_UFS=y
|
||||
CONFIG_TI_J721E_UFS=y
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SOC_K3_J721S2=y
|
||||
CONFIG_K3_EARLY_CONS=y
|
||||
CONFIG_TARGET_J721S2_R5_EVM=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
|
||||
CONFIG_SPL_TEXT_BASE=0x41c00000
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x80000
|
||||
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x41c76000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0xa000
|
||||
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
|
||||
CONFIG_SPL_EARLY_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
|
||||
CONFIG_SPL_DMA=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_REMOTEPROC=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||
CONFIG_SPL_THERMAL=y
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_SPL_CLK_CCF=y
|
||||
CONFIG_SPL_CLK_K3_PLL=y
|
||||
CONFIG_SPL_CLK_K3=y
|
||||
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
|
||||
CONFIG_DMA_CHANNELS=y
|
||||
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||
CONFIG_SYS_I2C_OMAP24XX=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_FS_LOADER=y
|
||||
CONFIG_SPL_FS_LOADER=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_SHOW_PROGRESS=0
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_SOFT_RESET=y
|
||||
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_GENERIC is not set
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_POWER_DOMAIN=y
|
||||
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_CADENCE_QSPI=y
|
||||
CONFIG_HAS_CQSPI_REF_CLK=y
|
||||
CONFIG_CQSPI_REF_CLK=133333333
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_TI_SCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_SPL_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_CDNS3=y
|
||||
CONFIG_USB_CDNS3_GADGET=y
|
||||
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_FS_EXT4=y
|
||||
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||
CONFIG_PANIC_HANG=y
|
||||
CONFIG_LIB_RATIONAL=y
|
||||
CONFIG_SPL_LIB_RATIONAL=y
|
||||
|
|
@ -26,6 +26,9 @@
|
|||
#define ESM_MCU_EN BIT(6)
|
||||
#define ESM_MCU_ENDRV BIT(5)
|
||||
|
||||
#define ESM_MCU_MASK_REG 0x59
|
||||
#define ESM_MCU_MASK 0x7
|
||||
|
||||
/**
|
||||
* pmic_esm_probe: configures and enables PMIC ESM functionality
|
||||
*
|
||||
|
|
@ -48,6 +51,12 @@ static int pmic_esm_probe(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = pmic_reg_write(dev->parent, ESM_MCU_MASK_REG, ESM_MCU_MASK);
|
||||
if (ret) {
|
||||
dev_err(dev, "clearing ESM masks failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = pmic_reg_write(dev->parent, ESM_MCU_START_REG, ESM_MCU_START);
|
||||
if (ret) {
|
||||
dev_err(dev, "starting ESM failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -55,7 +55,8 @@
|
|||
"do;" \
|
||||
"setenv overlaystring ${overlaystring}'#'${overlay};" \
|
||||
"done;\0" \
|
||||
"run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}\0" \
|
||||
"get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}\0" \
|
||||
"run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}\0" \
|
||||
|
||||
/*
|
||||
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
|
||||
|
|
|
|||
|
|
@ -20,5 +20,6 @@ get_overlaystring=
|
|||
do;
|
||||
setenv overlaystring ${overlaystring}'#'${overlay};
|
||||
done;
|
||||
run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}
|
||||
get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}
|
||||
run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue