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doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Leo Yu-Chi Liang
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@ -256,3 +256,161 @@ the following command:
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Falcon Mode was presented at the RMLL 2012. Slides are available at:
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http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
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Falcon Mode Boot on RISC-V
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--------------------------
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Introduction
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~~~~~~~~~~~~
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In the RISC-V environment, OpenSBI is required to enable a supervisor mode
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binary to execute certain privileged operations. The typical boot sequence on
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RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start
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the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot
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proper. The OpenSBI binary must be prepared in advance of the U-Boot build
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process and it will be packed together with U-Boot into a file called
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u-boot.itb.
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The Falcon Mode on RISC-V platforms is a distinct boot sequence. Borrowing
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ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase
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in the normal boot process and allows OpenSBI to load and start the Linux
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kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI
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binary and Linux kernel binary must be prepared prior to the U-Boot build
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process and they will be packed together as a FIT image named linux.itb in
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this process.
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CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V.
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This configuration setting tells OpenSBI that Linux kernel is its next OS
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image and makes it load and start the kernel afterwards.
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Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot.
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If the Linux kernel expects hardware initializations by U-Boot, make sure to
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port the relevant code to the SPL build process.
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Configuration
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~~~~~~~~~~~~~
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CONFIG_SPL_LOAD_FIT_ADDRESS
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Specifies the address to load u-boot.itb in a normal boot. When the Falcon
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Mode boot is enabled, it specifies the load address of linux.itb.
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CONFIG_SYS_TEXT_BASE
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Specifies the address of the text section for a u-boot proper in a normal
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boot. When the Falcon Mode boot is enabled, it specifies the text section
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address for the Linux kernel image.
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CONFIG_SPL_PAYLOAD_ARGS_ADDR
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The address in the RAM to which the FDT blob is to be moved by the SPL.
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SPL places the FDT blob right after the kernel. As the kernel does not
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include the BSS section in its size calculation, SPL ends up placing
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the FDT blob within the BSS section of the kernel. This may cause the
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FDT blob to be cleared during kernel BSS initialization. To avoid the
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issue, be sure to move the FDT blob out of the kernel first.
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CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
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Activates the Falcon Mode boot on RISC-V.
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Example for Andes AE350 Board
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350
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platforms generally come with a builtin dtb. To load a custom DTB, follow
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these steps:
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1. Load the custom DTB to SDRAM::
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=> fatload mmc 0:1 0x20000000 user_custom.dtb
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2. Set the SPI speed::
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=> sf probe 0:0 50000000 0
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3. Erase sectors from the SPI Flash::
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=> sf erase 0xf0000 0x10000
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4. Write the FDT blob to the erased sectors of the Flash::
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=> sf write 0x20000000 0xf0000 0x10000
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Console Log of AE350 Falcon Mode Boot
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800)
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Trying to boot from RAM
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OpenSBI v1.2-51-g7304e42
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____ _____ ____ _____
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/ __ \ / ____| _ \_ _|
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| | | |_ __ ___ _ __ | (___ | |_) || |
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| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
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| |__| | |_) | __/ | | |____) | |_) || |_
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\____/| .__/ \___|_| |_|_____/|____/_____|
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Platform Name : andestech,ax25
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Platform Features : medeleg
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Platform HART Count : 1
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Platform IPI Device : andes_plicsw
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Platform Timer Device : andes_plmt @ 60000000Hz
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Platform Console Device : uart8250
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Platform HSM Device : andes_smu
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Platform PMU Device : andes_pmu
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Platform Reboot Device : atcwdt200
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Platform Shutdown Device : ---
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Firmware Base : 0x0
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Firmware Size : 196 KB
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Runtime SBI Version : 1.0
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Domain0 Name : root
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Domain0 Boot HART : 0
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Domain0 HARTs : 0*
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Domain0 Region00 : 0x0000000000000000-0x000000000003ffff ()
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Domain0 Region01 : 0x00000000e6000000-0x00000000e60fffff (I,R)
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Domain0 Region02 : 0x00000000e6400000-0x00000000e67fffff (I)
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Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
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Domain0 Next Address : 0x0000000001800000
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Domain0 Next Arg1 : 0x0000000001700000
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Domain0 Next Mode : S-mode
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Domain0 SysReset : yes
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Boot HART ID : 0
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Boot HART Domain : root
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Boot HART Priv Version : v1.11
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Boot HART Base ISA : rv64imafdcx
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Boot HART ISA Extensions : none
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Boot HART PMP Count : 8
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Boot HART PMP Granularity : 4
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Boot HART PMP Address Bits: 31
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Boot HART MHPM Count : 4
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Boot HART MHPM Bits : 64
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Boot HART MIDELEG : 0x0000000000000222
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Boot HART MEDELEG : 0x000000000000b109
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[ 0.000000] Linux version 6.1.47-09019-g0584b09ad862-dirty
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[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x1800000
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[ 0.000000] Machine model: andestech,ax25
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[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
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[ 0.000000] printk: bootconsole [sbi0] enabled
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[ 0.000000] Disabled 4-level and 5-level paging
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[ 0.000000] efi: UEFI not found.
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[ 0.000000] Zone ranges:
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[ 0.000000] DMA32 [mem 0x0000000001800000-0x000000003fffffff]
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[ 0.000000] Normal empty
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[ 0.000000] Movable zone start for each node
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[ 0.000000] Early memory node ranges
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[ 0.000000] node 0: [mem 0x0000000001800000-0x000000003fffffff]
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[ 0.000000] Initmem setup node 0 [mem 0x0000000001800000-0x000000003fffffff]
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[ 0.000000] SBI specification v1.0 detected
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[ 0.000000] SBI implementation ID=0x1 Version=0x10002
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[ 0.000000] SBI TIME extension detected
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[ 0.000000] SBI IPI extension detected
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[ 0.000000] SBI RFENCE extension detected
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[ 0.000000] SBI SRST extension detected
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[ 0.000000] SBI HSM extension detected
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[ 0.000000] riscv: base ISA extensions acim
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[ 0.000000] riscv: ELF capabilities acim
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[ 0.000000] percpu: Embedded 18 pages/cpu s35000 r8192 d30536 u73728
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[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 252500
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