Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-25 06:00:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse source 
Update and fixes for ls1088a, FMAN, ls1046ardb, ls1043ardb
sync ls1028ardb u-boot and Linux device-tree
This commit is contained in:
Tom Rini 2022-02-02 09:16:49 -05:00
commit 006fddde01
53 changed files with 2043 additions and 153 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
arch/arm/Kconfig
View file

@ -1776,6 +1776,21 @@ config TARGET_SL28
help
Support for Kontron SMARC-sAL28 board.
config TARGET_TEN64
bool "Support ten64"
select ARCH_LS1088A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
select GPIO_EXTRA_HEADER
help
Support for Traverse Technologies Ten64 board, based
on NXP LS1088A.
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA27X
@ -2225,6 +2240,7 @@ source "board/socionext/developerbox/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/traverse/ten64/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"

2
arch/arm/dts/Makefile
View file

@ -485,6 +485,8 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
fsl-ls1028a-kontron-sl28-var3.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb

1
arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
View file

@ -15,6 +15,7 @@
&enetc_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

1
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
View file

@ -14,6 +14,7 @@
&enetc_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
View file

@ -44,24 +44,28 @@
&mscc_felix_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
View file

@ -29,24 +29,28 @@
&mscc_felix_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
View file

@ -29,24 +29,28 @@
&mscc_felix_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
View file

@ -23,24 +23,28 @@
&mscc_felix_port0 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};

2
arch/arm/dts/fsl-ls1028a-qds.dtsi
View file

@ -195,7 +195,7 @@
status = "okay";
rtc@51 {
compatible = "pcf2127-rtc";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};

15
arch/arm/dts/fsl-ls1028a-rdb-u-boot.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2021 NXP */
/*
* u-boot will enable the device in the linux device tree in place. Because
* we are using the linux device tree, we have to enable the PCI controller
* ourselves.
*/
&pcie1 {
status = "okay";
};
&pcie2 {
status = "okay";
};

324
arch/arm/dts/fsl-ls1028a-rdb.dts
View file

@ -1,19 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* NXP ls1028ARDB device tree source
* Device Tree file for NXP LS1028A RDB Board.
*
* Copyright 2019 NXP
* Copyright 2018-2021 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "NXP Layerscape 1028a RDB Board";
model = "LS1028A RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
rtc1 = &ftm_alarm0;
spi0 = &fspi;
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port2;
@ -22,96 +30,83 @@
ethernet4 = &mscc_felix_port2;
ethernet5 = &mscc_felix_port3;
};
};
&dspi0 {
status = "okay";
};
&dspi1 {
status = "okay";
};
&dspi2 {
status = "okay";
};
&esdhc {
status = "okay";
};
&esdhc1 {
status = "okay";
mmc-hs200-1_8v;
};
&fspi {
status = "okay";
mt35xu02g0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
chosen {
stdout-path = "serial0:115200n8";
};
};
&i2c0 {
status = "okay";
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0000000>;
};
i2c-mux@77 {
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai4>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&sgtl5000>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&i2c1 {
&can0 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&i2c2 {
&can1 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&sata {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&duart0 {
@ -122,60 +117,158 @@
status = "okay";
};
&pcie1 {
status = "okay";
};
&enetc_mdio_pf3 {
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
&pcie2 {
status = "okay";
};
/* VSC8514 QSGMII quad PHY */
qsgmii_phy0: ethernet-phy@10 {
reg = <0x10>;
};
&usb0 {
status = "okay";
};
qsgmii_phy1: ethernet-phy@11 {
reg = <0x11>;
};
&usb1 {
status = "okay";
qsgmii_phy2: ethernet-phy@12 {
reg = <0x12>;
};
qsgmii_phy3: ethernet-phy@13 {
reg = <0x13>;
};
};
&enetc_port0 {
status = "okay";
phy-handle = <&sgmii_phy0>;
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;
managed = "in-band-status";
status = "okay";
};
&enetc_port2 {
status = "okay";
};
&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&fspi {
status = "okay";
mt35xu02g0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
reg = <0>;
};
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9847";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
sgtl5000: audio-codec@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
sclk-strength = <3>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
current-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
};
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
label = "swp0";
phy-handle = <&sw_phy0>;
managed = "in-band-status";
phy-handle = <&qsgmii_phy0>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port1 {
label = "swp1";
phy-handle = <&sw_phy1>;
managed = "in-band-status";
phy-handle = <&qsgmii_phy1>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port2 {
label = "swp2";
phy-handle = <&sw_phy2>;
managed = "in-band-status";
phy-handle = <&qsgmii_phy2>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port3 {
label = "swp3";
phy-handle = <&sw_phy3>;
managed = "in-band-status";
phy-handle = <&qsgmii_phy3>;
phy-mode = "qsgmii";
status = "okay";
};
@ -185,26 +278,23 @@
status = "okay";
};
&enetc_mdio_pf3 {
&optee {
status = "okay";
};
&sai4 {
status = "okay";
};
&sata {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
dr_mode = "otg";
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};
/* VSC8514 QSGMII PHY */
sw_phy0: phy@10 {
reg = <0x10>;
};
sw_phy1: phy@11 {
reg = <0x11>;
};
sw_phy2: phy@12 {
reg = <0x12>;
};
sw_phy3: phy@13 {
reg = <0x13>;
};
};

2
arch/arm/dts/fsl-ls1088a-qds.dtsi
View file

@ -88,7 +88,7 @@
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};

2
arch/arm/dts/fsl-ls1088a-rdb.dts
View file

@ -135,7 +135,7 @@
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};

377
arch/arm/dts/fsl-ls1088a-ten64.dts Normal file
View file

@ -0,0 +1,377 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Travese Ten64 (LS1088) board
* Based on fsl-ls1088a-rdb.dts
* Copyright 2017-2020 NXP
* Copyright 2019-2021 Traverse Technologies
*
* Author: Mathew McBride <matt@traverse.com.au>
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Traverse Ten64";
compatible = "traverse,ten64", "fsl,ls1088a";
aliases {
spi0 = &qspi;
};
chosen {
stdout-path = "serial0:115200n8";
};
buttons {
compatible = "gpio-keys";
/* Fired by system controller when
* external power off (e.g ATX Power Button)
* asserted
*/
powerdn {
label = "External Power Down";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
linux,code = <KEY_POWER>;
};
/* Rear Panel 'ADMIN' button (GPIO_H) */
admin {
label = "ADMIN button";
gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
sfp1down {
label = "ten64:green:sfp1:down";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
};
sfp2up {
label = "ten64:green:sfp2:up";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
};
admin {
label = "ten64:admin";
gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
};
};
sfp_xg0: dpmac2-sfp {
compatible = "sff,sfp";
i2c-bus = <&sfplower_i2c>;
tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
sfp_xg1: dpmac1-sfp {
compatible = "sff,sfp";
i2c-bus = <&sfpupper_i2c>;
tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
/* XG1 - Upper SFP */
&dpmac1 {
sfp = <&sfp_xg1>;
phy-connection-type = "10gbase-r";
managed = "in-band-status";
status = "okay";
};
/* XG0 - Lower SFP */
&dpmac2 {
sfp = <&sfp_xg0>;
phy-connection-type = "10gbase-r";
managed = "in-band-status";
status = "okay";
};
/* DPMAC3..6 is GE4 to GE8 */
&dpmac3 {
phy-handle = <&mdio1_phy5>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac4 {
phy-handle = <&mdio1_phy6>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac5 {
phy-handle = <&mdio1_phy7>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac6 {
phy-handle = <&mdio1_phy8>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
/* DPMAC7..10 is GE0 to GE3 */
&dpmac7 {
phy-handle = <&mdio1_phy1>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac8 {
phy-handle = <&mdio1_phy2>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac9 {
phy-handle = <&mdio1_phy3>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&dpmac10 {
phy-handle = <&mdio1_phy4>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
status = "okay";
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&emdio1 {
status = "okay";
mdio1_phy5: ethernet-phy@c {
reg = <0xc>;
};
mdio1_phy6: ethernet-phy@d {
reg = <0xd>;
};
mdio1_phy7: ethernet-phy@e {
reg = <0xe>;
};
mdio1_phy8: ethernet-phy@f {
reg = <0xf>;
};
mdio1_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
mdio1_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
mdio1_phy3: ethernet-phy@1e {
reg = <0x1e>;
};
mdio1_phy4: ethernet-phy@1f {
reg = <0x1f>;
};
};
&esdhc {
status = "okay";
};
&i2c0 {
status = "okay";
sfpgpio: gpio@76 {
compatible = "ti,tca9539";
reg = <0x76>;
#gpio-cells = <2>;
gpio-controller;
admin_led_lower {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-low;
};
};
at97sc: tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
uc: board-controller@7e {
compatible = "traverse,ten64-controller";
reg = <0x7e>;
};
};
&i2c2 {
status = "okay";
rx8035: rtc@32 {
compatible = "epson,rx8035";
reg = <0x32>;
};
};
&i2c3 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9540";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
sfpupper_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
sfplower_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
&qspi {
status = "okay";
en25s64: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0 0x100000>;
};
partition@100000 {
label = "bl3";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "mcfirmware";
reg = <0x300000 0x200000>;
};
partition@500000 {
label = "ubootenv";
reg = <0x500000 0x80000>;
};
partition@580000 {
label = "dpl";
reg = <0x580000 0x40000>;
};
partition@5C0000 {
label = "dpc";
reg = <0x5C0000 0x40000>;
};
partition@600000 {
label = "devicetree";
reg = <0x600000 0x40000>;
};
};
};
nand: flash@1 {
compatible = "spi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* reserved for future boot direct from NAND flash
* (this would use the same layout as the 8MiB NOR flash)
*/
partition@0 {
label = "nand-boot-reserved";
reg = <0 0x800000>;
};
/* recovery / install environment */
partition@800000 {
label = "recovery";
reg = <0x800000 0x2000000>;
};
/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
partition@2800000 {
label = "ubia";
reg = <0x2800000 0x6C00000>;
};
/* ubib (second OpenWrt) */
partition@9400000 {
label = "ubib";
reg = <0x9400000 0x6C00000>;
};
};
};
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

2
arch/arm/dts/fsl-lx2160a-qds.dtsi
View file

@ -250,7 +250,7 @@
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};

2
arch/arm/dts/fsl-lx2160a-rdb.dts
View file

@ -117,7 +117,7 @@
status = "okay";
rtc@51 {
compatible = "pcf2127-rtc";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};

15
arch/arm/dts/ls1021a-pg-wcom-expu1.dts
View file

@ -87,7 +87,6 @@
label = "qe";
reg = <0x20000 0x20000>;
};
/* ZL30343 init data to be added here */
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
@ -101,8 +100,20 @@
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "redenvred";
reg = <0x200000 0x20000>;
};
partition@220000 {
label = "redenv";
reg = <0x220000 0x20000>;
};
partition@240000 {
label = "redu-boot";
reg = <0x240000 0x100000>;
};
partition@340000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
reg = <0x340000 0x03C00000>;
};
};
};

15
arch/arm/dts/ls1021a-pg-wcom-seli8.dts
View file

@ -38,6 +38,7 @@
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
max-speed = <100>;
status = "okay";
};
@ -82,8 +83,20 @@
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "redenvred";
reg = <0x200000 0x20000>;
};
partition@220000 {
label = "redenv";
reg = <0x220000 0x20000>;
};
partition@240000 {
label = "redu-boot";
reg = <0x240000 0x100000>;
};
partition@340000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
reg = <0x340000 0x03C00000>;
};
};
};

4
board/freescale/ls1043ardb/ls1043ardb.c
View file

@ -219,6 +219,10 @@ int board_init(void)
ppa_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
#ifdef CONFIG_U_QE
u_qe_init();
#endif

4
board/freescale/ls1046ardb/ls1046ardb.c
View file

@ -93,6 +93,10 @@ int board_init(void)
ppa_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
/* invert AQR105 IRQ pins polarity */
out_be32(&scfg->intpcr, AQR105_IRQ_MASK);

10
board/freescale/ls1088a/ls1088a.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2018 NXP
* Copyright 2017-2022 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@ -904,10 +904,10 @@ void fsl_fdt_fixup_flash(void *fdt)
}
if (disable_ifc) {
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
offset = fdt_path_offset(fdt, "/ifc/nor");
offset = fdt_path_offset(fdt, "/memory-controller/nor");
} else {
offset = fdt_path_offset(fdt, "/soc/quadspi");
@ -917,10 +917,10 @@ void fsl_fdt_fixup_flash(void *fdt)
#else
#ifdef CONFIG_FSL_QSPI
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
offset = fdt_path_offset(fdt, "/ifc/nor");
offset = fdt_path_offset(fdt, "/memory-controller/nor");
#else
offset = fdt_path_offset(fdt, "/soc/quadspi");

32
board/keymile/Kconfig
View file

@ -130,6 +130,38 @@ config SYS_IVM_EEPROM_PAGE_LEN
help
Page size of inventory in EEPROM.
config PG_WCOM_UBOOT_UPDATE_SUPPORTED
bool "Enable U-boot Field Fail-Safe Update Functionality"
default n
help
Indicates that field fail-safe u-boot update is supported.
This functionality works only for designs that are booting
from parallel NOR flash.
config PG_WCOM_UBOOT_BOOTPACKAGE
bool "U-boot Is Part Of Factory Boot-Package Image"
default n
help
Indicates that u-boot will be a part of the factory programmed
boot-package image.
Has to be set for original u-boot programmed at factory.
config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
hex "Text Base For U-boot Programmed Outside Factory"
default 0xFFFFFFFF
help
Text base of an updated u-boot that is not factory programmed but
later when the unit is rolled out on the field.
Has to be set for original u-boot programmed at factory.
config PG_WCOM_UBOOT_UPDATE
bool "U-boot Is Part Of Factory Boot-Package Image"
default n
help
Indicates that u-boot will be a part of the embedded software and
programmed at field.
Has to be set for updated u-boot version programmed at field.
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
source "board/keymile/km_arm/Kconfig"

18
board/keymile/README Normal file
View file

@ -0,0 +1,18 @@
Field Fail-Save U-boot Update
-----------------------------
Field Fail-Save u-boot update is a feature that allows save u-boot update
of FOX and XMC products that are rolled out in the field.
The feature is initially implemented for designs based on LS102x SoC, but in
theory can be used on all designs that are booting from parallel NOR flash.
The implementation expects redundant (secondary) u-boot image on a predefined
location in the NOR flash, u-boot execution will be transferred to the redundant 
(secondary) u-boot and redundant u-boot will be started if 'updateduboot' envvar
is set to 'yes'.
Update logic check_for_uboot_update() has to be invoked from the design early
before relocation just after SoC initialization, e.g from board_early_init_f or
misc_init_f functions.
By design it is expected that primary u-boot image is burned in the factory and
never updated, and in case u-boot update is required it can flashed and started
from secondary u-boot location.

53
board/keymile/common/common.c
View file

@ -19,6 +19,8 @@
#include <asm/io.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/bug.h>
#include <bootcount.h>
#if defined(CONFIG_POST)
#include "post.h"
@ -76,6 +78,57 @@ int set_km_env(void)
return 0;
}
#if CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE_SUPPORTED)
#if ((!CONFIG_IS_ENABLED(PG_WCOM_UBOOT_BOOTPACKAGE) && \
!CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE)) || \
(CONFIG_IS_ENABLED(PG_WCOM_UBOOT_BOOTPACKAGE) && \
CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE)))
#error "It has to be either bootpackage or update u-boot image!"
#endif
void check_for_uboot_update(void)
{
void (*uboot_update_entry)(void) =
(void (*)(void)) CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE;
char *isupdated = env_get("updateduboot");
ulong bootcount = bootcount_load();
ulong ebootcount = 0;
if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE)) {
/*
* When running in factory burned u-boot move to the updated
* u-boot version only if updateduboot envvar is set to 'yes'
* and bootcount limit is not exceeded.
* Board must be able to start in factory bootloader mode!
*/
if (isupdated && !strncmp(isupdated, "yes", 3) &&
bootcount <= CONFIG_BOOTCOUNT_BOOTLIMIT) {
printf("Check update: update detected, ");
printf("starting new image @%08x ...\n",
CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE);
ebootcount = early_bootcount_load();
if (ebootcount <= CONFIG_BOOTCOUNT_BOOTLIMIT) {
early_bootcount_store(++ebootcount);
uboot_update_entry();
} else {
printf("Check update: warning: ");
printf("early bootcount exceeded (%lu)\n",
ebootcount);
}
}
printf("Check update: starting factory image @%08x ...\n",
CONFIG_SYS_TEXT_BASE);
} else if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE)) {
/*
* When running in field updated u-boot, make sure that
* bootcount limit is never exceeded. Must never happen!
*/
WARN_ON(bootcount > CONFIG_BOOTCOUNT_BOOTLIMIT);
printf("Check update: updated u-boot starting @%08x ...\n",
CONFIG_SYS_TEXT_BASE);
}
}
#endif
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
static void i2c_write_start_seq(void)
{

4
board/keymile/common/common.h
View file

@ -133,6 +133,10 @@ int get_testpin(void);
int set_km_env(void);
ulong early_bootcount_load(void);
void early_bootcount_store(ulong ebootcount);
void check_for_uboot_update(void);
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))

64
board/keymile/common/qrio.c
View file

@ -27,6 +27,32 @@ void show_qrio(void)
(id_rev >> 8) & 0xff, id_rev & 0xff);
}
#define SLFTEST_OFF 0x06
bool qrio_get_selftest_pin(void)
{
u8 slftest;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
slftest = in_8(qrio_base + SLFTEST_OFF);
return (slftest & 1) > 0;
}
#define BPRTH_OFF 0x04
bool qrio_get_pgy_pres_pin(void)
{
u8 pgy_pres;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
pgy_pres = in_8(qrio_base + BPRTH_OFF);
return (pgy_pres & 0x80) > 0;
}
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
@ -244,6 +270,44 @@ void qrio_uprstreq(u8 mode)
out_8(qrio_base + RSTCFG_OFF, rstcfg);
}
/* Early bootcount memory area is avilable starting from QRIO3 Rev.2 */
#define QRIO3_ID 0x71
#define QRIO3_REV 0x02
#define EBOOTCNT_OFF 0x28
ulong early_bootcount_load(void)
{
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
u8 id = (id_rev >> 8) & 0xff;
u8 rev = id_rev & 0xff;
u32 ebootcount = 0;
if (id == QRIO3_ID && rev >= QRIO3_REV) {
ebootcount = in_be32(qrio_base + EBOOTCNT_OFF);
} else {
printf("QRIO: warning: early bootcount not supported, ");
printf("id = %u, rev = %u\n", id, rev);
}
return ebootcount;
}
void early_bootcount_store(ulong ebootcount)
{
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
u8 id = (id_rev >> 8) & 0xff;
u8 rev = id_rev & 0xff;
if (id == QRIO3_ID && rev >= QRIO3_REV) {
out_be32(qrio_base + EBOOTCNT_OFF, ebootcount);
} else {
printf("QRIO: warning: early bootcount not supported, ");
printf("id = %u, rev = %u\n", id, rev);
}
}
/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
* 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
* For I2C only the low state is activly driven and high state is pulled-up

2
board/keymile/common/qrio.h
View file

@ -12,6 +12,8 @@
#define QRIO_GPIO_B 0x60
void show_qrio(void);
bool qrio_get_selftest_pin(void);
bool qrio_get_pgy_pres_pin(void);
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);

2
board/keymile/pg-wcom-ls102xa/MAINTAINERS
View file

@ -7,6 +7,8 @@ F: include/configs/km/pg-wcom-ls102xa.h
F: include/configs/pg-wcom-seli8.h
F: include/configs/pg-wcom-expu1.h
F: configs/pg_wcom_seli8_defconfig
F: configs/pg_wcom_seli8_update_defconfig
F: configs/pg_wcom_expu1_defconfig
F: configs/pg_wcom_expu1_update_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts

30
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View file

@ -91,8 +91,10 @@ int board_early_init_f(void)
qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_CLIPS_RST, false, false);
#endif
/* deasset debug phy reset only if piggy is present */
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false);
i2c_deblock_gpio_cfg();
@ -107,6 +109,13 @@ int board_early_init_f(void)
return 0;
}
int misc_init_f(void)
{
if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
check_for_uboot_update();
return 0;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
@ -128,8 +137,7 @@ int board_late_init(void)
int misc_init_r(void)
{
if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
@ -150,24 +158,22 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_POST)
int post_hotkeys_pressed(void)
{
/* DIC26_SELFTEST: GPRTA0, GPA0 */
qrio_gpio_direction_input(QRIO_GPIO_A, 0);
return qrio_get_gpio(QRIO_GPIO_A, 0);
/* DIC26_SELFTEST: QRIO, SLFTEST */
return qrio_get_selftest_pin();
}
/* POST word is located in the unused SCRATCHRW4 register */
#define CCSR_SCRATCHRW4_ADDR 0x1ee020c
ulong post_word_load(void)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
return in_le32(addr);
}
void post_word_store(ulong value)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
out_le32(addr, value);
}

6
board/traverse/common/Kconfig Normal file
View file

@ -0,0 +1,6 @@
config TEN64_CONTROLLER
bool "Enable Ten64 board controller driver"
depends on TARGET_TEN64
help
Support for the board microcontroller on the Traverse
Ten64 family of boards.

1
board/traverse/common/Makefile Normal file
View file

@ -0,0 +1 @@
obj-$(CONFIG_TEN64_CONTROLLER) += ten64_controller.o

28
board/traverse/common/ten64-controller.h Normal file
View file

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef TEN64_CNTRL_H
#define TEN64_CNTRL_H
/**
* struct t64uc_board_info - Board Information Structure
* @mac: Base MAC address
* @cpuId: Microcontroller unique serial number
* @fwversion_major: Microcontroller version number (Major)
* @fwversion_minor: Microcontroller version number (Minor)
* @fwversion_patch: Microcontroller version number (Patch)
*/
struct t64uc_board_info {
u8 mac[6];
u32 cpuId[4];
u8 fwversion_major;
u8 fwversion_minor;
u8 fwversion_patch;
} __packed;
enum {
TEN64_CNTRL_GET_BOARD_INFO,
TEN64_CNTRL_10G_OFF,
TEN64_CNTRL_10G_ON,
TEN64_CNTRL_SET_NEXT_BOOTSRC
};
#endif

240
board/traverse/common/ten64_controller.c Normal file
View file

@ -0,0 +1,240 @@
// SPDX-License-Identifier: GPL-2.0+
/* Ten64 Board Microcontroller Driver
* Copyright 2021 Traverse Technologies Australia
*
*/
#include <common.h>
#include <dm.h>
#include <misc.h>
#include <i2c.h>
#include <hexdump.h>
#include <dm/device_compat.h>
#include <inttypes.h>
#include <linux/delay.h>
#include "ten64-controller.h"
/* Microcontroller command set and structure
* These should not be used outside this file
*/
#define T64_UC_DATA_MAX_SIZE 128U
#define T64_UC_API_MSG_HEADER_SIZE 4U
#define T64_UC_API_HEADER_PREAMB 0xcabe
enum {
TEN64_UC_CMD_SET_BOARD_MAC = 0x10,
TEN64_UC_CMD_GET_BOARD_INFO = 0x11,
TEN64_UC_CMD_GET_STATE = 0x20,
TEN64_UC_CMD_SET_RESET_BTN_HOLD_TIME = 0x21,
TEN64_UC_CMD_ENABLE_RESET_BUTTON = 0x22,
TEN64_UC_CMD_SET_NEXT_BOOTSRC = 0x23,
TEN64_UC_CMD_ENABLE_10G = 0x24,
TEN64_UC_CMD_FWUP_GET_INFO = 0xA0,
TEN64_UC_CMD_FWUP_INIT = 0xA1,
TEN64_UC_CMD_FWUP_XFER = 0xA2,
TEN64_UC_CMD_FWUP_CHECK = 0xA3,
TEN64_UC_CMD_FWUPBOOT = 0x0A
};
/** struct t64uc_message - Wire Format for microcontroller messages
* @preamb: Message preamble (always 0xcabe)
* @cmd: Command to invoke
* @len: Length of data
* @data: Command data, up to 128 bytes
*/
struct t64uc_message {
u16 preamb;
u8 cmd;
u8 len;
u8 data[T64_UC_DATA_MAX_SIZE];
} __packed;
enum {
T64_CTRL_IO_SET = 1U,
T64_CTRL_IO_CLEAR = 2U,
T64_CTRL_IO_TOGGLE = 3U,
T64_CTRL_IO_RESET = 4U,
T64_CTRL_IO_UNKNOWN = 5U
};
/** struct t64uc_board_10g_enable - Wrapper for 10G enable command
* @control: state to set the 10G retimer - either
* T64_CTRL_IO_CLEAR (0x02) for off or
* T64_CTRL_IO_SET (0x01) for on.
*
* This struct exists to simplify the wrapping of the
* command value into a microcontroller message and passing into
* functions.
*/
struct t64uc_board_10g_enable {
u8 control;
} __packed;
/** ten64_controller_send_recv_command() - Wrapper function to
* send a command to the microcontroller.
* @uc_chip: the DM I2C chip handle for the microcontroller
* @uc_cmd: the microcontroller API command code
* @uc_cmd_data: pointer to the data struct for this command
* @uc_data_len: size of command data struct
* @return_data: place to store response from microcontroller, NULL if not expected
* @expected_return_len: expected size of microcontroller command response
* @return_message_wait: wait this long (in us) before reading the response
*
* Invoke a microcontroller command and receive a response.
* This function includes communicating with the microcontroller over
* I2C and encoding a message in the wire format.
*
* Return: 0 if successful, error code otherwise.
* Returns -EBADMSG if the microcontroller response could not be validated,
* other error codes may be passed from dm_i2c_xfer()
*/
static int ten64_controller_send_recv_command(struct udevice *ucdev, u8 uc_cmd,
void *uc_cmd_data, u8 cmd_data_len,
void *return_data, u8 expected_return_len,
u16 return_message_wait)
{
int ret;
struct t64uc_message send, recv;
struct i2c_msg command_message, return_message;
struct dm_i2c_chip *chip = dev_get_parent_plat(ucdev);
dev_dbg(ucdev, "%s sending cmd %02X len %d\n", __func__, uc_cmd, cmd_data_len);
send.preamb = T64_UC_API_HEADER_PREAMB;
send.cmd = uc_cmd;
send.len = cmd_data_len;
if (uc_cmd_data && cmd_data_len > 0)
memcpy(send.data, uc_cmd_data, cmd_data_len);
command_message.addr = chip->chip_addr;
command_message.len = T64_UC_API_MSG_HEADER_SIZE + send.len;
command_message.buf = (void *)&send;
command_message.flags = I2C_M_STOP;
ret = dm_i2c_xfer(ucdev, &command_message, 1);
if (!return_data)
return ret;
udelay(return_message_wait);
return_message.addr = chip->chip_addr;
return_message.len = T64_UC_API_MSG_HEADER_SIZE + expected_return_len;
return_message.buf = (void *)&recv;
return_message.flags = I2C_M_RD;
ret = dm_i2c_xfer(ucdev, &return_message, 1);
if (ret)
return ret;
if (recv.preamb != T64_UC_API_HEADER_PREAMB) {
dev_err(ucdev, "%s: No preamble received in microcontroller response\n",
__func__);
return -EBADMSG;
}
if (recv.cmd != uc_cmd) {
dev_err(ucdev, "%s: command response mismatch, got %02X expecting %02X\n",
__func__, recv.cmd, uc_cmd);
return -EBADMSG;
}
if (recv.len != expected_return_len) {
dev_err(ucdev, "%s: received message has unexpected length, got %d expected %d\n",
__func__, recv.len, expected_return_len);
return -EBADMSG;
}
memcpy(return_data, recv.data, expected_return_len);
return ret;
}
/** ten64_controller_send_command() - Send command to microcontroller without
* expecting a response (for example, invoking a control command)
* @uc_chip: the DM I2C chip handle for the microcontroller
* @uc_cmd: the microcontroller API command code
* @uc_cmd_data: pointer to the data struct for this command
* @uc_data_len: size of command data struct
*/
static int ten64_controller_send_command(struct udevice *ucdev, u8 uc_cmd,
void *uc_cmd_data, u8 cmd_data_len)
{
return ten64_controller_send_recv_command(ucdev, uc_cmd,
uc_cmd_data, cmd_data_len,
NULL, 0, 0);
}
/** ten64_controller_get_board_info() -Get board information from microcontroller
* @dev: The microcontroller device handle
* @out: Pointer to a t64uc_board_info struct that has been allocated by the caller
*/
static int ten64_controller_get_board_info(struct udevice *dev, struct t64uc_board_info *out)
{
int ret;
ret = ten64_controller_send_recv_command(dev, TEN64_UC_CMD_GET_BOARD_INFO,
NULL, 0, out,
sizeof(struct t64uc_board_info),
10000);
if (ret) {
dev_err(dev, "%s unable to send board info command: %d\n",
__func__, ret);
return ret;
}
return 0;
}
/**
* ten64_controller_10g_enable_command() - Sends a 10G (Retimer) enable command
* to the microcontroller.
* @ucdev: The microcontroller udevice
* @value: The value flag for the 10G state
*/
static int ten64_controller_10g_enable_command(struct udevice *ucdev, u8 value)
{
int ret;
struct t64uc_board_10g_enable enable_msg;
enable_msg.control = value;
ret = ten64_controller_send_command(ucdev, TEN64_UC_CMD_ENABLE_10G,
&enable_msg, sizeof(enable_msg));
if (ret) {
dev_err(ucdev, "ERROR sending uC 10G Enable message: %d\n", ret);
return -1;
}
return 0;
}
int ten64_controller_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
void *rx_msg, int rx_size)
{
switch (msgid) {
case TEN64_CNTRL_GET_BOARD_INFO:
return ten64_controller_get_board_info(dev, (struct t64uc_board_info *)rx_msg);
case TEN64_CNTRL_10G_OFF:
return ten64_controller_10g_enable_command(dev, T64_CTRL_IO_CLEAR);
case TEN64_CNTRL_10G_ON:
return ten64_controller_10g_enable_command(dev, T64_CTRL_IO_SET);
default:
dev_err(dev, "%s: Unknown operation %d\n", __func__, msgid);
}
return -EINVAL;
}
static struct misc_ops ten64_ctrl_ops = {
.call = ten64_controller_call
};
static const struct udevice_id ten64_controller_ids[] = {
{.compatible = "traverse,ten64-controller"},
{}
};
U_BOOT_DRIVER(ten64_controller) = {
.name = "ten64-controller-i2c",
.id = UCLASS_MISC,
.of_match = ten64_controller_ids,
.ops = &ten64_ctrl_ops
};

17
board/traverse/ten64/Kconfig Normal file
View file

@ -0,0 +1,17 @@
if TARGET_TEN64
config SYS_BOARD
default "ten64"
config SYS_VENDOR
default "traverse"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ten64"
endif
source "board/traverse/common/Kconfig"

8
board/traverse/ten64/MAINTAINERS Normal file
View file

@ -0,0 +1,8 @@
TEN64 BOARD
M: Mathew McBride <matt@traverse.com.au>
S: Maintained
F: arch/arm/dts/fsl-ls1088a-ten64.dts
F: board/traverse/ten64/
F: board/traverse/common/
F: include/configs/ten64.h
F: configs/ten64_tfa_defconfig

6
board/traverse/ten64/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += ten64.o
obj-y += eth_ten64.o
CFLAGS_ten64.o += -DDEBUG

47
board/traverse/ten64/eth_ten64.c Normal file
View file

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
* Copyright 2019-2021 Traverse Technologies Australia
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <malloc.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
void reset_phy(void)
{
mc_env_boot();
}
int board_phy_config(struct phy_device *phydev)
{
/* These settings only apply to VSC8514 */
if (phydev->phy_id == 0x70670) {
/* First, ensure LEDs are driven to rails (not tristate)
* This is in the extended page 0x0010
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0010);
phy_write(phydev, MDIO_DEVAD_NONE, 0x0E, 0x2000);
/* Restore to page 0 */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0000);
/* Disable blink on the left LEDs, and make the activity LEDs blink faster */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0xC03);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x3421);
}
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}

438
board/traverse/ten64/ten64.c Normal file
View file

@ -0,0 +1,438 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Traverse Ten64 Family board
* Copyright 2017-2018 NXP
* Copyright 2019-2021 Traverse Technologies
*/
#include <common.h>
#include <dm/uclass.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#include <log.h>
#include <malloc.h>
#include <errno.h>
#include <misc.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <fsl_immap.h>
#include "../common/ten64-controller.h"
#define I2C_RETIMER_ADDR 0x27
DECLARE_GLOBAL_DATA_PTR;
static int ten64_read_board_info(struct t64uc_board_info *);
static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *);
static void ten64_board_retimer_ds110df410_init(void);
enum {
TEN64_BOARD_REV_A = 0xFF,
TEN64_BOARD_REV_B = 0xFE,
TEN64_BOARD_REV_C = 0xFD
};
#define RESV_MEM_IN_BANK(b) (gd->arch.resv_ram >= base[b] && \
gd->arch.resv_ram < base[b] + size[b])
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}
static u32 ten64_get_board_rev(void)
{
struct ccsr_gur *dcfg = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 board_rev_in = in_le32(&dcfg->gpporcr1);
return board_rev_in;
}
int checkboard(void)
{
enum boot_src src = get_boot_src();
char boardmodel[32];
struct t64uc_board_info boardinfo;
u32 board_rev = ten64_get_board_rev();
switch (board_rev) {
case TEN64_BOARD_REV_A:
snprintf(boardmodel, 32, "1064-0201A (Alpha)");
break;
case TEN64_BOARD_REV_B:
snprintf(boardmodel, 32, "1064-0201B (Beta)");
break;
case TEN64_BOARD_REV_C:
snprintf(boardmodel, 32, "1064-0201C");
break;
default:
snprintf(boardmodel, 32, "1064 Revision %X", (0xFF - board_rev));
break;
}
printf("Board: %s, boot from ", boardmodel);
if (src == BOOT_SOURCE_SD_MMC)
puts("SD card\n");
else if (src == BOOT_SOURCE_QSPI_NOR)
puts("QSPI\n");
else
printf("Unknown boot source %d\n", src);
puts("Controller: ");
if (CONFIG_IS_ENABLED(TEN64_CONTROLLER)) {
/* Driver not compatible with alpha/beta board MCU firmware */
if (board_rev <= TEN64_BOARD_REV_C) {
if (ten64_read_board_info(&boardinfo)) {
puts("ERROR: unable to communicate\n");
} else {
printf("firmware %d.%d.%d\n",
boardinfo.fwversion_major,
boardinfo.fwversion_minor,
boardinfo.fwversion_patch);
ten64_set_macaddrs_from_board_info(&boardinfo);
}
} else {
puts("not supported on this board revision\n");
}
} else {
puts("driver not enabled (no MAC addresses or other information will be read)\n");
}
return 0;
}
int board_init(void)
{
init_final_memctl_regs();
if (CONFIG_IS_ENABLED(FSL_CAAM))
sec_init();
return 0;
}
int fsl_initdram(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
}
void board_quiesce_devices(void)
{
if (IS_ENABLED(CONFIG_FSL_MC_ENET))
fsl_mc_ldpaa_exit(gd->bd);
}
void fdt_fixup_board_enet(void *fdt)
{
int offset;
offset = fdt_path_offset(fdt, "/fsl-mc");
if (offset < 0)
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
if (offset < 0) {
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
__func__, offset);
return;
}
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
}
/* Called after SoC board_late_init in fsl-layerscape/soc.c */
int fsl_board_late_init(void)
{
ten64_board_retimer_ds110df410_init();
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
int i;
u16 mc_memory_bank = 0;
u64 *base;
u64 *size;
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
debug("%s blob=0x%p\n", __func__, blob);
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
if (mc_memory_base != 0)
mc_memory_bank++;
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
base = calloc(total_memory_banks, sizeof(u64));
size = calloc(total_memory_banks, sizeof(u64));
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
size[i] = gd->bd->bi_dram[i].size;
/* reduce size if reserved memory is within this bank */
if (CONFIG_IS_ENABLED(RESV_RAM) && RESV_MEM_IN_BANK(i))
size[i] = gd->arch.resv_ram - base[i];
}
if (mc_memory_base != 0) {
for (i = 0; i <= total_memory_banks; i++) {
if (base[i] == 0 && size[i] == 0) {
base[i] = mc_memory_base;
size[i] = mc_memory_size;
break;
}
}
}
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
if (CONFIG_IS_ENABLED(FSL_MC_ENET))
fdt_fixup_board_enet(blob);
fdt_fixup_icid(blob);
return 0;
}
#define MACADDRBITS(a, b) (u8)(((a) >> (b)) & 0xFF)
/** Probe and return a udevice for the Ten64 board microcontroller.
* Optionally, return the I2C bus the microcontroller resides on
* @i2c_bus_out: return I2C bus device handle in this pointer
*/
static int ten64_get_micro_udevice(struct udevice **ucdev, struct udevice **i2c_bus_out)
{
int ret;
struct udevice *i2cbus;
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
if (ret) {
printf("%s: Could not get I2C UCLASS", __func__);
return ret;
}
if (i2c_bus_out)
*i2c_bus_out = i2cbus;
ret = dm_i2c_probe(i2cbus, 0x7E, DM_I2C_CHIP_RD_ADDRESS, ucdev);
if (ret) {
printf("%s: Could not get microcontroller device\n", __func__);
return ret;
}
return ret;
}
static int ten64_read_board_info(struct t64uc_board_info *boardinfo)
{
struct udevice *ucdev;
int ret;
ret = ten64_get_micro_udevice(&ucdev, NULL);
if (ret)
return ret;
ret = misc_call(ucdev, TEN64_CNTRL_GET_BOARD_INFO, NULL, 0, (void *)boardinfo, 0);
if (ret)
return ret;
return 0;
}
static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinfo)
{
char ethaddr[18];
char enetvar[10];
u8 intfidx, this_dpmac_num;
u64 macaddr = 0;
/* We will copy the MAC address returned from the
* uC (48 bits) into the u64 macaddr
*/
u8 *macaddr_bytes = (u8 *)&macaddr + 2;
/** MAC addresses are allocated in order of the physical port numbers,
* DPMAC7->10 is "eth0" through "eth3"
* DPMAC3->6 is "eth4" through "eth7"
* DPMAC2 and 1 are "eth8" and "eth9" respectively
*/
int allocation_order[10] = {7, 8, 9, 10, 3, 4, 5, 6, 2, 1};
memcpy(macaddr_bytes, boardinfo->mac, 6);
/* MAC address bytes from uC are in big endian,
* convert to CPU
*/
macaddr = __be64_to_cpu(macaddr);
for (intfidx = 0; intfidx < 10; intfidx++) {
snprintf(ethaddr, 18, "%02X:%02X:%02X:%02X:%02X:%02X",
MACADDRBITS(macaddr, 40),
MACADDRBITS(macaddr, 32),
MACADDRBITS(macaddr, 24),
MACADDRBITS(macaddr, 16),
MACADDRBITS(macaddr, 8),
MACADDRBITS(macaddr, 0));
this_dpmac_num = allocation_order[intfidx];
printf("DPMAC%d: %s\n", this_dpmac_num, ethaddr);
snprintf(enetvar, 10,
(this_dpmac_num != 1) ? "eth%daddr" : "ethaddr",
this_dpmac_num - 1);
macaddr++;
if (!env_get(enetvar))
env_set(enetvar, ethaddr);
}
}
/* The retimer (DS110DF410) is one of the devices without
* a RESET line, but a power switch is on the board
* allowing it to be reset via uC command
*/
static int board_cycle_retimer(struct udevice **retim_dev)
{
int ret;
u8 loop;
struct udevice *uc_dev;
struct udevice *i2cbus;
ret = ten64_get_micro_udevice(&uc_dev, &i2cbus);
if (ret)
return ret;
ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
if (ret == 0) {
puts("(retimer on, resetting...) ");
ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
mdelay(1000);
}
ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
// Wait for retimer to come back
for (loop = 0; loop < 5; loop++) {
ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
if (ret == 0)
return 0;
mdelay(500);
}
return -ENOSYS;
}
/* ten64_board_retimer_ds110df410_init() - Configure the 10G retimer
* Adopted from the t102xqds board file
*/
static void ten64_board_retimer_ds110df410_init(void)
{
u8 reg;
int ret;
struct udevice *retim_dev;
u32 board_rev = ten64_get_board_rev();
puts("Retimer: ");
/* Retimer power cycle not implemented on early board
* revisions/controller firmwares
*/
if (CONFIG_IS_ENABLED(TEN64_CONTROLLER) &&
board_rev >= TEN64_BOARD_REV_C) {
ret = board_cycle_retimer(&retim_dev);
if (ret) {
puts("Retimer power on failed\n");
return;
}
}
/* Access to Control/Shared register */
reg = 0x0;
ret = dm_i2c_write(retim_dev, 0xff, &reg, 1);
if (ret) {
printf("Error writing to retimer register (error %d)\n", ret);
return;
}
/* Read device revision and ID */
dm_i2c_read(retim_dev, 1, &reg, 1);
if (reg == 0xF0)
puts("DS110DF410 found\n");
else
printf("Unknown retimer 0x%xn\n", reg);
/* Enable Broadcast */
reg = 0x0c;
dm_i2c_write(retim_dev, 0xff, &reg, 1);
/* Perform a full reset (state, channel and clock)
* for all channels
* as the DS110DF410 does not have a RESET line
*/
dm_i2c_read(retim_dev, 0, &reg, 1);
reg |= 0x7;
dm_i2c_write(retim_dev, 0, &reg, 1);
/* Set rate/subrate = 0 */
reg = 0x6;
dm_i2c_write(retim_dev, 0x2F, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
dm_i2c_write(retim_dev, 0x60, &reg, 1);
reg = 0xb2;
dm_i2c_write(retim_dev, 0x61, &reg, 1);
reg = 0x90;
dm_i2c_write(retim_dev, 0x62, &reg, 1);
reg = 0xb3;
dm_i2c_write(retim_dev, 0x63, &reg, 1);
reg = 0xff;
dm_i2c_write(retim_dev, 0x64, &reg, 1);
/* Invert channel 2 (Lower SFP TX to CPU) due to the SFP being inverted */
reg = 0x05;
dm_i2c_write(retim_dev, 0xFF, &reg, 1);
dm_i2c_read(retim_dev, 0x1F, &reg, 1);
reg |= 0x80;
dm_i2c_write(retim_dev, 0x1F, &reg, 1);
puts("OK\n");
}

1
configs/T1024RDB_NAND_defconfig
View file

@ -96,6 +96,7 @@ CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FW_ADDR=0x200000

1
configs/T1042D4RDB_SDCARD_defconfig
View file

@ -90,6 +90,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x10400
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x124000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y

1
configs/T2080RDB_defconfig
View file

@ -79,6 +79,7 @@ CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y

1
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View file

@ -80,6 +80,7 @@ CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y

9
configs/pg_wcom_expu1_defconfig
View file

@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000
CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
@ -26,6 +29,9 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
@ -42,7 +48,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
@ -76,3 +82,4 @@ CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_VERSION_VARIABLE=y

83
configs/pg_wcom_expu1_update_defconfig Normal file
View file

@ -0,0 +1,83 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
CONFIG_PG_WCOM_UBOOT_UPDATE=y
CONFIG_SYS_TEXT_BASE=0x60240000
CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0x60220000
CONFIG_ENV_ADDR_REDUND=0x60200000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_VERSION_VARIABLE=y

9
configs/pg_wcom_seli8_defconfig
View file

@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_SELI8=y
CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000
CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
@ -26,6 +29,9 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
@ -42,7 +48,7 @@ CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
@ -76,3 +82,4 @@ CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_VERSION_VARIABLE=y

83
configs/pg_wcom_seli8_update_defconfig Normal file
View file

@ -0,0 +1,83 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_SELI8=y
CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
CONFIG_PG_WCOM_UBOOT_UPDATE=y
CONFIG_SYS_TEXT_BASE=0x60240000
CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0x60220000
CONFIG_ENV_ADDR_REDUND=0x60200000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_VERSION_VARIABLE=y

119
configs/ten64_tfa_defconfig Normal file
View file

@ -0,0 +1,119 @@
CONFIG_ARM=y
CONFIG_TARGET_TEN64=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_FDT_OVERLAY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_BOOTEFI_HELLO=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GPT=y
CONFIG_RANDOM_UUID=y
CONFIG_CMD_DM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_UBI=y
CONFIG_CMD_UBIFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_FS_FAT=y
CONFIG_FAT_WRITE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-ten64"
CONFIG_EMC230X=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SIZE=0x80000
CONFIG_ENV_SECT_SIZE=0x80000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_CMD_FAN=y
CONFIG_FANCONTROL=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_E1000=y
# CONFIG_ID_EEPROM is not set
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_CMD_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCA953X=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ARM_SMCCC=y
CONFIG_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_CMD_MTD=y
CONFIG_LOGLEVEL=7
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:8m(reserved),32m(recovery),108m(ubia),108m(ubib);nor1:1m(bl2),2m(bl3),2m(mcfirmware),512k(ubootenv),256k(dpl),256k(dpc),256k(devicetree)"
CONFIG_MPC8XXX_GPIO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_RTC=y
CONFIG_RTC_RX8025=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_DM_ETH=y
CONFIG_PCI_INIT_R=y
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_MDIO=y
CONFIG_FSL_LS_MDIO=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TPM=y
CONFIG_CMD_TPM=y
CONFIG_TPM_ATMEL_TWI=y
CONFIG_MISC=y
CONFIG_USB5744=y
CONFIG_TEN64_CONTROLLER=y
CONFIG_DM_SCSI=y
CONFIG_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y

9
drivers/i2c/muxes/pca954x.c
View file

@ -23,7 +23,8 @@ enum pca_type {
PCA9546,
PCA9547,
PCA9548,
PCA9646
PCA9646,
PCA9847,
};
struct chip_desc {
@ -68,6 +69,11 @@ static const struct chip_desc chips[] = {
.muxtype = pca954x_isswi,
.width = 4,
},
[PCA9847] = {
.enable = 0x8,
.muxtype = pca954x_ismux,
.width = 8,
},
};
static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
@ -106,6 +112,7 @@ static const struct udevice_id pca954x_ids[] = {
{ .compatible = "nxp,pca9547", .data = PCA9547 },
{ .compatible = "nxp,pca9548", .data = PCA9548 },
{ .compatible = "nxp,pca9646", .data = PCA9646 },
{ .compatible = "nxp,pca9847", .data = PCA9847 },
{ }
};

4
drivers/pci/Kconfig
View file

@ -233,8 +233,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
default "fsl,lx2160a-pcie" if ARCH_LX2160A
default "fsl,ls2088a-pcie" if ARCH_LX2162A
default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
@ -243,7 +242,6 @@ config FSL_PCIE_COMPAT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT

9
drivers/pci/pcie_layerscape_fixup.c
View file

@ -527,7 +527,7 @@ static void fdt_fixup_pcie_ls(void *blob)
}
if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
goto skip;
return;
list_for_each_entry(pcie_rc, &ls_pcie_list, list) {
nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
@ -568,9 +568,6 @@ static void fdt_fixup_pcie_ls(void *blob)
}
free(entries);
}
skip:
pcie_board_fix_fdt(blob);
}
#endif
@ -619,6 +616,10 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
{
struct ls_pcie_rc *pcie_rc;
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
pcie_board_fix_fdt(blob);
#endif
list_for_each_entry(pcie_rc, &ls_pcie_list, list)
ft_pcie_ls_setup(blob, pcie_rc);

4
drivers/rtc/pcf2127.c
View file

@ -120,7 +120,9 @@ static const struct rtc_ops pcf2127_rtc_ops = {
};
static const struct udevice_id pcf2127_rtc_ids[] = {
{ .compatible = "pcf2127-rtc" },
{ .compatible = "nxp,pcf2127" },
{ .compatible = "nxp,pcf2129" },
{ .compatible = "nxp,pca2129" },
{ }
};

2
include/configs/km/pg-wcom-ls102xa.h
View file

@ -274,4 +274,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#define CONFIG_MISC_INIT_F
#endif

55
include/configs/ten64.h Normal file
View file

@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
* Copyright 2019-2021 Traverse Technologies
*/
#ifndef __TEN64_H
#define __TEN64_H
#include "ls1088a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
#define SD_BOOTCOMMAND "run distro_bootcmd"
#define QSPI_MC_INIT_CMD \
"sf probe 0:0 && sf read 0x80000000 0x300000 0x200000 &&" \
"sf read 0x80200000 0x5C0000 0x40000 &&" \
"fsl_mc start mc 0x80000000 0x80200000 && " \
"sf read 0x80300000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x80300000\0"
#define SD_MC_INIT_CMD \
"mmcinfo; fatload mmc 0 0x80000000 mcfirmware/mc_ls1088a.itb; "\
"fatload mmc 0 0x80200000 dpaa2config/dpc.0x1D-0x0D.dtb; "\
"fsl_mc start mc 0x80000000 0x80200000\0"
#define BOOT_TARGET_DEVICES(func) \
func(NVME, nvme, 0) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, 0) \
func(PXE, pxe, 0)
#include <config_distro_bootcmd.h>
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"BOARD=ten64\0" \
"fdt_addr_r=0x90000000\0" \
"fdt_high=0xa0000000\0" \
"kernel_addr_r=0x81000000\0" \
"load_addr=0xa0000000\0" \
BOOTENV \
"load_efi_dtb=mtd read devicetree $fdt_addr_r && fdt addr $fdt_addr_r && " \
"fdt resize && fdt boardsetup\0" \
"bootcmd_recovery=mtd read recovery 0xa0000000; mtd read dpl 0x80100000 && " \
"fsl_mc apply DPL 0x80100000 && bootm 0xa0000000#ten64\0"
#endif /* __TEN64_H */