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OMAP4/5: Make the sysctrl structure common

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Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
This commit is contained in:
SRICHARAN R 2012-03-12 02:25:42 +00:00 committed by Albert ARIBAUD
parent 47c50143aa
commit 002a2c0c66
5 changed files with 19 additions and 16 deletions
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4
arch/arm/cpu/armv7/omap4/hwinit.c
View file

@ -59,8 +59,8 @@ void do_io_settings(void)
u32 lpddr2io; u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs = struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
struct omap4_sys_ctrl_regs *const ctrl = struct omap_sys_ctrl_regs *const ctrl =
(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision(); u32 omap4_rev = omap_revision();

4
arch/arm/cpu/armv7/omap5/hwinit.c
View file

@ -58,8 +58,8 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
void do_io_settings(void) void do_io_settings(void)
{ {
u32 io_settings = 0, mask = 0; u32 io_settings = 0, mask = 0;
struct omap5_sys_ctrl_regs *ioregs_base = struct omap_sys_ctrl_regs *ioregs_base =
(struct omap5_sys_ctrl_regs *) OMAP5_IOREGS_BASE; (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */ /* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) | mask = (ds_mask << 2) | (ds_mask << 8) |

10
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -139,18 +139,20 @@ struct s32ktimer {
unsigned int s32k_cr; /* 0x10 */ unsigned int s32k_cr; /* 0x10 */
}; };
struct omap4_sys_ctrl_regs { struct omap_sys_ctrl_regs {
unsigned int pad1[129]; unsigned int pad1[129];
unsigned int control_id_code; /* 0x4A002204 */ unsigned int control_id_code; /* 0x4A002204 */
unsigned int pad11[22]; unsigned int pad11[22];
unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
unsigned int pad2[47]; unsigned int pad2[24]; /* 0x4a002264 */
unsigned int control_status; /* 0x4a0022c4 */
unsigned int pad3[22]; /* 0x4a0022c8 */
unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad3[260277]; unsigned int pad4[260277];
unsigned int control_pbiaslite; /* 0x4A100600 */ unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad4[63]; unsigned int pad5[63];
unsigned int control_efuse_1; /* 0x4A100700 */ unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */ unsigned int control_efuse_2; /* 0x4A100704 */
}; };

13
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -136,9 +136,10 @@ struct s32ktimer {
unsigned int s32k_cr; /* 0x10 */ unsigned int s32k_cr; /* 0x10 */
}; };
#define OMAP5_IOREGS_BASE 0x4A002DA0 struct omap_sys_ctrl_regs {
u32 pad0[77]; /* 0x4A002000 */
struct omap5_sys_ctrl_regs { u32 control_status; /* 0x4A002134 */
u32 pad1[794]; /* 0x4A002138 */
u32 control_paconf_global; /* 0x4A002DA0 */ u32 control_paconf_global; /* 0x4A002DA0 */
u32 control_paconf_mode; /* 0x4A002DA4 */ u32 control_paconf_mode; /* 0x4A002DA4 */
u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
@ -149,7 +150,7 @@ struct omap5_sys_ctrl_regs {
u32 control_smart2io_padconf_2; /* 0x4A002DBC */ u32 control_smart2io_padconf_2; /* 0x4A002DBC */
u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
u32 pad1[14]; u32 pad2[14];
u32 control_pbias; /* 0x4A002E00 */ u32 control_pbias; /* 0x4A002E00 */
u32 control_i2c_0; /* 0x4A002E04 */ u32 control_i2c_0; /* 0x4A002E04 */
u32 control_camera_rx; /* 0x4A002E08 */ u32 control_camera_rx; /* 0x4A002E08 */
@ -160,7 +161,7 @@ struct omap5_sys_ctrl_regs {
u32 control_usb2phycore; /* 0x4A002E1C */ u32 control_usb2phycore; /* 0x4A002E1C */
u32 control_hdmi_1; /*0x4A002E20*/ u32 control_hdmi_1; /*0x4A002E20*/
u32 control_hsi; /*0x4A002E24*/ u32 control_hsi; /*0x4A002E24*/
u32 pad2[2]; u32 pad3[2];
u32 control_ddr3ch1_0; /*0x4A002E30*/ u32 control_ddr3ch1_0; /*0x4A002E30*/
u32 control_ddr3ch2_0; /*0x4A002E34*/ u32 control_ddr3ch2_0; /*0x4A002E34*/
u32 control_ddrch1_0; /*0x4A002E38*/ u32 control_ddrch1_0; /*0x4A002E38*/
@ -183,7 +184,7 @@ struct omap5_sys_ctrl_regs {
u32 control_srcomp_east_side; /*0x4A002E7C*/ u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/ u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/ u32 control_srcomp_code_latch; /*0x4A002E84*/
u32 pad3[3680198]; u32 pad4[3680198];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */ u32 control_padconf_mode; /* 0x4AE0CDA8 */

4
drivers/mmc/omap_hsmmc.c
View file

@ -45,8 +45,8 @@ static struct mmc hsmmc_dev[2];
static void omap4_vmmc_pbias_config(struct mmc *mmc) static void omap4_vmmc_pbias_config(struct mmc *mmc)
{ {
u32 value = 0; u32 value = 0;
struct omap4_sys_ctrl_regs *const ctrl = struct omap_sys_ctrl_regs *const ctrl =
(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
value = readl(&ctrl->control_pbiaslite); value = readl(&ctrl->control_pbiaslite);