mirror of
https://github.com/AsahiLinux/u-boot
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64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Rockchip Electronics Co., Ltd
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rv1126.h>
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#define GRF_BASE 0xFE000000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000",
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[BROM_BOOTSOURCE_SD] = "/mmc@ffc60000",
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};
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/* GRF_GPIO3A_IOMUX_L */
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enum {
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GPIO3A3_SHIFT = 12,
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GPIO3A3_MASK = GENMASK(14, 12),
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GPIO3A3_GPIO = 0,
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GPIO3A3_UART2_RX_M1,
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GPIO3A3_A7_JTAG_TMS_M1,
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GPIO3A2_SHIFT = 8,
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GPIO3A2_MASK = GENMASK(10, 8),
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GPIO3A2_GPIO = 0,
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GPIO3A2_UART2_TX_M1,
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GPIO3A2_A7_JTAG_TCK_M1,
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};
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/* GRF_IOFUNC_CON2 */
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enum {
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UART2_IO_SEL_SHIFT = 8,
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UART2_IO_SEL_MASK = GENMASK(8, 8),
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UART2_IO_SEL_M0 = 0,
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UART2_IO_SEL_M1,
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};
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void board_debug_uart_init(void)
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{
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static struct rv1126_grf * const grf = (void *)GRF_BASE;
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/* Enable early UART2 channel m1 on the rv1126 */
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rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
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UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
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/* Switch iomux */
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rk_clrsetreg(&grf->gpio3a_iomux_l,
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GPIO3A3_MASK | GPIO3A2_MASK,
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GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
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GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
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}
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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return 0;
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}
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#endif
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