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u-boot/arch/x86/lib/fsp2/fsp_dram.c

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x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
x86: fsp: Convert fsp_dram to use log_debug() Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-04 16:57:38 +00:00
#define LOG_CATEGORY LOGC_ARCH
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#include <common.h>
#include <handoff.h>
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:02 +00:00
#include <init.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#include <spl.h>
x86: Move acpi_s3.h to include/acpi/ This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-08 22:57:35 +00:00
#include <acpi/acpi_s3.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#include <asm/arch/cpu.h>
#include <asm/fsp/fsp_support.h>
#include <asm/fsp2/fsp_api.h>
#include <asm/fsp2/fsp_internal.h>
x86: fsp: Allow skipping init code when chain loading It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:12:53 +00:00
#include <linux/sizes.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
int dram_init(void)
{
int ret;
x86: fsp: Allow skipping init code when chain loading It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:12:53 +00:00
if (!ll_boot_init()) {
/* Use a small and safe amount of 1GB */
gd->ram_size = SZ_1G;
return 0;
}
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
if (spl_phase() == PHASE_SPL) {
bool s3wake = false;
x86: Avoid #ifdef with CONFIG_HAVE_ACPI_RESUME At present this enables a few arch-specific members of the global_data struct which are otherwise not part of the struct. As a result we have to use #ifdef in various places. The cost of always having these in the struct is small. Adjust things so that we can use compile-time code instead of #ifdefs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-10 00:43:16 +00:00
s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
gd->arch.prev_sleep_state == ACPI_S3;
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
ret = fsp_memory_init(s3wake,
IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
if (ret) {
x86: fsp: Convert fsp_dram to use log_debug() Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-04 16:57:38 +00:00
log_debug("Memory init failed (err=%x)\n", ret);
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
return ret;
}
/* The FSP has already set up DRAM, so grab the info we need */
ret = fsp_scan_for_ram_size();
if (ret)
return ret;
#ifdef CONFIG_ENABLE_MRC_CACHE
gd->arch.mrc[MRC_TYPE_NORMAL].buf =
fsp_get_nvs_data(gd->arch.hob_list,
&gd->arch.mrc[MRC_TYPE_NORMAL].len);
gd->arch.mrc[MRC_TYPE_VAR].buf =
fsp_get_var_nvs_data(gd->arch.hob_list,
&gd->arch.mrc[MRC_TYPE_VAR].len);
log_debug("normal %x, var %x\n",
gd->arch.mrc[MRC_TYPE_NORMAL].len,
gd->arch.mrc[MRC_TYPE_VAR].len);
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = gd->spl_handoff;
if (!ho) {
x86: fsp: Convert fsp_dram to use log_debug() Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-04 16:57:38 +00:00
log_debug("No SPL handoff found\n");
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
return -ESTRPIPE;
}
gd->ram_size = ho->ram_size;
handoff_load_dram_banks(ho);
#endif
ret = arch_fsps_preinit();
if (ret)
return log_msg_ret("fsp_s_preinit", ret);
}
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
x86: fsp: Allow skipping init code when chain loading It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:12:53 +00:00
if (!ll_boot_init())
return gd->ram_size;
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = gd->spl_handoff;
x86: fsp: Convert fsp_dram to use log_debug() Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-04 16:57:38 +00:00
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
return ho->arch.usable_ram_top;
#endif
return gd->ram_top;
}
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