2021-01-11 20:11:50 +00:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Arm Ltd.
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// based on the H6 dtsi, which is:
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// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h616-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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2022-09-10 23:04:41 +00:00
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#include <dt-bindings/clock/sun6i-rtc.h>
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2021-01-11 20:11:50 +00:00
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#include <dt-bindings/reset/sun50i-h616-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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};
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};
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2022-09-10 23:04:41 +00:00
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* 256 KiB reserved for Trusted Firmware-A (BL31).
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* This is added by BL31 itself, but some bootloaders fail
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* to propagate this into the DTB handed to kernels.
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*/
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secmon@40000000 {
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reg = <0x0 0x40000000 0x0 0x40000>;
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no-map;
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};
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};
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osc24M: osc24M-clk {
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2021-01-11 20:11:50 +00:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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syscon: syscon@3000000 {
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compatible = "allwinner,sun50i-h616-system-control";
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reg = <0x03000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c: sram@28000 {
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compatible = "mmio-sram";
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reg = <0x00028000 0x30000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00028000 0x30000>;
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};
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};
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h616-ccu";
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reg = <0x03001000 0x1000>;
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2022-09-10 23:04:41 +00:00
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clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
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2021-01-11 20:11:50 +00:00
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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watchdog: watchdog@30090a0 {
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compatible = "allwinner,sun50i-h616-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x030090a0 0x20>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h616-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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2022-09-10 23:04:41 +00:00
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
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2021-01-11 20:11:50 +00:00
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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ext_rgmii_pins: rgmii-pins {
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pins = "PI0", "PI1", "PI2", "PI3", "PI4",
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"PI5", "PI7", "PI8", "PI9", "PI10",
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"PI11", "PI12", "PI13", "PI14", "PI15",
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"PI16";
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function = "emac0";
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drive-strength = <40>;
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};
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i2c0_pins: i2c0-pins {
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pins = "PI6", "PI7";
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function = "i2c0";
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};
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i2c3_ph_pins: i2c3-ph-pins {
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pins = "PH4", "PH5";
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function = "i2c3";
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};
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2022-09-10 23:04:41 +00:00
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ir_rx_pin: ir-rx-pin {
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2021-01-11 20:11:50 +00:00
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pins = "PH10";
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function = "ir_rx";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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2021-01-11 20:11:50 +00:00
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC0", "PC1", "PC5", "PC6",
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"PC8", "PC9", "PC10", "PC11",
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"PC13", "PC14", "PC15", "PC16";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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2021-01-11 20:11:50 +00:00
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spi0_pins: spi0-pins {
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2022-09-10 23:04:41 +00:00
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pins = "PC0", "PC2", "PC4";
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2021-01-11 20:11:50 +00:00
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function = "spi0";
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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spi0_cs0_pin: spi0-cs0-pin {
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pins = "PC3";
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function = "spi0";
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};
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/omit-if-no-ref/
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2021-01-11 20:11:50 +00:00
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spi1_pins: spi1-pins {
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pins = "PH6", "PH7", "PH8";
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function = "spi1";
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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spi1_cs0_pin: spi1-cs0-pin {
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2021-01-11 20:11:50 +00:00
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pins = "PH5";
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function = "spi1";
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};
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uart0_ph_pins: uart0-ph-pins {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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2021-01-11 20:11:50 +00:00
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uart1_pins: uart1-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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2022-09-10 23:04:41 +00:00
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/omit-if-no-ref/
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2021-01-11 20:11:50 +00:00
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uart1_rts_cts_pins: uart1-rts-cts-pins {
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pins = "PG8", "PG9";
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function = "uart1";
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};
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h616-mmc",
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"allwinner,sun50i-a100-mmc";
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reg = <0x04020000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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2022-09-10 23:04:41 +00:00
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max-frequency = <150000000>;
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2021-01-11 20:11:50 +00:00
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-3_3v;
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cap-sdio-irq;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun50i-h616-mmc",
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"allwinner,sun50i-a100-mmc";
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reg = <0x04021000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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status = "disabled";
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2022-09-10 23:04:41 +00:00
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max-frequency = <150000000>;
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2021-01-11 20:11:50 +00:00
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-3_3v;
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cap-sdio-irq;
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#address-cells = <1>;
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|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@4022000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-emmc",
|
|
|
|
|
"allwinner,sun50i-a100-emmc";
|
|
|
|
|
reg = <0x04022000 0x1000>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
|
|
|
clock-names = "ahb", "mmc";
|
|
|
|
|
resets = <&ccu RST_BUS_MMC2>;
|
|
|
|
|
reset-names = "ahb";
|
|
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&mmc2_pins>;
|
|
|
|
|
status = "disabled";
|
2022-09-10 23:04:41 +00:00
|
|
|
max-frequency = <150000000>;
|
2021-01-11 20:11:50 +00:00
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
|
mmc-ddr-3_3v;
|
|
|
|
|
cap-sdio-irq;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart0: serial@5000000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05000000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1: serial@5000400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05000400 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: serial@5000800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05000800 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: serial@5000c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05000c00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: serial@5001000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05001000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART4>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART4>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@5001400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x05001400 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_UART5>;
|
|
|
|
|
resets = <&ccu RST_BUS_UART5>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c0: i2c@5002000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x05002000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
|
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@5002400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x05002400 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
|
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@5002800 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x05002800 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
|
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@5002c00 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x05002c00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_I2C3>;
|
|
|
|
|
resets = <&ccu RST_BUS_I2C3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c4: i2c@5003000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x05003000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_I2C4>;
|
|
|
|
|
resets = <&ccu RST_BUS_I2C4>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi0: spi@5010000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-spi",
|
|
|
|
|
"allwinner,sun8i-h3-spi";
|
|
|
|
|
reg = <0x05010000 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
resets = <&ccu RST_BUS_SPI0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1: spi@5011000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-spi",
|
|
|
|
|
"allwinner,sun8i-h3-spi";
|
|
|
|
|
reg = <0x05011000 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
resets = <&ccu RST_BUS_SPI1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emac0: ethernet@5020000 {
|
2022-09-10 23:04:41 +00:00
|
|
|
compatible = "allwinner,sun50i-h616-emac0",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun50i-a64-emac";
|
|
|
|
|
reg = <0x05020000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "macirq";
|
|
|
|
|
clocks = <&ccu CLK_BUS_EMAC0>;
|
|
|
|
|
clock-names = "stmmaceth";
|
2022-09-10 23:04:41 +00:00
|
|
|
resets = <&ccu RST_BUS_EMAC0>;
|
2021-01-11 20:11:50 +00:00
|
|
|
reset-names = "stmmaceth";
|
2022-09-10 23:04:41 +00:00
|
|
|
syscon = <&syscon>;
|
2021-01-11 20:11:50 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
|
2022-09-10 23:04:41 +00:00
|
|
|
mdio0: mdio {
|
2021-01-11 20:11:50 +00:00
|
|
|
compatible = "snps,dwmac-mdio";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2023-01-12 11:22:20 +00:00
|
|
|
usbotg: usb@5100000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-musb",
|
|
|
|
|
"allwinner,sun8i-h3-musb";
|
|
|
|
|
reg = <0x05100000 0x0400>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OTG>;
|
|
|
|
|
resets = <&ccu RST_BUS_OTG>;
|
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
phys = <&usbphy 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
extcon = <&usbphy 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbphy: phy@5100400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-usb-phy";
|
|
|
|
|
reg = <0x05100400 0x24>,
|
|
|
|
|
<0x05101800 0x14>,
|
|
|
|
|
<0x05200800 0x14>,
|
|
|
|
|
<0x05310800 0x14>,
|
|
|
|
|
<0x05311800 0x14>;
|
|
|
|
|
reg-names = "phy_ctrl",
|
|
|
|
|
"pmu0",
|
|
|
|
|
"pmu1",
|
|
|
|
|
"pmu2",
|
|
|
|
|
"pmu3";
|
|
|
|
|
clocks = <&ccu CLK_USB_PHY0>,
|
|
|
|
|
<&ccu CLK_USB_PHY1>,
|
|
|
|
|
<&ccu CLK_USB_PHY2>,
|
|
|
|
|
<&ccu CLK_USB_PHY3>,
|
|
|
|
|
<&ccu CLK_BUS_EHCI2>;
|
|
|
|
|
clock-names = "usb0_phy",
|
|
|
|
|
"usb1_phy",
|
|
|
|
|
"usb2_phy",
|
|
|
|
|
"usb3_phy",
|
|
|
|
|
"pmu2_clk";
|
|
|
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
|
|
|
<&ccu RST_USB_PHY1>,
|
|
|
|
|
<&ccu RST_USB_PHY2>,
|
|
|
|
|
<&ccu RST_USB_PHY3>;
|
|
|
|
|
reset-names = "usb0_reset",
|
|
|
|
|
"usb1_reset",
|
|
|
|
|
"usb2_reset",
|
|
|
|
|
"usb3_reset";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#phy-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci0: usb@5101000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ehci",
|
|
|
|
|
"generic-ehci";
|
|
|
|
|
reg = <0x05101000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
|
|
|
<&ccu CLK_BUS_EHCI0>,
|
|
|
|
|
<&ccu CLK_USB_OHCI0>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI0>,
|
|
|
|
|
<&ccu RST_BUS_EHCI0>;
|
|
|
|
|
phys = <&usbphy 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci0: usb@5101400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ohci",
|
|
|
|
|
"generic-ohci";
|
|
|
|
|
reg = <0x05101400 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
|
|
|
<&ccu CLK_USB_OHCI0>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI0>;
|
|
|
|
|
phys = <&usbphy 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci1: usb@5200000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ehci",
|
|
|
|
|
"generic-ehci";
|
|
|
|
|
reg = <0x05200000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
|
|
|
<&ccu CLK_BUS_EHCI1>,
|
|
|
|
|
<&ccu CLK_USB_OHCI1>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI1>,
|
|
|
|
|
<&ccu RST_BUS_EHCI1>;
|
|
|
|
|
phys = <&usbphy 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci1: usb@5200400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ohci",
|
|
|
|
|
"generic-ohci";
|
|
|
|
|
reg = <0x05200400 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
|
|
|
<&ccu CLK_USB_OHCI1>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI1>;
|
|
|
|
|
phys = <&usbphy 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci2: usb@5310000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ehci",
|
|
|
|
|
"generic-ehci";
|
|
|
|
|
reg = <0x05310000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI2>,
|
|
|
|
|
<&ccu CLK_BUS_EHCI2>,
|
|
|
|
|
<&ccu CLK_USB_OHCI2>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI2>,
|
|
|
|
|
<&ccu RST_BUS_EHCI2>;
|
|
|
|
|
phys = <&usbphy 2>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci2: usb@5310400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ohci",
|
|
|
|
|
"generic-ohci";
|
|
|
|
|
reg = <0x05310400 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI2>,
|
|
|
|
|
<&ccu CLK_USB_OHCI2>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI2>;
|
|
|
|
|
phys = <&usbphy 2>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci3: usb@5311000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ehci",
|
|
|
|
|
"generic-ehci";
|
|
|
|
|
reg = <0x05311000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI3>,
|
|
|
|
|
<&ccu CLK_BUS_EHCI3>,
|
|
|
|
|
<&ccu CLK_USB_OHCI3>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI3>,
|
|
|
|
|
<&ccu RST_BUS_EHCI3>;
|
|
|
|
|
phys = <&usbphy 3>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci3: usb@5311400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-ohci",
|
|
|
|
|
"generic-ohci";
|
|
|
|
|
reg = <0x05311400 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ccu CLK_BUS_OHCI3>,
|
|
|
|
|
<&ccu CLK_USB_OHCI3>;
|
|
|
|
|
resets = <&ccu RST_BUS_OHCI3>;
|
|
|
|
|
phys = <&usbphy 3>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2021-01-11 20:11:50 +00:00
|
|
|
rtc: rtc@7000000 {
|
2022-09-10 23:04:41 +00:00
|
|
|
compatible = "allwinner,sun50i-h616-rtc";
|
2021-01-11 20:11:50 +00:00
|
|
|
reg = <0x07000000 0x400>;
|
2022-09-10 23:04:41 +00:00
|
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
|
|
|
|
|
<&ccu CLK_PLL_SYSTEM_32K>;
|
|
|
|
|
clock-names = "bus", "hosc",
|
|
|
|
|
"pll-32k";
|
2021-01-11 20:11:50 +00:00
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r_ccu: clock@7010000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-r-ccu";
|
2022-09-10 23:04:41 +00:00
|
|
|
reg = <0x07010000 0x210>;
|
|
|
|
|
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
|
2021-01-11 20:11:50 +00:00
|
|
|
<&ccu CLK_PLL_PERIPH0>;
|
|
|
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r_pio: pinctrl@7022000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-r-pinctrl";
|
|
|
|
|
reg = <0x07022000 0x400>;
|
2022-09-10 23:04:41 +00:00
|
|
|
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
|
|
|
|
|
<&rtc CLK_OSC32K>;
|
2021-01-11 20:11:50 +00:00
|
|
|
clock-names = "apb", "hosc", "losc";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <3>;
|
|
|
|
|
|
2022-09-10 23:04:41 +00:00
|
|
|
/omit-if-no-ref/
|
2021-01-11 20:11:50 +00:00
|
|
|
r_i2c_pins: r-i2c-pins {
|
|
|
|
|
pins = "PL0", "PL1";
|
|
|
|
|
function = "s_i2c";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r_rsb_pins: r-rsb-pins {
|
|
|
|
|
pins = "PL0", "PL1";
|
|
|
|
|
function = "s_rsb";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ir: ir@7040000 {
|
2022-09-10 23:04:41 +00:00
|
|
|
compatible = "allwinner,sun50i-h616-ir",
|
|
|
|
|
"allwinner,sun6i-a31-ir";
|
|
|
|
|
reg = <0x07040000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&r_ccu CLK_R_APB1_IR>,
|
|
|
|
|
<&r_ccu CLK_IR>;
|
|
|
|
|
clock-names = "apb", "ir";
|
|
|
|
|
resets = <&r_ccu RST_R_APB1_IR>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&ir_rx_pin>;
|
|
|
|
|
status = "disabled";
|
2021-01-11 20:11:50 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r_i2c: i2c@7081400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-i2c",
|
2022-09-10 23:04:41 +00:00
|
|
|
"allwinner,sun8i-v536-i2c",
|
2021-01-11 20:11:50 +00:00
|
|
|
"allwinner,sun6i-a31-i2c";
|
|
|
|
|
reg = <0x07081400 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&r_ccu CLK_R_APB2_I2C>;
|
|
|
|
|
resets = <&r_ccu RST_R_APB2_I2C>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r_rsb: rsb@7083000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h616-rsb",
|
|
|
|
|
"allwinner,sun8i-a23-rsb";
|
|
|
|
|
reg = <0x07083000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&r_ccu CLK_R_APB2_RSB>;
|
|
|
|
|
clock-frequency = <3000000>;
|
|
|
|
|
resets = <&r_ccu RST_R_APB2_RSB>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&r_rsb_pins>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
