2020-12-14 05:54:27 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/clock/ast2600-clock.h>
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#include <dt-bindings/reset/ast2600-reset.h>
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#include "ast2600.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2600-scu";
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reg = <0x1e6e2000 0x1000>;
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2020-12-14 05:54:27 +00:00
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#clock-cells = <1>;
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#reset-cells = <1>;
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uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
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};
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rst: reset-controller {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2020-12-14 05:54:27 +00:00
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compatible = "aspeed,ast2600-reset";
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aspeed,wdt = <&wdt1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2020-12-14 05:54:27 +00:00
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compatible = "aspeed,ast2600-sdrammc";
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reg = <0x1e6e0000 0x100
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0x1e6e0100 0x300
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0x1e6e0400 0x200 >;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_MPLL>;
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resets = <&rst ASPEED_RESET_SDRAM>;
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};
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ahb {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2020-12-14 05:54:27 +00:00
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apb {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2020-12-14 05:54:27 +00:00
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};
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};
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};
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