2022-03-02 07:09:05 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021
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* lixinde <lixinde@phytium.com.cn>
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* weichangzheng <weichangzheng@phytium.com.cn>
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*/
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#include <stdio.h>
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#include <command.h>
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <linux/arm-smccc.h>
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#include <scsi.h>
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#include <init.h>
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#include <asm/u-boot.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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debug("Phytium ddr init\n");
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ddr_init();
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gd->mem_clk = 0;
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2022-11-16 18:10:37 +00:00
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
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2022-03-02 07:09:05 +00:00
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sec_init();
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debug("PBF relocate done\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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void reset_cpu(void)
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{
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struct arm_smccc_res res;
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debug("run in reset cpu\n");
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arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
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if (res.a0 != 0)
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panic("reset cpu error, %lx\n", res.a0);
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}
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int mach_cpu_init(void)
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{
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check_reset();
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return 0;
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}
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int board_early_init_f(void)
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{
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pcie_init();
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return 0;
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}
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static struct mm_region pomelo_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN |
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PTE_BLOCK_UXN
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},
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x7b000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NS |
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PTE_BLOCK_INNER_SHARE
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = pomelo_mem_map;
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int __asm_flush_l3_dcache(void)
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{
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int i, pstate;
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
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for (i = 0; i < HNF_COUNT; i++) {
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do {
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pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
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} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
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}
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
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return 0;
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}
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int last_stage_init(void)
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{
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int ret;
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/* pci e */
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pci_init();
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/* scsi scan */
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ret = scsi_scan(true);
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if (ret) {
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printf("scsi scan failed\n");
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return CMD_RET_FAILURE;
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}
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return ret;
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}
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