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62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*/
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#ifndef __PINCTRL_MXS_H
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#define __PINCTRL_MXS_H
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#include <dm/pinctrl.h>
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#define SET 0x4
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#define CLR 0x8
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#define TOG 0xc
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#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
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#define PINID(bank, pin) ((bank) * 32 + (pin))
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/*
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* pinmux-id bit field definitions
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*
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* bank: 15..12 (4)
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* pin: 11..4 (8)
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* muxsel: 3..0 (4)
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*/
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#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
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#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
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#define PINID_TO_BANK(p) ((p) >> 5)
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#define PINID_TO_PIN(p) ((p) % 32)
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/*
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* pin config bit field definitions
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*
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* pull-up: 6..5 (2)
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* voltage: 4..3 (2)
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* mA: 2..0 (3)
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*
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* MSB of each field is presence bit for the config.
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*/
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#define PULL_PRESENT (1 << 6)
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#define PULL_SHIFT 5
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#define VOL_PRESENT (1 << 4)
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#define VOL_SHIFT 3
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#define MA_PRESENT (1 << 2)
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#define MA_SHIFT 0
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#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
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#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
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#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
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struct mxs_regs {
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u16 muxsel;
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u16 drive;
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u16 pull;
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};
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static inline void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift,
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void __iomem *reg)
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{
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clrsetbits_le32(reg, mask << shift, value << shift);
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}
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#endif /* __PINCTRL_MXS_H */
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