2021-08-07 08:00:35 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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2021-08-07 08:00:45 +00:00
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* Copyright 2021 NXP
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2021-08-07 08:00:35 +00:00
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*/
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#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
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#define _ASM_ARCH_IMX8ULP_CLOCK_H
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/* Mainly for compatible to imx common code. */
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_AHB_CLK,
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MXC_IPG_CLK,
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MXC_UART_CLK,
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MXC_CSPI_CLK,
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MXC_AXI_CLK,
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MXC_DDR_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_I2C_CLK,
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};
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u32 mxc_get_clock(enum mxc_clock clk);
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u32 get_lpuart_clk(void);
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#ifdef CONFIG_SYS_I2C_IMX_LPI2C
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int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
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u32 imx_get_i2cclk(unsigned int i2c_num);
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#endif
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void enable_usboh3_clk(unsigned char enable);
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int enable_usb_pll(ulong usb_phy_base);
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2021-08-07 08:00:35 +00:00
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable);
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#endif
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void init_clk_usdhc(u32 index);
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void init_clk_fspi(int index);
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void init_clk_ddr(void);
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int set_ddr_clk(u32 phy_freq_mhz);
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2021-08-07 08:00:35 +00:00
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void clock_init(void);
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2021-08-07 08:00:45 +00:00
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void cgc1_enet_stamp_sel(u32 clk_src);
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2021-08-07 08:00:35 +00:00
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#endif
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