2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2002-10-21 17:04:47 +00:00
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/*
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2010-07-24 18:22:02 +00:00
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* (C) Copyright 2002-2010
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2002-10-21 17:04:47 +00:00
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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2012-12-13 20:48:30 +00:00
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2021-02-23 06:34:37 +00:00
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#ifndef __ASSEMBLY__
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2021-06-03 13:39:02 +00:00
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#include <config.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/types.h>
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#include <linux/types.h>
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2012-12-13 20:48:30 +00:00
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/* Architecture-specific global data */
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struct arch_global_data {
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2019-06-21 03:42:28 +00:00
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#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
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2012-12-13 20:49:05 +00:00
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u32 sdhc_clk;
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#endif
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2014-09-25 05:52:25 +00:00
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2019-12-19 10:59:28 +00:00
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_per_clk;
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#endif
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2014-09-25 05:52:25 +00:00
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#if defined(CONFIG_U_QE)
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u32 qe_clk;
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u32 brg_clk;
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uint mp_alloc_base;
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uint mp_alloc_top;
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#endif /* CONFIG_U_QE */
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2012-12-13 20:48:31 +00:00
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#ifdef CONFIG_AT91FAMILY
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/* "static data" needed by at91's clock.c */
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unsigned long cpu_clk_rate_hz;
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unsigned long main_clk_rate_hz;
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unsigned long mck_rate_hz;
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unsigned long plla_rate_hz;
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unsigned long pllb_rate_hz;
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unsigned long at91_pllb_usb_init;
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#endif
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2012-12-13 20:48:32 +00:00
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/* "static data" needed by most of timer.c on ARM platforms */
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unsigned long timer_rate_hz;
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2017-05-09 02:32:02 +00:00
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unsigned int tbu;
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unsigned int tbl;
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2012-12-13 20:48:35 +00:00
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unsigned long lastinc;
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2012-12-13 20:48:36 +00:00
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unsigned long long timer_reset_value;
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2019-05-03 13:41:00 +00:00
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#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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2012-12-13 20:48:39 +00:00
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unsigned long tlb_addr;
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2016-03-04 00:09:47 +00:00
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unsigned long tlb_size;
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2016-03-04 00:09:54 +00:00
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#if defined(CONFIG_ARM64)
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2016-03-04 00:09:47 +00:00
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unsigned long tlb_fillptr;
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unsigned long tlb_emerg;
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2023-03-17 16:22:52 +00:00
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unsigned int first_block_level;
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2023-03-17 16:22:51 +00:00
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bool has_hafdbs;
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2015-10-14 16:55:45 +00:00
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#endif
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2012-12-13 20:48:39 +00:00
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#endif
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2022-11-16 18:10:41 +00:00
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#ifdef CFG_SYS_MEM_RESERVE_SECURE
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2016-06-24 23:46:18 +00:00
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#define MEM_RESERVE_SECURE_SECURED 0x1
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#define MEM_RESERVE_SECURE_MAINTAINED 0x2
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#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
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/*
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* Secure memory addr
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* This variable needs maintenance if the RAM base is not zero,
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* or if RAM splits into non-consecutive banks. It also has a
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* flag indicating the secure memory is marked as secure by MMU.
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* Flags used: 0x1 secured
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* 0x2 maintained
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*/
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phys_addr_t secure_ram;
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2016-06-24 23:46:19 +00:00
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unsigned long tlb_allocated;
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2016-06-24 23:46:18 +00:00
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#endif
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2017-03-06 17:02:24 +00:00
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#ifdef CONFIG_RESV_RAM
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/*
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* Reserved RAM for memory resident, eg. Management Complex (MC)
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* driver which continues to run after U-Boot exits.
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*/
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phys_addr_t resv_ram;
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#endif
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2013-04-24 00:41:23 +00:00
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2017-04-25 04:10:11 +00:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
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2015-07-15 14:02:19 +00:00
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u32 omap_boot_device;
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u32 omap_boot_mode;
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u8 omap_ch_flags;
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2013-04-24 00:41:23 +00:00
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#endif
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2015-11-09 11:12:07 +00:00
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#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
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2015-01-06 21:18:49 +00:00
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unsigned long mem2_clk;
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#endif
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2018-10-18 12:28:10 +00:00
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#ifdef CONFIG_ARCH_IMX8
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struct udevice *scu_dev;
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#endif
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2021-08-07 08:00:41 +00:00
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2022-07-26 08:40:49 +00:00
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#ifdef CONFIG_IMX_SENTINEL
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2021-08-07 08:00:41 +00:00
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struct udevice *s400_dev;
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2022-07-26 08:40:56 +00:00
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u32 soc_rev;
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u32 lifecycle;
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u32 uid[4];
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2021-08-07 08:00:41 +00:00
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#endif
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2023-01-31 08:42:17 +00:00
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#ifdef CONFIG_ARCH_IMX8ULP
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bool m33_handshake_done;
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#endif
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2012-12-13 20:48:30 +00:00
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};
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2012-12-13 20:49:14 +00:00
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#include <asm-generic/global_data.h>
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2002-10-21 17:04:47 +00:00
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2022-08-03 18:13:08 +00:00
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#if defined(__clang__) || defined(LTO_ENABLE)
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2014-07-30 19:54:52 +00:00
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#define DECLARE_GLOBAL_DATA_PTR
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#define gd get_gd()
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static inline gd_t *get_gd(void)
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{
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gd_t *gd_ptr;
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#ifdef CONFIG_ARM64
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__asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
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#else
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__asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
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#endif
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return gd_ptr;
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}
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#else
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2013-12-14 03:47:35 +00:00
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#ifdef CONFIG_ARM64
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
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#else
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
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#endif
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2014-07-30 19:54:52 +00:00
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#endif
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2002-10-21 17:04:47 +00:00
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2020-05-26 23:58:30 +00:00
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static inline void set_gd(volatile gd_t *gd_ptr)
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{
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#ifdef CONFIG_ARM64
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__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
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2021-05-20 11:24:09 +00:00
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#elif __ARM_ARCH >= 7
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2020-05-26 23:58:30 +00:00
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__asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
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2021-05-20 11:24:09 +00:00
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#else
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__asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr));
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2020-05-26 23:58:30 +00:00
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#endif
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}
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2021-02-23 06:34:37 +00:00
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#endif /* __ASSEMBLY__ */
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2002-10-21 17:04:47 +00:00
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#endif /* __ASM_GBL_DATA_H */
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