u-boot/arch/powerpc/dts/p1010si-post.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * P1010 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2020 NXP
 */

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "fsl,p1010-immr", "simple-bus";
	bus-frequency = <0>;

	mpic: pic@40000 {
		interrupt-controller;
		#address-cells = <0>;
		#interrupt-cells = <4>;
		reg = <0x40000 0x40000>;
		compatible = "fsl,mpic";
		device_type = "open-pic";
		big-endian;
		single-cpu-affinity;
		last-interrupt-source = <255>;
	};

	espi0: spi@7000 {
		compatible = "fsl,mpc8536-espi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x7000 0x1000>;
		fsl,espi-num-chipselects = <1>;
		status = "disabled";
	};

/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"

/include/ "pq3-etsec2-0.dtsi"
	enet0: ethernet@b0000 {
		queue-group@b0000 {
			fsl,rx-bit-map = <0xff>;
			fsl,tx-bit-map = <0xff>;
		};
	};

/include/ "pq3-etsec2-1.dtsi"
	enet1: ethernet@b1000 {
		queue-group@b1000 {
			fsl,rx-bit-map = <0xff>;
			fsl,tx-bit-map = <0xff>;
		};
	};

/include/ "pq3-etsec2-2.dtsi"
	enet2: ethernet@b2000 {
		queue-group@b2000 {
			fsl,rx-bit-map = <0xff>;
			fsl,tx-bit-map = <0xff>;
		};

	};
};

/* controller at 0x9000 */
&pci1 {
	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
	law_trgt_if = <1>;
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	bus-range = <0x0 0xff>;
};

/* controller at 0xa000 */
&pci0 {
	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
	law_trgt_if = <2>;
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	bus-range = <0x0 0xff>;
};