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38 lines
724 B
C
38 lines
724 B
C
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/*
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* Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (c) 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __serial_sh_h
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#define __serial_sh_h
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enum sh_clk_mode {
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INT_CLK,
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EXT_CLK,
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};
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enum sh_serial_type {
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PORT_SCI,
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PORT_SCIF,
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PORT_SCIFA,
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PORT_SCIFB,
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};
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/*
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* Information about SCIF port
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*
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* @base: Register base address
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* @clk: Input clock rate, used for calculating the baud rate divisor
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* @clk_mode: Clock mode, set internal (INT) or external (EXT)
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* @type: Type of SCIF
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*/
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struct sh_serial_platdata {
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unsigned long base;
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unsigned int clk;
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enum sh_clk_mode clk_mode;
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enum sh_serial_type type;
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};
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#endif /* __serial_sh_h */
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