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u-boot/arch/riscv/cpu/ax25/Kconfig

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riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 09:34:06 +08:00
config RISCV_NDS
riscv: ax25: Hide the ax25-specific Kconfig option There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-12 06:12:28 -08:00
bool
riscv: ax25: Add platform-specific Kconfig options Add ax25 RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Also disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 15:56:41 +08:00
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 21:14:43 +02:00
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 09:34:06 +08:00
help
riscv: ax25: Hide the ax25-specific Kconfig option There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-12 06:12:28 -08:00
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
if RISCV_NDS
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 21:14:43 +02:00
depends on RISCV_MMODE || SPL_RISCV_MMODE
riscv: ax25: Hide the ax25-specific Kconfig option There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-12 06:12:28 -08:00
help
Provide Andes Technology AndeStar V5 families specific cache support.
endif
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