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https://github.com/AsahiLinux/u-boot
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168 lines
3.3 KiB
C
168 lines
3.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __OCTEONTX_BCH_REGS_H__
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#define __OCTEONTX_BCH_REGS_H__
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#define BCH_NR_VF 1
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union bch_cmd {
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u64 u[4];
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struct fields {
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struct {
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u64 size:12;
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u64 reserved_12_31:20;
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u64 ecc_level:4;
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u64 reserved_36_61:26;
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u64 ecc_gen:2;
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} cword;
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struct {
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u64 ptr:49;
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u64 reserved_49_55:7;
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u64 nc:1;
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u64 fw:1;
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u64 reserved_58_63:6;
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} oword;
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struct {
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u64 ptr:49;
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u64 reserved_49_55:7;
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u64 nc:1;
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u64 reserved_57_63:7;
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} iword;
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struct {
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u64 ptr:49;
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u64 reserved_49_63:15;
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} rword;
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} s;
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};
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enum ecc_gen {
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eg_correct,
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eg_copy,
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eg_gen,
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eg_copy3,
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};
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/** Response from BCH instruction */
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union bch_resp {
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u16 u16;
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struct {
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u16 num_errors:7; /** Number of errors in block */
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u16 zero:6; /** Always zero, ignore */
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u16 erased:1; /** Block is erased */
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u16 uncorrectable:1;/** too many bits flipped */
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u16 done:1; /** Block is done */
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} s;
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};
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union bch_vqx_ctl {
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u64 u;
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struct {
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u64 reserved_0:1;
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u64 cmd_be:1;
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u64 max_read:4;
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u64 reserved_6_15:10;
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u64 erase_disable:1;
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u64 one_cmd:1;
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u64 early_term:4;
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u64 reserved_22_63:42;
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} s;
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};
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union bch_vqx_cmd_buf {
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u64 u;
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struct {
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u64 reserved_0_32:33;
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u64 size:13;
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u64 dfb:1;
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u64 ldwb:1;
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u64 reserved_48_63:16;
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} s;
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};
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/* keep queue state indexed, even though just one supported here,
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* for later generalization to similarly-shaped queues on other Cavium devices
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*/
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enum {
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QID_BCH,
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QID_MAX
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};
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struct bch_q {
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struct udevice *dev;
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int index;
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u16 max_depth;
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u16 pool_size_m1;
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u64 *base_vaddr;
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dma_addr_t base_paddr;
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};
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extern struct bch_q octeontx_bch_q[QID_MAX];
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/* with one dma-mapped area, virt<->phys conversions by +/- (vaddr-paddr) */
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static inline dma_addr_t qphys(int qid, void *v)
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{
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struct bch_q *q = &octeontx_bch_q[qid];
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int off = (u8 *)v - (u8 *)q->base_vaddr;
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return q->base_paddr + off;
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}
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#define octeontx_ptr_to_phys(v) qphys(QID_BCH, (v))
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static inline void *qvirt(int qid, dma_addr_t p)
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{
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struct bch_q *q = &octeontx_bch_q[qid];
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int off = p - q->base_paddr;
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return q->base_vaddr + off;
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}
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#define octeontx_phys_to_ptr(p) qvirt(QID_BCH, (p))
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/* plenty for interleaved r/w on two planes with 16k page, ecc_size 1k */
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/* QDEPTH >= 16, as successive chunks must align on 128-byte boundaries */
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#define QDEPTH 256 /* u64s in a command queue chunk, incl next-pointer */
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#define NQS 1 /* linked chunks in the chain */
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/**
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* Write an arbitrary number of command words to a command queue.
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* This is a generic function; the fixed number of command word
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* functions yield higher performance.
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*
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* Could merge with crypto version for FPA use on cn83xx
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*/
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static inline int octeontx_cmd_queue_write(int queue_id, bool use_locking,
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int cmd_count, const u64 *cmds)
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{
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int ret = 0;
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u64 *cmd_ptr;
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struct bch_q *qptr = &octeontx_bch_q[queue_id];
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if (unlikely(cmd_count < 1 || cmd_count > 32))
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return -EINVAL;
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if (unlikely(!cmds))
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return -EINVAL;
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cmd_ptr = qptr->base_vaddr;
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while (cmd_count > 0) {
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int slot = qptr->index % (QDEPTH * NQS);
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if (slot % QDEPTH != QDEPTH - 1) {
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cmd_ptr[slot] = *cmds++;
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cmd_count--;
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}
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qptr->index++;
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}
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__iowmb(); /* flush commands before ringing bell */
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return ret;
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}
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#endif /* __OCTEONTX_BCH_REGS_H__ */
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