2008-10-22 11:38:21 +00:00
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/*
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* MCF5301x Internal Memory Map
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2008-10-22 11:38:21 +00:00
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*/
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#ifndef __IMMAP_5301X__
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#define __IMMAP_5301X__
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#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
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#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
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#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
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#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
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#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
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#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
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#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
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#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
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#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
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#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
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#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
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#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
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#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
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#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
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#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
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#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
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#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
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#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
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#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
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#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
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#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
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#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
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#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
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#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
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#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
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#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
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#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
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#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
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#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
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#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
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#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
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#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
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#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
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#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
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#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
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#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
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#include <asm/coldfire/crossbar.h>
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#include <asm/coldfire/dspi.h>
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#include <asm/coldfire/edma.h>
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/ssi.h>
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#include <asm/coldfire/rng.h>
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#include <asm/rtc.h>
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/* System Controller Module */
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typedef struct scm1 {
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u32 mpr; /* 0x00 Master Privilege */
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u32 rsvd1[7];
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u32 pacra; /* 0x20 Peripheral Access Ctrl A */
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u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
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u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
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u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
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u32 rsvd2[4];
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u32 pacre; /* 0x40 Peripheral Access Ctrl E */
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u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
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u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
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} scm1_t;
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typedef struct scm2 {
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u8 rsvd1[19]; /* 0x00 - 0x12 */
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u8 wcr; /* 0x13 */
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u16 rsvd2; /* 0x14 - 0x15 */
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u16 cwcr; /* 0x16 */
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u8 rsvd3[3]; /* 0x18 - 0x1A */
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u8 cwsr; /* 0x1B */
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u8 rsvd4[3]; /* 0x1C - 0x1E */
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u8 scmisr; /* 0x1F */
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u32 rsvd5; /* 0x20 - 0x23 */
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u8 bcr; /* 0x24 */
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u8 rsvd6[74]; /* 0x25 - 0x6F */
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u32 cfadr; /* 0x70 */
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u8 rsvd7; /* 0x74 */
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u8 cfier; /* 0x75 */
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u8 cfloc; /* 0x76 */
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u8 cfatr; /* 0x77 */
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u32 rsvd8; /* 0x78 - 0x7B */
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u32 cfdtr; /* 0x7C */
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} scm2_t;
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/* PWM module */
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typedef struct pwm_ctrl {
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u8 en; /* 0x00 PWM Enable */
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u8 pol; /* 0x01 Polarity */
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u8 clk; /* 0x02 Clock Select */
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u8 prclk; /* 0x03 Prescale Clock Select */
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u8 cae; /* 0x04 Center Align Enable */
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u8 ctl; /* 0x05 Ctrl */
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u8 res1[2]; /* 0x06 - 0x07 */
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u8 scla; /* 0x08 Scale A */
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u8 sclb; /* 0x09 Scale B */
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u8 res2[2]; /* 0x0A - 0x0B */
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u8 cnt0; /* 0x0C Channel 0 Counter */
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u8 cnt1; /* 0x0D Channel 1 Counter */
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u8 cnt2; /* 0x0E Channel 2 Counter */
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u8 cnt3; /* 0x0F Channel 3 Counter */
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u8 cnt4; /* 0x10 Channel 4 Counter */
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u8 cnt5; /* 0x11 Channel 5 Counter */
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u8 cnt6; /* 0x12 Channel 6 Counter */
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u8 cnt7; /* 0x13 Channel 7 Counter */
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u8 per0; /* 0x14 Channel 0 Period */
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u8 per1; /* 0x15 Channel 1 Period */
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u8 per2; /* 0x16 Channel 2 Period */
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u8 per3; /* 0x17 Channel 3 Period */
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u8 per4; /* 0x18 Channel 4 Period */
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u8 per5; /* 0x19 Channel 5 Period */
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u8 per6; /* 0x1A Channel 6 Period */
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u8 per7; /* 0x1B Channel 7 Period */
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u8 dty0; /* 0x1C Channel 0 Duty */
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u8 dty1; /* 0x1D Channel 1 Duty */
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u8 dty2; /* 0x1E Channel 2 Duty */
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u8 dty3; /* 0x1F Channel 3 Duty */
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u8 dty4; /* 0x20 Channel 4 Duty */
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u8 dty5; /* 0x21 Channel 5 Duty */
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u8 dty6; /* 0x22 Channel 6 Duty */
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u8 dty7; /* 0x23 Channel 7 Duty */
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u8 sdn; /* 0x24 Shutdown */
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u8 res3[3]; /* 0x25 - 0x27 */
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} pwm_t;
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/* Chip configuration module */
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typedef struct rcm {
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u8 rcr;
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u8 rsr;
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} rcm_t;
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typedef struct ccm_ctrl {
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u16 ccr; /* 0x00 Chip Cfg */
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u16 res1; /* 0x02 */
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u16 rcon; /* 0x04 Reset Cfg */
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u16 cir; /* 0x06 Chip ID */
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u32 res2; /* 0x08 */
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u16 misccr; /* 0x0A Misc Ctrl */
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u16 cdr; /* 0x0C Clock divider */
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u16 uhcsr; /* 0x10 USB Host status */
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u16 uocsr; /* 0x12 USB On-the-Go Status */
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u16 res3; /* 0x14 */
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u16 codeccr; /* 0x16 Codec Control */
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u16 misccr2; /* 0x18 Misc2 Ctrl */
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} ccm_t;
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/* GPIO port */
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typedef struct gpio_ctrl {
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/* Port Output Data */
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u8 podr_fbctl; /* 0x00 */
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u8 podr_be; /* 0x01 */
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u8 podr_cs; /* 0x02 */
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u8 podr_dspi; /* 0x03 */
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u8 res01; /* 0x04 */
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u8 podr_fec0; /* 0x05 */
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u8 podr_feci2c; /* 0x06 */
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u8 res02[2]; /* 0x07 - 0x08 */
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u8 podr_simp1; /* 0x09 */
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u8 podr_simp0; /* 0x0A */
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u8 podr_timer; /* 0x0B */
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u8 podr_uart; /* 0x0C */
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u8 podr_debug; /* 0x0D */
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u8 res03; /* 0x0E */
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u8 podr_sdhc; /* 0x0F */
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u8 podr_ssi; /* 0x10 */
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u8 res04[3]; /* 0x11 - 0x13 */
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/* Port Data Direction */
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u8 pddr_fbctl; /* 0x14 */
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u8 pddr_be; /* 0x15 */
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u8 pddr_cs; /* 0x16 */
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u8 pddr_dspi; /* 0x17 */
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u8 res05; /* 0x18 */
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u8 pddr_fec0; /* 0x19 */
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u8 pddr_feci2c; /* 0x1A */
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u8 res06[2]; /* 0x1B - 0x1C */
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u8 pddr_simp1; /* 0x1D */
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u8 pddr_simp0; /* 0x1E */
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u8 pddr_timer; /* 0x1F */
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u8 pddr_uart; /* 0x20 */
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u8 pddr_debug; /* 0x21 */
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u8 res07; /* 0x22 */
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u8 pddr_sdhc; /* 0x23 */
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u8 pddr_ssi; /* 0x24 */
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u8 res08[3]; /* 0x25 - 0x27 */
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/* Port Data Direction */
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u8 ppdr_fbctl; /* 0x28 */
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u8 ppdr_be; /* 0x29 */
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u8 ppdr_cs; /* 0x2A */
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u8 ppdr_dspi; /* 0x2B */
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u8 res09; /* 0x2C */
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u8 ppdr_fec0; /* 0x2D */
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u8 ppdr_feci2c; /* 0x2E */
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u8 res10[2]; /* 0x2F - 0x30 */
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u8 ppdr_simp1; /* 0x31 */
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u8 ppdr_simp0; /* 0x32 */
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u8 ppdr_timer; /* 0x33 */
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u8 ppdr_uart; /* 0x34 */
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u8 ppdr_debug; /* 0x35 */
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u8 res11; /* 0x36 */
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u8 ppdr_sdhc; /* 0x37 */
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u8 ppdr_ssi; /* 0x38 */
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u8 res12[3]; /* 0x39 - 0x3B */
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/* Port Clear Output Data */
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u8 pclrr_fbctl; /* 0x3C */
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u8 pclrr_be; /* 0x3D */
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u8 pclrr_cs; /* 0x3E */
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u8 pclrr_dspi; /* 0x3F */
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u8 res13; /* 0x40 */
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u8 pclrr_fec0; /* 0x41 */
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u8 pclrr_feci2c; /* 0x42 */
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u8 res14[2]; /* 0x43 - 0x44 */
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u8 pclrr_simp1; /* 0x45 */
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u8 pclrr_simp0; /* 0x46 */
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u8 pclrr_timer; /* 0x47 */
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u8 pclrr_uart; /* 0x48 */
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u8 pclrr_debug; /* 0x49 */
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u8 res15; /* 0x4A */
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u8 pclrr_sdhc; /* 0x4B */
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u8 pclrr_ssi; /* 0x4C */
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u8 res16[3]; /* 0x4D - 0x4F */
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/* Pin Assignment */
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u8 par_fbctl; /* 0x50 */
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u8 par_be; /* 0x51 */
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u8 par_cs; /* 0x52 */
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u8 res17; /* 0x53 */
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u8 par_dspih; /* 0x54 */
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u8 par_dspil; /* 0x55 */
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u8 par_fec; /* 0x56 */
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u8 par_feci2c; /* 0x57 */
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u8 par_irq0h; /* 0x58 */
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u8 par_irq0l; /* 0x59 */
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u8 par_irq1h; /* 0x5A */
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u8 par_irq1l; /* 0x5B */
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u8 par_simp1h; /* 0x5C */
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u8 par_simp1l; /* 0x5D */
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u8 par_simp0; /* 0x5E */
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u8 par_timer; /* 0x5F */
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u8 par_uart; /* 0x60 */
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u8 res18; /* 0x61 */
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u8 par_debug; /* 0x62 */
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u8 par_sdhc; /* 0x63 */
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u8 par_ssih; /* 0x64 */
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u8 par_ssil; /* 0x65 */
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u8 res19[2]; /* 0x66 - 0x67 */
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/* Mode Select Control */
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/* Drive Strength Control */
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u8 mscr_mscr1; /* 0x68 */
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u8 mscr_mscr2; /* 0x69 */
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u8 mscr_mscr3; /* 0x6A */
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u8 mscr_mscr45; /* 0x6B */
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u8 srcr_dspi; /* 0x6C */
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u8 dscr_fec; /* 0x6D */
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u8 srcr_i2c; /* 0x6E */
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u8 srcr_irq; /* 0x6F */
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u8 srcr_sim; /* 0x70 */
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u8 srcr_timer; /* 0x71 */
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u8 srcr_uart; /* 0x72 */
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u8 res20; /* 0x73 */
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u8 srcr_sdhc; /* 0x74 */
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u8 srcr_ssi; /* 0x75 */
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u8 res21[2]; /* 0x76 - 0x77 */
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u8 pcr_pcrh; /* 0x78 */
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u8 pcr_pcrl; /* 0x79 */
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} gpio_t;
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/* SDRAM controller */
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typedef struct sdram_ctrl {
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u32 mode; /* 0x00 Mode/Extended Mode */
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u32 ctrl; /* 0x04 Ctrl */
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u32 cfg1; /* 0x08 Cfg 1 */
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u32 cfg2; /* 0x0C Cfg 2 */
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u32 res1[64]; /* 0x10 - 0x10F */
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u32 cs0; /* 0x110 Chip Select 0 Cfg */
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u32 cs1; /* 0x114 Chip Select 1 Cfg */
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} sdram_t;
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/* Clock Module */
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typedef struct pll_ctrl {
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u32 pcr; /* 0x00 Ctrl */
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u32 pdr; /* 0x04 Divider */
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u32 psr; /* 0x08 Status */
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} pll_t;
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typedef struct rtcex {
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u32 rsvd1[3];
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u32 gocu;
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u32 gocl;
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} rtcex_t;
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#endif /* __IMMAP_5301X__ */
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