2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2018-03-08 10:00:27 +00:00
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _BMU_H_
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#define _BMU_H_
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#define BMU_VERSION 0x000
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#define BMU_CTRL 0x004
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#define BMU_UCAST_CONFIG 0x008
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#define BMU_UCAST_BASE_ADDR 0x00c
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#define BMU_BUF_SIZE 0x010
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#define BMU_BUF_CNT 0x014
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#define BMU_THRES 0x018
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#define BMU_INT_SRC 0x020
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#define BMU_INT_ENABLE 0x024
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#define BMU_ALLOC_CTRL 0x030
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#define BMU_FREE_CTRL 0x034
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#define BMU_FREE_ERR_ADDR 0x038
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#define BMU_CURR_BUF_CNT 0x03c
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#define BMU_MCAST_CNT 0x040
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#define BMU_MCAST_ALLOC_CTRL 0x044
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#define BMU_REM_BUF_CNT 0x048
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#define BMU_LOW_WATERMARK 0x050
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#define BMU_HIGH_WATERMARK 0x054
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#define BMU_INT_MEM_ACCESS 0x100
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struct bmu_cfg {
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u32 baseaddr;
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u32 count;
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u32 size;
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};
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#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
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#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
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#endif /* _BMU_H_ */
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