2019-02-25 08:15:19 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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2021-09-01 07:01:42 +00:00
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#include <cpu_func.h>
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2019-02-25 08:15:19 +00:00
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#include <dm.h>
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2020-05-10 17:40:03 +00:00
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#include <env.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-05-29 06:03:22 +00:00
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#include <log.h>
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2020-07-15 10:08:58 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:08 +00:00
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#include <linux/bug.h>
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2019-06-25 06:31:44 +00:00
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#include <linux/delay.h>
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2020-05-29 06:03:22 +00:00
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#include <misc.h>
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2020-05-29 06:03:35 +00:00
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#include <spl.h>
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2021-07-27 09:06:59 +00:00
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#include <asm/sections.h>
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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/*
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* This define is a value used for error/unknown serial.
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* If we really care about distinguishing errors and 0 is
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* valid, we'll need a different one.
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*/
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#define ERROR_READING_SERIAL_NUMBER 0
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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#ifdef CONFIG_MISC_INIT_R
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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#if CONFIG_IS_ENABLED(SIFIVE_OTP)
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static u32 otp_read_serialnum(struct udevice *dev)
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2019-06-25 06:31:44 +00:00
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{
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2020-05-29 06:03:22 +00:00
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int ret;
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u32 serial[2] = {0};
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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for (int i = 0xfe * 4; i > 0; i -= 8) {
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ret = misc_read(dev, i, serial, sizeof(serial));
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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if (ret != sizeof(serial)) {
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printf("%s: error reading serial from OTP\n", __func__);
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break;
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}
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2019-06-25 06:31:44 +00:00
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2020-05-29 06:03:22 +00:00
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if (serial[0] == ~serial[1])
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return serial[0];
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2019-06-25 06:31:44 +00:00
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}
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2020-05-29 06:03:22 +00:00
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return ERROR_READING_SERIAL_NUMBER;
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2019-06-25 06:31:44 +00:00
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}
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2020-05-29 06:03:22 +00:00
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#endif
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2019-06-25 06:31:44 +00:00
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static u32 fu540_read_serialnum(void)
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{
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2020-05-29 06:03:22 +00:00
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u32 serial = ERROR_READING_SERIAL_NUMBER;
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#if CONFIG_IS_ENABLED(SIFIVE_OTP)
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struct udevice *dev;
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2019-06-25 06:31:44 +00:00
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int ret;
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2020-05-29 06:03:22 +00:00
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/* init OTP */
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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2020-12-29 03:34:56 +00:00
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DM_DRIVER_GET(sifive_otp), &dev);
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2020-05-29 06:03:22 +00:00
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if (ret) {
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debug("%s: could not find otp device\n", __func__);
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return serial;
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2019-06-25 06:31:44 +00:00
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}
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2020-05-29 06:03:22 +00:00
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/* read serial from OTP and set env var */
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serial = otp_read_serialnum(dev);
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#endif
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return serial;
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2019-06-25 06:31:44 +00:00
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}
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static void fu540_setup_macaddr(u32 serialnum)
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{
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/* Default MAC address */
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unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
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/*
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* We derive our board MAC address by ORing last three bytes
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* of board serial number to above default MAC address.
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*
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* This logic of deriving board MAC address is taken from
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* SiFive FSBL and is kept unchanged.
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*/
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mac[5] |= (serialnum >> 0) & 0xff;
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mac[4] |= (serialnum >> 8) & 0xff;
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mac[3] |= (serialnum >> 16) & 0xff;
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/* Update environment variable */
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eth_env_set_enetaddr("ethaddr", mac);
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}
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int misc_init_r(void)
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{
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2019-08-12 14:57:40 +00:00
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u32 serial_num;
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char buf[9] = {0};
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/* Set ethaddr environment variable from board serial number */
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if (!env_get("serial#")) {
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serial_num = fu540_read_serialnum();
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if (!serial_num) {
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WARN(true, "Board serial number should not be 0 !!\n");
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return 0;
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}
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snprintf(buf, sizeof(buf), "%08x", serial_num);
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env_set("serial#", buf);
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fu540_setup_macaddr(serial_num);
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}
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2019-06-25 06:31:44 +00:00
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return 0;
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}
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#endif
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2019-02-25 08:15:19 +00:00
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2021-10-26 06:12:33 +00:00
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void *board_fdt_blob_setup(int *err)
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2021-07-27 09:06:59 +00:00
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{
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2021-10-26 06:12:33 +00:00
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*err = 0;
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2021-07-27 09:06:59 +00:00
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if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
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if (gd->arch.firmware_fdt_addr)
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2021-09-12 03:15:16 +00:00
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return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
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2021-07-27 09:06:59 +00:00
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}
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2021-09-11 14:31:23 +00:00
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return (ulong *)&_end;
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2021-07-27 09:06:59 +00:00
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}
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2019-02-25 08:15:19 +00:00
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int board_init(void)
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{
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2020-05-29 06:44:51 +00:00
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/* enable all cache ways */
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2021-09-01 07:01:42 +00:00
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enable_caches();
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2019-02-25 08:15:19 +00:00
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return 0;
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}
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