2019-12-07 04:42:53 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Intel Corp.
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* Copyright 2019 Google LLC
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*
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* Taken partly from coreboot gpio.c
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*
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* Pinctrl is modelled as a separate device-tree node and device for each
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* 'community' (basically a set of GPIOs). The separate devices work together
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* and many functions permit any PINCTRL device to be provided as a parameter,
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* since the pad numbering is unique across all devices.
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*
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* Each pinctrl has a single child GPIO device to handle GPIO access and
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* therefore there is a simple GPIO driver included in this file.
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*/
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#define LOG_CATEGORY UCLASS_GPIO
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#include <common.h>
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#include <dm.h>
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#include <irq.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2019-12-07 04:42:53 +00:00
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#include <p2sb.h>
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#include <spl.h>
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#include <asm-generic/gpio.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/arch/gpio.h>
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2020-01-22 15:01:45 +00:00
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#include <asm/itss.h>
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2019-12-07 04:42:53 +00:00
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/gpio.h>
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2020-02-03 14:36:15 +00:00
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#include <linux/err.h>
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2019-12-07 04:42:53 +00:00
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#define GPIO_DW_SIZE(x) (sizeof(u32) * (x))
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#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num))
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#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0)
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#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1)
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#define MISCCFG_GPE0_DW0_SHIFT 8
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#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
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#define MISCCFG_GPE0_DW1_SHIFT 12
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#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
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#define MISCCFG_GPE0_DW2_SHIFT 16
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#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
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#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \
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((group) * sizeof(u32)))
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#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
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((group) * sizeof(u32)))
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#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
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((group) * sizeof(uint32_t)))
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#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
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((group) * sizeof(uint32_t)))
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/**
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* relative_pad_in_comm() - Get the relative position of a GPIO
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*
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* This finds the position of a GPIO within a community
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*
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* @comm: Community to search
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* @gpio: Pad number to look up (assumed to be valid)
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* @return offset, 0 for first GPIO in community
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*/
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static size_t relative_pad_in_comm(const struct pad_community *comm,
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uint gpio)
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{
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return gpio - comm->first_pad;
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}
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/**
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* pinctrl_group_index() - Find group for a a pad
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*
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* Find the group within the community that the pad is a part of
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*
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* @comm: Community to search
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* @relative_pad: Pad to look up
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* @return group number if found (see community_n_groups, etc.), or
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* -ESPIPE if no groups, or -ENOENT if not found
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*/
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static int pinctrl_group_index(const struct pad_community *comm,
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uint relative_pad)
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{
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int i;
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if (!comm->groups)
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return -ESPIPE;
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/* find the base pad number for this pad's group */
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for (i = 0; i < comm->num_groups; i++) {
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if (relative_pad >= comm->groups[i].first_pad &&
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relative_pad < comm->groups[i].first_pad +
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comm->groups[i].size)
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return i;
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}
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return -ENOENT;
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}
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static int pinctrl_group_index_scaled(const struct pad_community *comm,
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uint relative_pad, size_t scale)
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{
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int ret;
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ret = pinctrl_group_index(comm, relative_pad);
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if (ret < 0)
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return ret;
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return ret * scale;
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}
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static int pinctrl_within_group(const struct pad_community *comm,
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uint relative_pad)
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{
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int ret;
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ret = pinctrl_group_index(comm, relative_pad);
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if (ret < 0)
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return ret;
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return relative_pad - comm->groups[ret].first_pad;
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}
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static u32 pinctrl_bitmask_within_group(const struct pad_community *comm,
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uint relative_pad)
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{
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return 1U << pinctrl_within_group(comm, relative_pad);
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}
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/**
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* pinctrl_get_device() - Find the device for a particular pad
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*
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* Each pinctr, device is attached to one community and this supports a number
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* of pads. This function finds the device which controls a particular pad.
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*
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* @pad: Pad to check
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* @devp: Returns the device for that pad
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* @return 0 if OK, -ENOTBLK if no device was found for the given pin
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*/
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static int pinctrl_get_device(uint pad, struct udevice **devp)
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{
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struct udevice *dev;
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/*
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* We have to probe each one of these since the community link is only
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* attached in intel_pinctrl_ofdata_to_platdata().
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*/
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uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
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struct intel_pinctrl_priv *priv = dev_get_priv(dev);
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const struct pad_community *comm = priv->comm;
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if (pad >= comm->first_pad && pad <= comm->last_pad) {
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*devp = dev;
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return 0;
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}
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}
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printf("pad %d not found\n", pad);
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return -ENOTBLK;
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}
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int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp)
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{
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const struct pad_community *comm;
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struct intel_pinctrl_priv *priv;
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struct udevice *dev;
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int ret;
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ret = pinctrl_get_device(pad, &dev);
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if (ret)
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return log_msg_ret("pad", ret);
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priv = dev_get_priv(dev);
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comm = priv->comm;
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*devp = dev;
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*offsetp = relative_pad_in_comm(comm, pad);
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return 0;
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}
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static int pinctrl_configure_owner(struct udevice *dev,
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const struct pad_config *cfg,
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const struct pad_community *comm)
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{
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u32 hostsw_own;
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u16 hostsw_own_offset;
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int pin;
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int ret;
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pin = relative_pad_in_comm(comm, cfg->pad);
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/*
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* Based on the gpio pin number configure the corresponding bit in
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* HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
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*/
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hostsw_own_offset = comm->host_own_reg_0;
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ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32));
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if (ret < 0)
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return ret;
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hostsw_own_offset += ret;
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hostsw_own = pcr_read32(dev, hostsw_own_offset);
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/*
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*The 4th bit in pad_config 1 (RO) is used to indicate if the pad
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* needs GPIO driver ownership. Set the bit if GPIO driver ownership
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* requested, otherwise clear the bit.
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*/
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if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
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hostsw_own |= pinctrl_bitmask_within_group(comm, pin);
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else
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hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin);
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pcr_write32(dev, hostsw_own_offset, hostsw_own);
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return 0;
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}
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static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg,
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const struct pad_community *comm)
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{
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u32 value;
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u16 sts_reg;
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u16 en_reg;
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int group;
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int pin;
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int ret;
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if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
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return 0;
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pin = relative_pad_in_comm(comm, cfg->pad);
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ret = pinctrl_group_index(comm, pin);
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if (ret < 0)
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return ret;
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group = ret;
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sts_reg = GPI_SMI_STS_OFFSET(comm, group);
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value = pcr_read32(dev, sts_reg);
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/* Write back 1 to reset the sts bits */
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pcr_write32(dev, sts_reg, value);
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/* Set enable bits */
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en_reg = GPI_SMI_EN_OFFSET(comm, group);
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pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin));
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return 0;
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}
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static int pinctrl_configure_itss(struct udevice *dev,
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const struct pad_config *cfg,
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uint pad_cfg_offset)
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{
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struct intel_pinctrl_priv *priv = dev_get_priv(dev);
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if (!priv->itss_pol_cfg)
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return -ENOSYS;
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int irq;
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/*
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* Set up ITSS polarity if pad is routed to APIC.
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*
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* The ITSS takes only active high interrupt signals. Therefore,
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* if the pad configuration indicates an inversion assume the
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* intent is for the ITSS polarity. Before forwarding on the
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* request to the APIC there's an inversion setting for how the
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* signal is forwarded to the APIC. Honor the inversion setting
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* in the GPIO pad configuration so that a hardware active low
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* signal looks that way to the APIC (double inversion).
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*/
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if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
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return 0;
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irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
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irq &= PAD_CFG1_IRQ_MASK;
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if (!irq) {
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log_err("GPIO %u doesn't support APIC routing\n", cfg->pad);
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return -EPROTONOSUPPORT;
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}
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irq_set_polarity(priv->itss, irq,
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cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT);
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return 0;
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}
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/* Number of DWx config registers can be different for different SOCs */
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static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad)
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{
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const struct pad_community *comm = priv->comm;
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size_t offset;
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offset = relative_pad_in_comm(comm, pad);
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offset *= GPIO_DW_SIZE(priv->num_cfgs);
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return offset + comm->pad_cfg_base;
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}
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static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
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u32 config_value)
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{
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const struct reset_mapping *rst_map = comm->reset_map;
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int i;
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/* Logical reset values equal chipset values */
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if (!rst_map || !comm->num_reset_vals)
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return config_value;
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for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
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if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
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config_value &= ~PAD_CFG0_RESET_MASK;
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config_value |= rst_map->chipset;
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return config_value;
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}
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}
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log_err("Logical-to-Chipset mapping not found\n");
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return -ENOENT;
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}
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static const int mask[4] = {
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PAD_CFG0_TX_STATE |
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PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |
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PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK |
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PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL |
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PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK |
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PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK,
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#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY
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PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK,
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#else
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PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK,
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#endif
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PAD_CFG2_DEBOUNCE_MASK,
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0,
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};
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/**
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* pinctrl_configure_pad() - Configure a pad
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*
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* @dev: Pinctrl device containing the pad (see pinctrl_get_device())
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* @cfg: Configuration to apply
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* @return 0 if OK, -ve on error
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*/
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static int pinctrl_configure_pad(struct udevice *dev,
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const struct pad_config *cfg)
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{
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struct intel_pinctrl_priv *priv = dev_get_priv(dev);
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const struct pad_community *comm = priv->comm;
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uint config_offset;
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u32 pad_conf, soc_pad_conf;
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int ret;
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int i;
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if (IS_ERR(comm))
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return PTR_ERR(comm);
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config_offset = pad_config_offset(priv, cfg->pad);
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for (i = 0; i < priv->num_cfgs; i++) {
|
|
|
|
pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i));
|
|
|
|
|
|
|
|
soc_pad_conf = cfg->pad_config[i];
|
|
|
|
if (i == 0) {
|
|
|
|
ret = pinctrl_pad_reset_config_override(comm,
|
|
|
|
soc_pad_conf);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
soc_pad_conf = ret;
|
|
|
|
}
|
|
|
|
soc_pad_conf &= mask[i];
|
|
|
|
soc_pad_conf |= pad_conf & ~mask[i];
|
|
|
|
|
|
|
|
log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n",
|
|
|
|
comm->port, relative_pad_in_comm(comm, cfg->pad), i,
|
|
|
|
pad_conf,/* old value */
|
|
|
|
/* value passed from pinctrl table */
|
|
|
|
cfg->pad_config[i],
|
|
|
|
soc_pad_conf); /*new value*/
|
|
|
|
pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i),
|
|
|
|
soc_pad_conf);
|
|
|
|
}
|
|
|
|
ret = pinctrl_configure_itss(dev, cfg, config_offset);
|
|
|
|
if (ret && ret != -ENOSYS)
|
|
|
|
return log_msg_ret("itss config failed", ret);
|
|
|
|
ret = pinctrl_configure_owner(dev, cfg, comm);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
ret = gpi_enable_smi(dev, cfg, comm);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
const struct pad_community *comm = priv->comm;
|
|
|
|
uint config_offset;
|
|
|
|
|
|
|
|
assert(device_get_uclass_id(dev) == UCLASS_PINCTRL);
|
|
|
|
config_offset = comm->pad_cfg_base + offset *
|
|
|
|
GPIO_DW_SIZE(priv->num_cfgs);
|
|
|
|
|
|
|
|
return config_offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
|
|
|
|
{
|
|
|
|
uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset);
|
|
|
|
|
|
|
|
return pcr_read32(dev, config_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
const struct pad_community *comm = priv->comm;
|
|
|
|
int group;
|
|
|
|
|
|
|
|
group = pinctrl_group_index(comm, offset);
|
|
|
|
|
|
|
|
/* If pad base is not set then use GPIO number as ACPI pin number */
|
|
|
|
if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE)
|
|
|
|
return comm->first_pad + offset;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If this group has a non-zero pad base then compute the ACPI pin
|
|
|
|
* number from the pad base and the relative pad in the group.
|
|
|
|
*/
|
|
|
|
return comm->groups[group].acpi_pad_base +
|
|
|
|
pinctrl_within_group(comm, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d)
|
|
|
|
{
|
|
|
|
struct udevice *pinctrl_dev;
|
|
|
|
u32 misccfg_value;
|
|
|
|
u32 misccfg_clr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the group here for community specific MISCCFG register.
|
|
|
|
* If any of these returns -1 then there is some error in devicetree
|
|
|
|
* where the group is probably hardcoded and does not comply with the
|
|
|
|
* PMC group defines. So we return from here and MISCFG is set to
|
|
|
|
* default.
|
|
|
|
*/
|
|
|
|
ret = irq_route_pmc_gpio_gpe(itss, gpe0b);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
gpe0b = ret;
|
|
|
|
|
|
|
|
ret = irq_route_pmc_gpio_gpe(itss, gpe0c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
gpe0c = ret;
|
|
|
|
|
|
|
|
ret = irq_route_pmc_gpio_gpe(itss, gpe0d);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
gpe0d = ret;
|
|
|
|
|
|
|
|
misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
|
|
|
|
misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
|
|
|
|
misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT;
|
|
|
|
|
|
|
|
/* Program GPIO_MISCCFG */
|
|
|
|
misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK |
|
|
|
|
MISCCFG_GPE0_DW0_MASK;
|
|
|
|
|
|
|
|
log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr,
|
|
|
|
misccfg_value);
|
|
|
|
uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) {
|
|
|
|
pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr,
|
|
|
|
misccfg_value);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_gpi_clear_int_cfg(void)
|
|
|
|
{
|
|
|
|
struct udevice *dev;
|
|
|
|
struct uclass *uc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = uclass_get(UCLASS_PINCTRL, &uc);
|
|
|
|
if (ret)
|
|
|
|
return log_msg_ret("pinctrl uc", ret);
|
|
|
|
uclass_foreach_dev(dev, uc) {
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
const struct pad_community *comm = priv->comm;
|
|
|
|
uint sts_value;
|
|
|
|
int group;
|
|
|
|
|
|
|
|
for (group = 0; group < comm->num_gpi_regs; group++) {
|
|
|
|
/* Clear the enable register */
|
|
|
|
pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0);
|
|
|
|
|
|
|
|
/* Read and clear the set status register bits*/
|
|
|
|
sts_value = pcr_read32(dev,
|
|
|
|
GPI_IS_OFFSET(comm, group));
|
|
|
|
pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
const u32 *ptr;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
log_debug("%s: pads_count=%d\n", __func__, pads_count);
|
|
|
|
for (ptr = pads, i = 0; i < pads_count;
|
|
|
|
ptr += 1 + priv->num_cfgs, i++) {
|
|
|
|
struct udevice *pad_dev = NULL;
|
|
|
|
struct pad_config *cfg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
cfg = (struct pad_config *)ptr;
|
|
|
|
ret = pinctrl_get_device(cfg->pad, &pad_dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
ret = pinctrl_configure_pad(pad_dev, cfg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
|
|
|
|
u32 **padsp, int *pad_countp)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
u32 *pads;
|
|
|
|
int size;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*padsp = NULL;
|
|
|
|
*pad_countp = 0;
|
|
|
|
size = ofnode_read_size(node, prop);
|
|
|
|
if (size < 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pads = malloc(size);
|
|
|
|
if (!pads)
|
|
|
|
return -ENOMEM;
|
|
|
|
size /= sizeof(fdt32_t);
|
|
|
|
ret = ofnode_read_u32_array(node, prop, pads, size);
|
|
|
|
if (ret) {
|
|
|
|
free(pads);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
*pad_countp = size / (1 + priv->num_cfgs);
|
|
|
|
*padsp = pads;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
int count = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < size;) {
|
|
|
|
u32 val;
|
|
|
|
int j;
|
|
|
|
|
|
|
|
for (val = j = 0; j < priv->num_cfgs + 1; j++)
|
|
|
|
val |= pads[i + j];
|
|
|
|
if (!val)
|
|
|
|
break;
|
|
|
|
count++;
|
|
|
|
i += priv->num_cfgs + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node)
|
|
|
|
{
|
|
|
|
int pads_count;
|
|
|
|
u32 *pads;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (device_get_uclass_id(dev) != UCLASS_PINCTRL)
|
|
|
|
return log_msg_ret("uclass", -EPROTONOSUPPORT);
|
|
|
|
ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count);
|
|
|
|
if (ret)
|
|
|
|
return log_msg_ret("no pads", ret);
|
|
|
|
ret = pinctrl_config_pads(dev, pads, pads_count);
|
|
|
|
free(pads);
|
|
|
|
if (ret)
|
|
|
|
return log_msg_ret("pad config", ret);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
|
|
|
|
const struct pad_community *comm,
|
|
|
|
int num_cfgs)
|
|
|
|
{
|
|
|
|
struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!comm) {
|
|
|
|
log_err("Cannot find community for pid %d\n", pplat->pid);
|
|
|
|
return -EDOM;
|
|
|
|
}
|
2020-02-06 16:54:58 +00:00
|
|
|
ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
|
2019-12-07 04:42:53 +00:00
|
|
|
if (ret)
|
|
|
|
return log_msg_ret("Cannot find ITSS", ret);
|
|
|
|
priv->comm = comm;
|
|
|
|
priv->num_cfgs = num_cfgs;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_pinctrl_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
priv->itss_pol_cfg = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct pinctrl_ops intel_pinctrl_ops = {
|
|
|
|
/* No operations are supported, but DM expects this to be present */
|
|
|
|
};
|