u-boot/arch/arm/cpu/armv8/fsl-lsch3/Makefile

#
# Copyright 2014, Freescale Semiconductor
#
# SPDX-License-Identifier:	GPL-2.0+
#

obj-y += cpu.o
obj-y += lowlevel.o
obj-y += speed.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> 2014-06-23 22:15:54 +00:00			`#`
			`# Copyright 2014, Freescale Semiconductor`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`obj-y += cpu.o`
			`obj-y += lowlevel.o`
			`obj-y += speed.o`
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> 2014-09-08 19:20:00 +00:00			`obj-$(CONFIG_MP) += mp.o`
			`obj-$(CONFIG_OF_LIBFDT) += fdt.o`