2021-07-21 15:58:48 +00:00
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.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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.. sectionauthor:: Lokesh Vutla <lokeshvutla@ti.com>
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2022-12-19 20:29:49 +00:00
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J721E Platforms
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===============
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2021-07-21 15:58:48 +00:00
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Introduction:
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-------------
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The J721e family of SoCs are part of K3 Multicore SoC architecture platform
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targeting automotive applications. They are designed as a low power, high
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performance and highly integrated device architecture, adding significant
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enhancement on processing power, graphics capability, video and imaging
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processing, virtualization and coherent memory support.
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The device is partitioned into three functional domains, each containing
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specific processing cores and peripherals:
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1. Wake-up (WKUP) domain:
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* Device Management and Security Controller (DMSC)
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2. Microcontroller (MCU) domain:
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* Dual Core ARM Cortex-R5F processor
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3. MAIN domain:
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* Dual core 64-bit ARM Cortex-A72
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* 2 x Dual cortex ARM Cortex-R5 subsystem
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* 2 x C66x Digital signal processor sub system
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* C71x Digital signal processor sub-system with MMA.
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More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
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Boot Flow:
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----------
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Boot flow is similar to that of AM65x SoC and extending it with remoteproc
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support. Below is the pictorial representation of boot flow:
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.. code-block:: text
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+------------------------------------------------------------------------+-----------------------+
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| DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x |
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+------------------------------------------------------------------------+-----------------------+
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| +--------+ | | | |
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| | Reset | | | | |
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| +--------+ | | | |
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| : | | | |
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| +--------+ | +-----------+ | | |
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| | *ROM* |----------|-->| Reset rls | | | |
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| +--------+ | +-----------+ | | |
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| | | | : | | |
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| | ROM | | : | | |
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| |services| | : | | |
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| | | | +-------------+ | | |
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| | | | | *R5 ROM* | | | |
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| | | | +-------------+ | | |
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| | |<---------|---|Load and auth| | | |
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| | | | | tiboot3.bin | | | |
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| | | | +-------------+ | | |
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| | | | +-------------+ | | |
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| | | | | *R5 SPL* | | | |
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| | | | +-------------+ | | |
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| | | | | Load | | | |
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| | | | | sysfw.itb | | | |
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| | Start | | +-------------+ | | |
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| | System |<---------|---| Start | | | |
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| |Firmware| | | SYSFW | | | |
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| +--------+ | +-------------+ | | |
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| : | | | | | |
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| +---------+ | | Load | | | |
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| | *SYSFW* | | | system | | | |
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| +---------+ | | Config data | | | |
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| | |<--------|---| | | | |
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| | | | +-------------+ | | |
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| | | | | DDR | | | |
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| | | | | config | | | |
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| | | | +-------------+ | | |
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| | | | | Load | | | |
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| | | | | tispl.bin | | | |
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| | | | +-------------+ | | |
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| | | | | Load R5 | | | |
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| | | | | firmware | | | |
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| | | | +-------------+ | | |
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| | |<--------|---| Start A72 | | | |
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| | | | | and jump to | | | |
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| | | | | DM fw image | | | |
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| | | | +-------------+ | | |
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| | | | | +-----------+ | |
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| | |---------|-----------------------|---->| Reset rls | | |
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| | | | | +-----------+ | |
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| | TIFS | | | : | |
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| |Services | | | +-------------+ | |
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| | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | |
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| | | | | +-------------+ | |
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2021-07-21 15:58:48 +00:00
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| | | | | : | |
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| | | | | +-----------+ | |
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| | |<--------|-----------------------|---->| *A72 SPL* | | |
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| | | | | +-----------+ | |
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| | | | | | Load | | |
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| | | | | | u-boot.img| | |
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| | | | | +-----------+ | |
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| | | | | +-----------+ | |
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| | |<--------|-----------------------|---->| *U-Boot* | | |
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| | | | | +-----------+ | |
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| | | | | | prompt | | |
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| | | | | +-----------+ | |
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| | | | | | Load R5 | | |
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| | | | | | Firmware | | |
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| | | | | +-----------+ | |
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| | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
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| | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
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| | | | | | Load C6 | | +-----------+ |
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| | | | | | Firmware | | |
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| | |<--------|-----------------------|-----| Start C6 | | +-----------+ |
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| | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | |
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| | | | | | Load C7 | | +-----------+ |
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| | | | | | Firmware | | |
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| | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
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| | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
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| +---------+ | | | +-----------+ |
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+------------------------------------------------------------------------+-----------------------+
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- Here DMSC acts as master and provides all the critical services. R5/A72
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requests DMSC to get these services done as shown in the above diagram.
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Sources:
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--------
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2023-07-21 18:44:43 +00:00
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1. Trusted Firmware-A:
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Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
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Branch: master
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2023-07-21 18:44:43 +00:00
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2. OP-TEE:
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Tree: https://github.com/OP-TEE/optee_os.git
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Branch: master
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2023-07-21 18:44:43 +00:00
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3. U-Boot:
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Tree: https://source.denx.de/u-boot/u-boot
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Branch: master
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2023-07-21 18:44:43 +00:00
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4. TI Linux Firmware:
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2022-11-09 17:30:00 +00:00
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Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
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Branch: ti-linux-firmware
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2021-07-21 15:58:48 +00:00
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Build procedure:
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----------------
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2023-07-21 18:44:43 +00:00
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1. Trusted Firmware-A:
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2021-07-21 15:58:48 +00:00
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2022-11-09 17:30:01 +00:00
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.. code-block:: bash
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2021-07-21 15:58:48 +00:00
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2023-07-21 18:44:43 +00:00
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$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 \
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TARGET_BOARD=generic SPD=opteed
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2021-07-21 15:58:48 +00:00
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2023-07-21 18:44:43 +00:00
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2. OP-TEE:
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2021-07-21 15:58:48 +00:00
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2022-11-09 17:30:01 +00:00
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.. code-block:: bash
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2021-07-21 15:58:48 +00:00
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2023-07-21 18:44:43 +00:00
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$ make PLATFORM=k3-j721e CFG_ARM64_core=y
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2023-07-21 18:44:43 +00:00
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3. U-Boot:
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2021-07-21 15:58:48 +00:00
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* 4.1 R5:
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2022-11-09 17:30:01 +00:00
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.. code-block:: bash
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2023-07-21 18:44:43 +00:00
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$ make j721e_evm_r5_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- \
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BINMAN_INDIRS=<path/to/ti-linux-firmware>
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* 4.2 A72:
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2022-11-09 17:30:01 +00:00
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.. code-block:: bash
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2023-07-21 18:44:43 +00:00
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$ make j721e_evm_a72_defconfig
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$ make CROSS_COMPILE=aarch64-linux-gnu- \
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BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \
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TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \
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BINMAN_INDIRS=<path/to/ti-linux-firmware>
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Target Images
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--------------
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2023-07-25 16:44:16 +00:00
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In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
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Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these
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files.
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2023-07-21 18:44:43 +00:00
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- GP
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* tiboot3-j721e-gp-evm.bin, sysfw-j721e-gp-evm.itb from step 4.1
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* tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
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- HS-FS
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* tiboot3-j721e_sr2-hs-fs-evm.bin, sysfw-j721e_sr2-hs-fs-evm.itb from step 4.1
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* tispl.bin, u-boot.img from step 4.2
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- HS-SE
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* tiboot3-j721e_sr2-hs-evm.bin, sysfw-j721e_sr2-hs-evm.itb from step 4.1
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* tispl.bin, u-boot.img from step 4.2
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Image formats:
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--------------
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- tiboot3.bin:
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.. code-block:: text
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+-----------------------+
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| X.509 |
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| Certificate |
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| +-------------------+ |
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| | R5 | |
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| | u-boot-spl.bin | |
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| +-------------------+ |
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| | FIT header | |
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| | +---------------+ | |
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| | | DTB 1...N | | |
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| | +---------------+ | |
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| +-------------------+ |
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+-----------------------+
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- tispl.bin
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.. code-block:: text
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+-----------------------+
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| FIT HEADER |
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| +-------------------+ |
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| | A72 TF-A | |
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| +-------------------+ |
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| | A72 OP-TEE | |
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| +-------------------+ |
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| | R5 DM FW | |
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| +-------------------+ |
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| | A72 SPL | |
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| +-------------------+ |
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| | SPL DTB 1...N | |
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| +-------------------+ |
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+-----------------------+
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- sysfw.itb
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.. code-block:: text
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+-----------------------+
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| FIT HEADER |
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| +-------------------+ |
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| | sysfw.bin | |
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| +-------------------+ |
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| | board config | |
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| +-------------------+ |
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| | PM config | |
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| +-------------------+ |
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| | RM config | |
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| +-------------------+ |
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| | Secure config | |
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| +-------------------+ |
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+-----------------------+
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2023-05-16 04:54:36 +00:00
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R5 Memory Map:
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--------------
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.. list-table::
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:widths: 16 16 16
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:header-rows: 1
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* - Region
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- Start Address
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- End Address
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* - SPL
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- 0x41c00000
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- 0x41c40000
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* - EMPTY
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- 0x41c40000
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- 0x41c81920
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* - STACK
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- 0x41c85920
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- 0x41c81920
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* - Global data
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- 0x41c859f0
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- 0x41c85920
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* - Heap
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- 0x41c859f0
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- 0x41cf59f0
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* - BSS
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- 0x41cf59f0
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- 0x41cff9f0
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* - MCU Scratchpad
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- 0x41cff9fc
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- 0x41cffbfc
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* - ROM DATA
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- 0x41cffbfc
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- 0x41cfffff
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2021-07-21 15:58:48 +00:00
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OSPI:
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-----
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ROM supports booting from OSPI from offset 0x0.
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Flashing images to OSPI:
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Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
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and sysfw.itb over tftp and then flash those to OSPI at their respective
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addresses.
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.. code-block:: text
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=> sf probe
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=> tftp ${loadaddr} tiboot3.bin
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=> sf update $loadaddr 0x0 $filesize
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=> tftp ${loadaddr} tispl.bin
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=> sf update $loadaddr 0x80000 $filesize
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=> tftp ${loadaddr} u-boot.img
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=> sf update $loadaddr 0x280000 $filesize
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=> tftp ${loadaddr} sysfw.itb
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=> sf update $loadaddr 0x6C0000 $filesize
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Flash layout for OSPI:
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.. code-block:: text
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0x0 +----------------------------+
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| ospi.tiboot3(512K) |
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| |
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0x80000 +----------------------------+
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| ospi.tispl(2M) |
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| |
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0x280000 +----------------------------+
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| ospi.u-boot(4M) |
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| |
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0x680000 +----------------------------+
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| ospi.env(128K) |
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| |
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|
0x6A0000 +----------------------------+
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| ospi.env.backup (128K) |
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| |
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|
0x6C0000 +----------------------------+
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| ospi.sysfw(1M) |
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|
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| |
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|
0x7C0000 +----------------------------+
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| padding (256k) |
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|
0x800000 +----------------------------+
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| ospi.rootfs(UBIFS) |
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| |
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|
+----------------------------+
|
2021-07-21 15:58:49 +00:00
|
|
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|
|
|
|
|
Firmwares:
|
|
|
|
|
----------
|
|
|
|
|
|
|
|
|
|
The J721e u-boot allows firmware to be loaded for the Cortex-R5 subsystem.
|
|
|
|
|
The CPSW5G in J7200 and CPSW9G in J721E present in MAIN domain is configured
|
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|
|
and controlled by the ethernet firmware that executes in the MAIN Cortex R5.
|
|
|
|
|
The default supported environment variables support loading these firmwares
|
|
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|
|
from only MMC. "dorprocboot" env variable has to be set for the U-BOOT to load
|
|
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|
|
and start the remote cores in the system.
|
|
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|
|
J721E common processor board can be attached to a Ethernet QSGMII card and the
|
|
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|
|
PHY in the card has to be reset before it can be used for data transfer.
|
|
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|
|
"do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to
|
|
|
|
|
configure this PHY.
|
