2018-11-02 14:21:08 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family MCU Domain peripherals
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*
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2021-02-01 05:56:39 +00:00
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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2018-11-02 14:21:08 +00:00
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*/
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&cbass_mcu {
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2021-02-01 05:56:39 +00:00
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mcu_conf: scm-conf@40f00000 {
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2020-07-06 08:06:56 +00:00
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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2023-12-29 17:47:01 +00:00
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/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
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mcu_timerio_input: pinctrl@40f04200 {
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compatible = "pinctrl-single";
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reg = <0x0 0x40f04200 0x0 0x10>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x00000101>;
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};
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/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
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mcu_timerio_output: pinctrl@40f04280 {
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compatible = "pinctrl-single";
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reg = <0x0 0x40f04280 0x0 0x8>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x00000003>;
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};
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2018-11-02 14:21:08 +00:00
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mcu_uart0: serial@40a00000 {
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compatible = "ti,am654-uart";
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2023-12-29 17:47:01 +00:00
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reg = <0x00 0x40a00000 0x00 0x100>;
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interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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2021-02-01 05:56:39 +00:00
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x80000>;
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ranges = <0x0 0x00 0x41c00000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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2018-11-02 14:21:08 +00:00
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};
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2019-06-04 23:08:14 +00:00
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 114 1>;
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2019-06-07 13:54:47 +00:00
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2019-06-04 23:08:14 +00:00
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};
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2019-09-04 10:31:41 +00:00
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2021-02-01 05:56:39 +00:00
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mcu_spi0: spi@40300000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40300000 0x0 0x400>;
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interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 142 1>;
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power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
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2019-09-04 10:31:41 +00:00
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#address-cells = <1>;
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2021-02-01 05:56:39 +00:00
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#size-cells = <0>;
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2021-02-01 05:56:39 +00:00
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};
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2019-09-04 10:31:41 +00:00
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2021-02-01 05:56:39 +00:00
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mcu_spi1: spi@40310000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40310000 0x0 0x400>;
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interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 143 1>;
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power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2021-02-01 05:56:39 +00:00
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};
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2019-09-04 10:31:41 +00:00
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2021-02-01 05:56:39 +00:00
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mcu_spi2: spi@40320000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40320000 0x0 0x400>;
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interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 144 1>;
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power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2019-09-04 10:31:41 +00:00
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};
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2020-02-04 05:39:51 +00:00
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2021-02-01 05:56:39 +00:00
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tscadc0: tscadc@40200000 {
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compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
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reg = <0x0 0x40200000 0x0 0x1000>;
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interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 0 2>;
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assigned-clocks = <&k3_clks 0 2>;
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assigned-clock-rates = <60000000>;
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2023-12-29 17:47:01 +00:00
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clock-names = "fck";
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2021-02-01 05:56:39 +00:00
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dmas = <&mcu_udmap 0x7100>,
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<&mcu_udmap 0x7101 >;
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dma-names = "fifo0", "fifo1";
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2020-02-04 05:39:51 +00:00
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2021-02-01 05:56:39 +00:00
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adc {
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#io-channel-cells = <1>;
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compatible = "ti,am654-adc", "ti,am3359-adc";
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2020-02-04 05:39:51 +00:00
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};
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2021-02-01 05:56:39 +00:00
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};
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2020-02-04 05:39:51 +00:00
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2021-02-01 05:56:39 +00:00
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tscadc1: tscadc@40210000 {
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compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
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reg = <0x0 0x40210000 0x0 0x1000>;
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 1 2>;
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assigned-clocks = <&k3_clks 1 2>;
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assigned-clock-rates = <60000000>;
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2023-12-29 17:47:01 +00:00
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clock-names = "fck";
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2021-02-01 05:56:39 +00:00
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dmas = <&mcu_udmap 0x7102>,
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<&mcu_udmap 0x7103>;
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dma-names = "fifo0", "fifo1";
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2023-12-29 17:47:01 +00:00
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status = "disabled";
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2021-02-01 05:56:39 +00:00
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adc {
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#io-channel-cells = <1>;
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compatible = "ti,am654-adc", "ti,am3359-adc";
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2020-02-04 05:39:51 +00:00
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};
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};
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2020-07-07 08:13:35 +00:00
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2023-12-29 17:47:01 +00:00
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/*
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* The MCU domain timer interrupts are routed only to the ESM module,
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* and not currently available for Linux. The MCU domain timers are
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* of limited use without interrupts, and likely reserved by the ESM.
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*/
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mcu_timer0: timer@40400000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40400000 0x00 0x400>;
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clocks = <&k3_clks 35 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer1: timer@40410000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40410000 0x00 0x400>;
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clocks = <&k3_clks 36 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer2: timer@40420000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40420000 0x00 0x400>;
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clocks = <&k3_clks 37 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer3: timer@40430000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40430000 0x00 0x400>;
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clocks = <&k3_clks 38 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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2021-09-10 21:37:43 +00:00
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mcu_navss: bus@28380000 {
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2023-12-29 17:47:01 +00:00
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compatible = "simple-bus";
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2020-07-07 08:13:35 +00:00
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#address-cells = <2>;
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#size-cells = <2>;
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2021-09-10 21:37:43 +00:00
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
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2020-07-07 08:13:35 +00:00
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <119>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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2023-12-29 17:47:01 +00:00
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg",
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"proxy_target", "cfg";
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2020-07-07 08:13:35 +00:00
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ti,num-rings = <286>;
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2020-08-17 05:30:49 +00:00
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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2020-07-07 08:13:35 +00:00
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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2021-02-01 05:56:39 +00:00
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msi-parent = <&inta_main_udmass>;
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2020-07-07 08:13:35 +00:00
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,am654-navss-mcu-udmap";
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2023-12-29 17:47:01 +00:00
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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2020-07-07 08:13:35 +00:00
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reg-names = "gcfg", "rchanrt", "tchanrt";
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2021-02-01 05:56:39 +00:00
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msi-parent = <&inta_main_udmass>;
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2020-07-07 08:13:35 +00:00
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <194>;
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ti,ringacc = <&mcu_ringacc>;
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2020-08-17 05:30:49 +00:00
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ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
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<0xd>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
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<0xa>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
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2020-07-07 08:13:35 +00:00
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};
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};
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2020-07-06 08:06:56 +00:00
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2023-12-29 17:47:01 +00:00
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secure_proxy_mcu: mailbox@2a480000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x0 0x2a480000 0x0 0x80000>,
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<0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>;
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/*
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* Marked Disabled:
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* Node is incomplete as it is meant for bootloaders and
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* firmware on non-MPU processors
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*/
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status = "disabled";
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};
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m_can0: can@40528000 {
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compatible = "bosch,m_can";
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reg = <0x0 0x40528000 0x0 0x400>,
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<0x0 0x40500000 0x0 0x4400>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
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clock-names = "hclk", "cclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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m_can1: can@40568000 {
|
|
|
|
|
compatible = "bosch,m_can";
|
|
|
|
|
reg = <0x0 0x40568000 0x0 0x400>,
|
|
|
|
|
<0x0 0x40540000 0x0 0x4400>;
|
|
|
|
|
reg-names = "m_can", "message_ram";
|
|
|
|
|
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
|
|
|
|
|
clock-names = "hclk", "cclk";
|
|
|
|
|
interrupt-parent = <&gic500>;
|
|
|
|
|
interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "int0", "int1";
|
|
|
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fss: bus@47000000 {
|
2021-02-01 05:56:39 +00:00
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
ospi0: spi@47040000 {
|
|
|
|
|
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
|
|
|
|
reg = <0x0 0x47040000 0x0 0x100>,
|
|
|
|
|
<0x5 0x00000000 0x1 0x0000000>;
|
|
|
|
|
interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
cdns,fifo-depth = <256>;
|
|
|
|
|
cdns,fifo-width = <4>;
|
|
|
|
|
cdns,trigger-address = <0x0>;
|
|
|
|
|
clocks = <&k3_clks 248 0>;
|
|
|
|
|
assigned-clocks = <&k3_clks 248 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 248 2>;
|
|
|
|
|
assigned-clock-rates = <166666666>;
|
|
|
|
|
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2023-12-29 17:47:01 +00:00
|
|
|
status = "disabled";
|
2021-02-01 05:56:39 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ospi1: spi@47050000 {
|
|
|
|
|
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
|
|
|
|
reg = <0x0 0x47050000 0x0 0x100>,
|
|
|
|
|
<0x7 0x00000000 0x1 0x00000000>;
|
|
|
|
|
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
cdns,fifo-depth = <256>;
|
|
|
|
|
cdns,fifo-width = <4>;
|
|
|
|
|
cdns,trigger-address = <0x0>;
|
|
|
|
|
clocks = <&k3_clks 249 6>;
|
|
|
|
|
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2023-12-29 17:47:01 +00:00
|
|
|
status = "disabled";
|
2021-02-01 05:56:39 +00:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-06 08:06:56 +00:00
|
|
|
mcu_cpsw: ethernet@46000000 {
|
|
|
|
|
compatible = "ti,am654-cpsw-nuss";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
reg-names = "cpsw_nuss";
|
|
|
|
|
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
clocks = <&k3_clks 5 10>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
dmas = <&mcu_udmap 0xf000>,
|
|
|
|
|
<&mcu_udmap 0xf001>,
|
|
|
|
|
<&mcu_udmap 0xf002>,
|
|
|
|
|
<&mcu_udmap 0xf003>,
|
|
|
|
|
<&mcu_udmap 0xf004>,
|
|
|
|
|
<&mcu_udmap 0xf005>,
|
|
|
|
|
<&mcu_udmap 0xf006>,
|
|
|
|
|
<&mcu_udmap 0xf007>,
|
|
|
|
|
<&mcu_udmap 0x7000>;
|
|
|
|
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
|
|
|
|
"tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"rx";
|
|
|
|
|
|
|
|
|
|
ethernet-ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpsw_port1: port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
ti,mac-only;
|
|
|
|
|
label = "port1";
|
|
|
|
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
|
|
|
|
phys = <&phy_gmii_sel 1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
davinci_mdio: mdio@f00 {
|
|
|
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
|
|
|
reg = <0x0 0xf00 0x0 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 5 10>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
bus_freq = <1000000>;
|
2023-12-29 17:47:01 +00:00
|
|
|
status = "disabled";
|
2020-07-06 08:06:56 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpts@3d000 {
|
|
|
|
|
compatible = "ti,am65-cpts";
|
|
|
|
|
reg = <0x0 0x3d000 0x0 0x400>;
|
|
|
|
|
clocks = <&mcu_cpsw_cpts_mux>;
|
|
|
|
|
clock-names = "cpts";
|
|
|
|
|
interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cpts";
|
|
|
|
|
ti,cpts-ext-ts-inputs = <4>;
|
|
|
|
|
ti,cpts-periodic-outputs = <2>;
|
|
|
|
|
|
|
|
|
|
mcu_cpsw_cpts_mux: refclk-mux {
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
|
|
|
|
|
<&k3_clks 118 6>, <&k3_clks 118 3>,
|
|
|
|
|
<&k3_clks 118 8>, <&k3_clks 118 14>,
|
|
|
|
|
<&k3_clks 120 3>, <&k3_clks 121 3>;
|
|
|
|
|
assigned-clocks = <&mcu_cpsw_cpts_mux>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 118 5>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-06-23 11:15:10 +00:00
|
|
|
|
2021-02-01 05:56:39 +00:00
|
|
|
mcu_r5fss0: r5fss@41000000 {
|
|
|
|
|
compatible = "ti,am654-r5fss";
|
|
|
|
|
ti,cluster-mode = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
|
|
|
|
<0x41400000 0x00 0x41400000 0x20000>;
|
|
|
|
|
power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
mcu_r5fss0_core0: r5f@41000000 {
|
|
|
|
|
compatible = "ti,am654-r5f";
|
|
|
|
|
reg = <0x41000000 0x00008000>,
|
|
|
|
|
<0x41010000 0x00008000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <159>;
|
|
|
|
|
ti,sci-proc-ids = <0x01 0xff>;
|
|
|
|
|
resets = <&k3_reset 159 1>;
|
|
|
|
|
firmware-name = "am65x-mcu-r5f0_0-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcu_r5fss0_core1: r5f@41400000 {
|
|
|
|
|
compatible = "ti,am654-r5f";
|
|
|
|
|
reg = <0x41400000 0x00008000>,
|
|
|
|
|
<0x41410000 0x00008000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <245>;
|
|
|
|
|
ti,sci-proc-ids = <0x02 0xff>;
|
|
|
|
|
resets = <&k3_reset 245 1>;
|
|
|
|
|
firmware-name = "am65x-mcu-r5f0_1-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
2020-06-23 11:15:10 +00:00
|
|
|
};
|
2021-09-10 21:37:43 +00:00
|
|
|
|
|
|
|
|
mcu_rti1: watchdog@40610000 {
|
|
|
|
|
compatible = "ti,j7-rti-wdt";
|
|
|
|
|
reg = <0x0 0x40610000 0x0 0x100>;
|
|
|
|
|
clocks = <&k3_clks 135 0>;
|
|
|
|
|
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
|
|
|
|
|
assigned-clocks = <&k3_clks 135 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 135 4>;
|
|
|
|
|
};
|
2018-11-02 14:21:08 +00:00
|
|
|
};
|
