mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
482 lines
14 KiB
Text
482 lines
14 KiB
Text
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0 X11
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*
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*<auto-generated>
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* This code was generated by a tool based on
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* handoffs from both Qsys and Quartus.
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*
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* Changes to this file may be lost if
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* the code is regenerated.
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*</auto-generated>
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*/
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#include "socfpga_arria10.dtsi"
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/ {
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model = "Altera SOCFPGA Arria 10";
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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chosen {
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/* Bootloader setting: uboot.rbf_filename */
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cff-file = "ghrd_10as066n2.periph.rbf";
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early-release-fpga-config;
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};
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soc {
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u-boot,dm-pre-reloc;
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clkmgr@ffd04000 {
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u-boot,dm-pre-reloc;
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clocks {
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u-boot,dm-pre-reloc;
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osc1 {
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u-boot,dm-pre-reloc;
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clock-frequency = <25000000>;
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clock-output-names = "altera_arria10_hps_eosc1-clk";
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};
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cb_intosc_ls_clk {
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u-boot,dm-pre-reloc;
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clock-frequency = <60000000>;
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clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
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};
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f2s_free_clk {
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u-boot,dm-pre-reloc;
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clock-frequency = <200000000>;
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clock-output-names = "altera_arria10_hps_f2h_free-clk";
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};
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main_pll {
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u-boot,dm-pre-reloc;
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/*
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* Address Block: soc_clock_manager_OCP_SLV.
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* i_clk_mgr_mainpllgrp
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*/
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altr,of_reg_value = <
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0 /* Field: vco0.psrc */
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1 /* Field: vco1.denom */
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191 /* Field: vco1.numer */
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0 /* Field: mpuclk */
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0 /* Field: mpuclk.cnt */
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0 /* Field: mpuclk.src */
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0 /* Field: nocclk */
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0 /* Field: nocclk.cnt */
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0 /* Field: nocclk.src */
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900 /* Field: cntr2clk.cnt */
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900 /* Field: cntr3clk.cnt */
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900 /* Field: cntr4clk.cnt */
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900 /* Field: cntr5clk.cnt */
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900 /* Field: cntr6clk.cnt */
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900 /* Field: cntr7clk.cnt */
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0 /* Field: cntr7clk.src */
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900 /* Field: cntr8clk.cnt */
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900 /* Field: cntr9clk.cnt */
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0 /* Field: cntr9clk.src */
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900 /* Field: cntr15clk.cnt */
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0 /* Field: nocdiv.l4mainclk */
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0 /* Field: nocdiv.l4mpclk */
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2 /* Field: nocdiv.l4spclk */
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0 /* Field: nocdiv.csatclk */
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1 /* Field: nocdiv.cstraceclk */
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1 /* Field: nocdiv.cspdbgclk */
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>;
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};
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periph_pll {
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u-boot,dm-pre-reloc;
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/*
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* Address Block: soc_clock_manager_OCP_SLV.
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* i_clk_mgr_perpllgrp
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*/
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altr,of_reg_value = <
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0 /* Field: vco0.psrc */
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1 /* Field: vco1.denom */
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159 /* Field: vco1.numer */
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7 /* Field: cntr2clk.cnt */
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1 /* Field: cntr2clk.src */
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900 /* Field: cntr3clk.cnt */
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1 /* Field: cntr3clk.src */
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19 /* Field: cntr4clk.cnt */
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1 /* Field: cntr4clk.src */
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499 /* Field: cntr5clk.cnt */
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1 /* Field: cntr5clk.src */
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9 /* Field: cntr6clk.cnt */
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1 /* Field: cntr6clk.src */
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900 /* Field: cntr7clk.cnt */
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900 /* Field: cntr8clk.cnt */
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0 /* Field: cntr8clk.src */
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900 /* Field: cntr9clk.cnt */
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0 /* Field: emacctl.emac0sel */
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0 /* Field: emacctl.emac1sel */
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0 /* Field: emacctl.emac2sel */
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32000 /* Field: gpiodiv.gpiodbclk */
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>;
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};
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altera {
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u-boot,dm-pre-reloc;
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/*
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* Address Block: soc_clock_manager_OCP_SLV.
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* i_clk_mgr_alteragrp
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*/
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altr,of_reg_value = <
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0x0384000b /* Register: nocclk */
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0x03840001 /* Register: mpuclk */
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>;
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};
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};
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};
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/*
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* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
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* Binding: pinmux
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*/
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i_io48_pin_mux: pinmux@0xffd07000 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "pinctrl-single";
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reg = <0xffd07000 0x00000800>;
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reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
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/*
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* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
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* i_io48_pin_mux_shared_3v_io_grp
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*/
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shared {
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u-boot,dm-pre-reloc;
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reg = <0xffd07000 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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pinctrl-single,pins =
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/* Reg: pinmux_shared_io_q1_1 */
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<0x00000000 0x00000008>,
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/* Reg: pinmux_shared_io_q1_2 */
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<0x00000004 0x00000008>,
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/* Reg: pinmux_shared_io_q1_3 */
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<0x00000008 0x00000008>,
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/* Reg: pinmux_shared_io_q1_4 */
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<0x0000000c 0x00000008>,
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/* Reg: pinmux_shared_io_q1_5 */
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<0x00000010 0x00000008>,
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/* Reg: pinmux_shared_io_q1_6 */
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<0x00000014 0x00000008>,
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/* Reg: pinmux_shared_io_q1_7 */
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<0x00000018 0x00000008>,
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/* Reg: pinmux_shared_io_q1_8 */
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<0x0000001c 0x00000008>,
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/* Reg: pinmux_shared_io_q1_9 */
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<0x00000020 0x00000008>,
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/* Reg: pinmux_shared_io_q1_10 */
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<0x00000024 0x00000008>,
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/* Reg: pinmux_shared_io_q1_11 */
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<0x00000028 0x00000008>,
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/* Reg: pinmux_shared_io_q1_12 */
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<0x0000002c 0x00000008>,
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/* Reg: pinmux_shared_io_q2_1 */
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<0x00000030 0x00000004>,
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/* Reg: pinmux_shared_io_q2_2 */
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<0x00000034 0x00000004>,
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/* Reg: pinmux_shared_io_q2_3 */
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<0x00000038 0x00000004>,
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/* Reg: pinmux_shared_io_q2_4 */
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<0x0000003c 0x00000004>,
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/* Reg: pinmux_shared_io_q2_5 */
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<0x00000040 0x00000004>,
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/* Reg: pinmux_shared_io_q2_6 */
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<0x00000044 0x00000004>,
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/* Reg: pinmux_shared_io_q2_7 */
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<0x00000048 0x00000004>,
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/* Reg: pinmux_shared_io_q2_8 */
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<0x0000004c 0x00000004>,
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/* Reg: pinmux_shared_io_q2_9 */
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<0x00000050 0x00000004>,
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/* Reg: pinmux_shared_io_q2_10 */
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<0x00000054 0x00000004>,
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/* Reg: pinmux_shared_io_q2_11 */
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<0x00000058 0x00000004>,
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/* Reg: pinmux_shared_io_q2_12 */
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<0x0000005c 0x00000004>,
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/* Reg: pinmux_shared_io_q3_1 */
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<0x00000060 0x00000003>,
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/* Reg: pinmux_shared_io_q3_2 */
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<0x00000064 0x00000003>,
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/* Reg: pinmux_shared_io_q3_3 */
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<0x00000068 0x00000003>,
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/* Reg: pinmux_shared_io_q3_4 */
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<0x0000006c 0x00000003>,
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/* Reg: pinmux_shared_io_q3_5 */
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<0x00000070 0x00000003>,
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/* Reg: pinmux_shared_io_q3_6 */
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<0x00000074 0x0000000f>,
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/* Reg: pinmux_shared_io_q3_7 */
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<0x00000078 0x0000000a>,
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/* Reg: pinmux_shared_io_q3_8 */
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<0x0000007c 0x0000000a>,
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/* Reg: pinmux_shared_io_q3_9 */
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<0x00000080 0x0000000a>,
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/* Reg: pinmux_shared_io_q3_10 */
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<0x00000084 0x0000000a>,
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/* Reg: pinmux_shared_io_q3_11 */
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<0x00000088 0x00000001>,
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/* Reg: pinmux_shared_io_q3_12 */
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<0x0000008c 0x00000001>,
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/* Reg: pinmux_shared_io_q4_1 */
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<0x00000090 0x00000000>,
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/* Reg: pinmux_shared_io_q4_2 */
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<0x00000094 0x00000000>,
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/* Reg: pinmux_shared_io_q4_3 */
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<0x00000098 0x0000000f>,
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/* Reg: pinmux_shared_io_q4_4 */
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<0x0000009c 0x0000000c>,
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/* Reg: pinmux_shared_io_q4_5 */
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<0x000000a0 0x0000000f>,
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/* Reg: pinmux_shared_io_q4_6 */
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<0x000000a4 0x0000000f>,
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/* Reg: pinmux_shared_io_q4_7 */
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<0x000000a8 0x0000000a>,
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/* Reg: pinmux_shared_io_q4_8 */
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<0x000000ac 0x0000000a>,
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/* Reg: pinmux_shared_io_q4_9 */
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<0x000000b0 0x0000000c>,
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/* Reg: pinmux_shared_io_q4_10 */
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<0x000000b4 0x0000000c>,
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/* Reg: pinmux_shared_io_q4_11 */
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<0x000000b8 0x0000000c>,
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/* Reg: pinmux_shared_io_q4_12 */
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<0x000000bc 0x0000000c>;
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};
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/*
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* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
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* i_io48_pin_mux_dedicated_io_grp
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*/
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dedicated {
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u-boot,dm-pre-reloc;
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reg = <0xffd07200 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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pinctrl-single,pins =
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/* Reg: pinmux_dedicated_io_4 */
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<0x0000000c 0x00000008>,
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/* Reg: pinmux_dedicated_io_5 */
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<0x00000010 0x00000008>,
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/* Reg: pinmux_dedicated_io_6 */
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<0x00000014 0x00000008>,
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/* Regi: pinmux_dedicated_io_7 */
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<0x00000018 0x00000008>,
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/* Reg: pinmux_dedicated_io_8 */
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<0x0000001c 0x00000008>,
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/* Reg: pinmux_dedicated_io_9 */
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<0x00000020 0x00000008>,
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/* Reg: pinmux_dedicated_io_10 */
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<0x00000024 0x0000000a>,
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/* Reg: pinmux_dedicated_io_11 */
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<0x00000028 0x0000000a>,
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/* Reg: pinmux_dedicated_io_12 */
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<0x0000002c 0x00000008>,
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/* Reg: pinmux_dedicated_io_13 */
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<0x00000030 0x00000008>,
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/* Reg: pinmux_dedicated_io_14 */
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<0x00000034 0x00000008>,
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/* Reg: pinmux_dedicated_io_15 */
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<0x00000038 0x00000008>,
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/* Reg: pinmux_dedicated_io_16 */
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<0x0000003c 0x0000000d>,
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/* Reg: pinmux_dedicated_io_17 */
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<0x00000040 0x0000000d>;
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};
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/*
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* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
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* i_io48_pin_mux_dedicated_io_grp
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*/
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dedicated_cfg {
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u-boot,dm-pre-reloc;
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reg = <0xffd07200 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x003f3f3f>;
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pinctrl-single,pins =
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/* Reg: cfg_dedicated_io_bank */
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<0x00000100 0x00000101>,
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/* Reg: cfg_dedicated_io_1 */
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<0x00000104 0x000b080a>,
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/* Reg: cfg_dedicated_io_2 */
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<0x00000108 0x000b080a>,
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/* Reg: cfg_dedicated_io_3 */
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<0x0000010c 0x000b080a>,
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/* Reg: cfg_dedicated_io_4 */
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<0x00000110 0x000a282a>,
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/* Reg: cfg_dedicated_io_5 */
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<0x00000114 0x000a282a>,
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/* Reg: cfg_dedicated_io_6 */
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<0x00000118 0x0008282a>,
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/* Reg: cfg_dedicated_io_7 */
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<0x0000011c 0x000a282a>,
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/* Reg: cfg_dedicated_io_8 */
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<0x00000120 0x000a282a>,
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/* Reg: cfg_dedicated_io_9 */
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<0x00000124 0x000a282a>,
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/* Reg: cfg_dedicated_io_10 */
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<0x00000128 0x00090000>,
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/* Reg: cfg_dedicated_io_11 */
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<0x0000012c 0x00090000>,
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/* Reg: cfg_dedicated_io_12 */
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<0x00000130 0x000b282a>,
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/* Reg: cfg_dedicated_io_13 */
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<0x00000134 0x000b282a>,
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/* Reg: cfg_dedicated_io_14 */
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<0x00000138 0x000b282a>,
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/* Reg: cfg_dedicated_io_15 */
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<0x0000013c 0x000b282a>,
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|
|
/* Reg: cfg_dedicated_io_16 */
|
||
|
|
<0x00000140 0x0008282a>,
|
||
|
|
/* Reg: cfg_dedicated_io_17 */
|
||
|
|
<0x00000144 0x000a282a>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
||
|
|
* i_io48_pin_mux_fpga_interface_grp
|
||
|
|
*/
|
||
|
|
fpga {
|
||
|
|
u-boot,dm-pre-reloc;
|
||
|
|
reg = <0xffd07400 0x00000100>;
|
||
|
|
pinctrl-single,register-width = <32>;
|
||
|
|
pinctrl-single,function-mask = <0x00000001>;
|
||
|
|
pinctrl-single,pins =
|
||
|
|
/* Reg: pinmux_emac0_usefpga */
|
||
|
|
<0x00000000 0x00000000>,
|
||
|
|
/* Reg: pinmux_emac1_usefpga */
|
||
|
|
<0x00000004 0x00000000>,
|
||
|
|
/* Reg: pinmux_emac2_usefpga */
|
||
|
|
<0x00000008 0x00000000>,
|
||
|
|
/* Reg: pinmux_i2c0_usefpga */
|
||
|
|
<0x0000000c 0x00000000>,
|
||
|
|
/* Reg: pinmux_i2c1_usefpga */
|
||
|
|
<0x00000010 0x00000000>,
|
||
|
|
/* Reg: pinmux_i2c_emac0_usefpga */
|
||
|
|
<0x00000014 0x00000000>,
|
||
|
|
/* Reg: pinmux_i2c_emac1_usefpga */
|
||
|
|
<0x00000018 0x00000000>,
|
||
|
|
/* Reg: pinmux_i2c_emac2_usefpga */
|
||
|
|
<0x0000001c 0x00000000>,
|
||
|
|
/* Reg: pinmux_nand_usefpga */
|
||
|
|
<0x00000020 0x00000000>,
|
||
|
|
/* Reg: pinmux_qspi_usefpga */
|
||
|
|
<0x00000024 0x00000000>,
|
||
|
|
/* Reg: pinmux_sdmmc_usefpga */
|
||
|
|
<0x00000028 0x00000000>,
|
||
|
|
/* Reg: pinmux_spim0_usefpga */
|
||
|
|
<0x0000002c 0x00000000>,
|
||
|
|
/* Reg: pinmux_spim1_usefpga */
|
||
|
|
<0x00000030 0x00000000>,
|
||
|
|
/* Reg: pinmux_spis0_usefpga */
|
||
|
|
<0x00000034 0x00000000>,
|
||
|
|
/* Reg: pinmux_spis1_usefpga */
|
||
|
|
<0x00000038 0x00000000>,
|
||
|
|
/* Reg: pinmux_uart0_usefpga */
|
||
|
|
<0x0000003c 0x00000000>,
|
||
|
|
/* Reg: pinmux_uart1_usefpga */
|
||
|
|
<0x00000040 0x00000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i_noc: noc@0xffd10000 {
|
||
|
|
u-boot,dm-pre-reloc;
|
||
|
|
compatible = "altr,socfpga-a10-noc";
|
||
|
|
reg = <0xffd10000 0x00008000>;
|
||
|
|
reg-names = "mpu_m0";
|
||
|
|
|
||
|
|
firewall {
|
||
|
|
u-boot,dm-pre-reloc;
|
||
|
|
/*
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* mpuregion0addr.base
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* mpuregion0addr.limit
|
||
|
|
*/
|
||
|
|
altr,mpu0 = <0x00000000 0x0000ffff>;
|
||
|
|
/*
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
||
|
|
* hpsregion0addr.base
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
||
|
|
* hpsregion0addr.limit
|
||
|
|
*/
|
||
|
|
altr,l3-0 = <0x00000000 0x0000ffff>;
|
||
|
|
/*
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram0region0addr.base
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram0region0addr.limit
|
||
|
|
*/
|
||
|
|
altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
|
||
|
|
/*
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram1region0addr.base
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram1region0addr.limit
|
||
|
|
*/
|
||
|
|
altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
|
||
|
|
/*
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram2region0addr.base
|
||
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||
|
|
* I_NOC.mpu_m0.
|
||
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||
|
|
* fpga2sdram2region0addr.limit
|
||
|
|
*/
|
||
|
|
altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge0: fpgabridge@0 {
|
||
|
|
compatible = "altr,socfpga-hps2fpga-bridge";
|
||
|
|
altr,init-val = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge1: fpgabridge@1 {
|
||
|
|
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||
|
|
altr,init-val = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge2: fpgabridge@2 {
|
||
|
|
compatible = "altr,socfpga-fpga2hps-bridge";
|
||
|
|
altr,init-val = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge3: fpgabridge@3 {
|
||
|
|
compatible = "altr,socfpga-fpga2sdram0-bridge";
|
||
|
|
altr,init-val = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge4: fpgabridge@4 {
|
||
|
|
compatible = "altr,socfpga-fpga2sdram1-bridge";
|
||
|
|
altr,init-val = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hps_fpgabridge5: fpgabridge@5 {
|
||
|
|
compatible = "altr,socfpga-fpga2sdram2-bridge";
|
||
|
|
altr,init-val = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|