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442 lines
15 KiB
C
442 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#if defined(CONFIG_DDR4)
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#include "ddr3_init.h"
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#include "mv_ddr_regs.h"
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static int mv_ddr4_dynamic_pb_wl_supp(u32 dev_num, enum mv_wl_supp_mode ecc_mode);
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/* compare test for ddr4 write leveling supplementary */
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#define MV_DDR4_COMP_TEST_NO_RESULT 0
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#define MV_DDR4_COMP_TEST_RESULT_0 1
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#define MV_DDR4_XSB_COMP_PATTERNS_NUM 8
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static u8 mv_ddr4_xsb_comp_test(u32 dev_num, u32 subphy_num, u32 if_id,
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enum mv_wl_supp_mode ecc_mode)
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{
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u32 wl_invert;
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u8 pb_key, bit, bit_max, word;
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struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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u32 subphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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uint64_t read_pattern_64[MV_DDR4_XSB_COMP_PATTERNS_NUM] = {0};
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/*
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* FIXME: the pattern below is used for writing to the memory
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* by the cpu. it was changed to be written through the odpg.
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* for a workaround
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* uint64_t pattern_test_table_64[MV_DDR4_XSB_COMP_PATTERNS_NUM] = {
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* 0xffffffffffffffff,
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* 0xffffffffffffffff,
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* 0x0000000000000000,
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* 0x0000000000000000,
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* 0x0000000000000000,
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* 0x0000000000000000,
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* 0xffffffffffffffff,
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* 0xffffffffffffffff};
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*/
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u32 read_pattern[MV_DDR4_XSB_COMP_PATTERNS_NUM];
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/*u32 pattern_test_table[MV_DDR4_XSB_COMP_PATTERNS_NUM] = {
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0xffffffff,
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0xffffffff,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff,
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0xffffffff}; TODO: use pattern_table_get_word */
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int i, status;
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uint64_t data64;
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uintptr_t addr64;
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int ecc_running = 0;
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u32 ecc_read_subphy_num = 0; /* FIXME: change ecc read subphy num to be configurable */
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u8 bit_counter = 0;
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int edge = 0;
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/* write and read data */
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if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)) {
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status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG,
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effective_cs << ODPG_DATA_CS_OFFS,
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ODPG_DATA_CS_MASK << ODPG_DATA_CS_OFFS);
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if (status != MV_OK)
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return status;
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addr64 = (uintptr_t)pattern_table[PATTERN_TEST].start_addr;
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/*
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* FIXME: changed the load pattern to memory through the odpg
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* this change is needed to be validate
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* this change is done due to un calibrated dm at this stage
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* the below code is the code for loading the pattern directly
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* to the memory
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*
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* for (i = 0; i < MV_DDR4_XSB_COMP_PATTERNS_NUM; i++) {
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* data64 = pattern_test_table_64[i];
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* writeq(addr64, data64);
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* addr64 += sizeof(uint64_t);
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*}
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* FIXME: the below code loads the pattern to the memory through the odpg
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* it loads it twice to due supplementary failure, need to check it
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*/
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int j;
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for (j = 0; j < 2; j++)
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ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST);
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} else if (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(tm->bus_act_mask, subphy_max)) {
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status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG,
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effective_cs << ODPG_DATA_CS_OFFS,
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ODPG_DATA_CS_MASK << ODPG_DATA_CS_OFFS);
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if (status != MV_OK)
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return status;
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/*
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* FIXME: changed the load pattern to memory through the odpg
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* this change is needed to be validate
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* this change is done due to un calibrated dm at this stage
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* the below code is the code for loading the pattern directly
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* to the memory
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*/
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int j;
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for (j = 0; j < 2; j++)
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ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST);
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} else {
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/*
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* FIXME: changed the load pattern to memory through the odpg
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* this change is needed to be validate
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* this change is done due to un calibrated dm at this stage
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* the below code is the code for loading the pattern directly
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* to the memory
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*/
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int j;
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for (j = 0; j < 2; j++)
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ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST);
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}
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if ((ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4) ||
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(ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3 ||
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ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8)) {
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/* disable ecc write mux */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x100);
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if (status != MV_OK)
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return status;
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/* enable read data ecc mux */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x3, 0x3);
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if (status != MV_OK)
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return status;
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/* unset training start bit */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_REG, 0x80000000, 0x80000000);
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if (status != MV_OK)
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return status;
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ecc_running = 1;
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ecc_read_subphy_num = ECC_READ_BUS_0;
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}
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if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)) {
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status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG,
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effective_cs << ODPG_DATA_CS_OFFS,
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ODPG_DATA_CS_MASK << ODPG_DATA_CS_OFFS);
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if (status != MV_OK)
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return status;
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/*
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* in case of reading the pattern read it from the address x 8
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* the odpg multiply by 8 the addres to read from
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*/
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addr64 = ((uintptr_t)pattern_table[PATTERN_TEST].start_addr) << 3;
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for (i = 0; i < MV_DDR4_XSB_COMP_PATTERNS_NUM; i++) {
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data64 = readq(addr64);
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addr64 += sizeof(uint64_t);
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read_pattern_64[i] = data64;
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}
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("xsb comp: if %d bus id %d\n", 0, subphy_num));
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for (edge = 0; edge < 8; edge++)
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("0x%16llx\n", (unsigned long long)read_pattern_64[edge]));
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("\n"));
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} else if (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(tm->bus_act_mask, subphy_max)) {
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status = ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG,
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effective_cs << ODPG_DATA_CS_OFFS,
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ODPG_DATA_CS_MASK << ODPG_DATA_CS_OFFS);
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if (status != MV_OK)
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return status;
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status = ddr3_tip_ext_read(dev_num, if_id, pattern_table[PATTERN_TEST].start_addr << 3,
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1, read_pattern);
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if (status != MV_OK)
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return status;
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("xsb comp: if %d bus id %d\n", 0, subphy_num));
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for (edge = 0; edge < 8; edge++)
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("0x%16x\n", read_pattern[edge]));
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("\n"));
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} else {
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status = ddr3_tip_ext_read(dev_num, if_id, ((pattern_table[PATTERN_TEST].start_addr << 3) +
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((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern);
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if (status != MV_OK)
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return status;
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("xsb comp: if %d bus id %d\n", 0, subphy_num));
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for (edge = 0; edge < 8; edge++)
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("0x%16x\n", read_pattern[edge]));
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DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("\n"));
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}
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/* read centralization result to decide on half phase by inverse bit */
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status = ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, subphy_num, DDR_PHY_DATA,
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CTX_PHY_REG(0), &wl_invert);
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if (status != MV_OK)
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return status;
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if ((wl_invert & 0x20) != 0)
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wl_invert = 1;
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else
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wl_invert = 0;
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/* for ecc, read from the "read" subphy (usualy subphy 0) */
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if (ecc_running)
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subphy_num = ecc_read_subphy_num;
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/* per bit loop*/
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bit_max = subphy_num * BUS_WIDTH_IN_BITS + BUS_WIDTH_IN_BITS;
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for (bit = subphy_num * BUS_WIDTH_IN_BITS; bit < bit_max; bit++) {
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/* get per bit pattern key (value of the same bit in the pattern) */
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pb_key = 0;
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for (word = 0; word < MV_DDR4_XSB_COMP_PATTERNS_NUM; word++) {
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if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)) {
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if ((read_pattern_64[word] & ((uint64_t)1 << bit)) != 0)
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pb_key |= (1 << word);
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} else {
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if ((read_pattern[word] & (1 << bit)) != 0)
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pb_key |= (1 << word);
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}
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}
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/* find the key value and make decision */
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switch (pb_key) {
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/* case(s) for 0 */
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case 0b11000011: /* nominal */
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case 0b10000011: /* sample at start of UI sample at the dqvref TH */
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case 0b10000111: /* sample at start of UI sample at the dqvref TH */
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case 0b11000001: /* sample at start of UI sample at the dqvref TH */
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case 0b11100001: /* sample at start of UI sample at the dqvref TH */
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case 0b11100011: /* sample at start of UI sample at the dqvref TH */
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case 0b11000111: /* sample at start of UI sample at the dqvref TH */
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bit_counter++;
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break;
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} /* end of switch */
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} /* end of per bit loop */
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/* check all bits in the current subphy has met the switch condition above */
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if (bit_counter == BUS_WIDTH_IN_BITS)
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return MV_DDR4_COMP_TEST_RESULT_0;
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else {
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DEBUG_LEVELING(
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DEBUG_LEVEL_INFO,
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("different supplementary results (%d -> %d)\n",
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MV_DDR4_COMP_TEST_NO_RESULT, MV_DDR4_COMP_TEST_RESULT_0));
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return MV_DDR4_COMP_TEST_NO_RESULT;
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}
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}
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int mv_ddr4_dynamic_wl_supp(u32 dev_num)
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{
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int status = MV_OK;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask)) {
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if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask))
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status = mv_ddr4_dynamic_pb_wl_supp(dev_num, WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4);
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else if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
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status = mv_ddr4_dynamic_pb_wl_supp(dev_num, WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3);
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else /* WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8 */
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status = mv_ddr4_dynamic_pb_wl_supp(dev_num, WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8);
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if (status != MV_OK)
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return status;
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status = mv_ddr4_dynamic_pb_wl_supp(dev_num, WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS);
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} else { /* regular supplementary for data subphys in non-ecc mode */
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status = mv_ddr4_dynamic_pb_wl_supp(dev_num, WRITE_LEVELING_SUPP_REG_MODE);
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}
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return status;
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}
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/* dynamic per bit write leveling supplementary */
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static int mv_ddr4_dynamic_pb_wl_supp(u32 dev_num, enum mv_wl_supp_mode ecc_mode)
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{
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u32 if_id;
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u32 subphy_start, subphy_end;
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u32 subphy_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
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u8 compare_result = 0;
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u32 orig_phase;
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u32 rd_data, wr_data = 0;
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u32 flag, step;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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u32 ecc_phy_access_id;
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int status;
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if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4 ||
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ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3 ||
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ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8) {
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/* enable ecc write mux */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x100, 0x100);
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if (status != MV_OK)
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return status;
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/* disable read data ecc mux */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x3);
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if (status != MV_OK)
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return status;
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/* unset training start bit */
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status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_REG, 0x0, 0x80000000);
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if (status != MV_OK)
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return status;
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if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3)
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ecc_phy_access_id = ECC_PHY_ACCESS_3;
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|
else if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4)
|
||
|
|
ecc_phy_access_id = ECC_PHY_ACCESS_4;
|
||
|
|
else /* ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8 */
|
||
|
|
ecc_phy_access_id = ECC_PHY_ACCESS_8;
|
||
|
|
|
||
|
|
subphy_start = ecc_phy_access_id;
|
||
|
|
subphy_end = subphy_start + 1;
|
||
|
|
} else if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS) {
|
||
|
|
/* disable ecc write mux */
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_SW_2_REG, 0x0, 0x100);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
/* disable ecc mode*/
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
SDRAM_CFG_REG, 0, 0x40000);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
subphy_start = 0;
|
||
|
|
if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, subphy_num))
|
||
|
|
subphy_end = (subphy_num - 1) / 2;
|
||
|
|
else
|
||
|
|
subphy_end = subphy_num - 1;
|
||
|
|
} else { /* ecc_mode == WRITE_LEVELING_SUPP_REG_MODE */
|
||
|
|
subphy_start = 0;
|
||
|
|
/* remove ecc subphy prior to algorithm's start */
|
||
|
|
subphy_end = subphy_num - 1; /* TODO: check it */
|
||
|
|
}
|
||
|
|
|
||
|
|
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
|
||
|
|
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
|
||
|
|
for (subphy_num = subphy_start; subphy_num < subphy_end; subphy_num++) {
|
||
|
|
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
|
||
|
|
flag = 1;
|
||
|
|
step = 0;
|
||
|
|
status = ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, subphy_num, DDR_PHY_DATA,
|
||
|
|
WL_PHY_REG(effective_cs), &rd_data);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
orig_phase = (rd_data >> 6) & 0x7;
|
||
|
|
while (flag != 0) {
|
||
|
|
/* get decision for subphy */
|
||
|
|
compare_result = mv_ddr4_xsb_comp_test(dev_num, subphy_num, if_id, ecc_mode);
|
||
|
|
if (compare_result == MV_DDR4_COMP_TEST_RESULT_0) {
|
||
|
|
flag = 0;
|
||
|
|
} else { /* shift phase to -1 */
|
||
|
|
step++;
|
||
|
|
if (step == 1) { /* set phase (0x0[6-8]) to -2 */
|
||
|
|
if (orig_phase > 1)
|
||
|
|
wr_data = (rd_data & ~0x1c0) | ((orig_phase - 2) << 6);
|
||
|
|
else if (orig_phase == 1)
|
||
|
|
wr_data = (rd_data & ~0x1df);
|
||
|
|
if (orig_phase >= 1)
|
||
|
|
ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id,
|
||
|
|
ACCESS_TYPE_UNICAST, subphy_num,
|
||
|
|
DDR_PHY_DATA,
|
||
|
|
WL_PHY_REG(effective_cs), wr_data);
|
||
|
|
} else if (step == 2) { /* shift phase to +1 */
|
||
|
|
if (orig_phase <= 5) {
|
||
|
|
wr_data = (rd_data & ~0x1c0) | ((orig_phase + 2) << 6);
|
||
|
|
ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id,
|
||
|
|
ACCESS_TYPE_UNICAST, subphy_num,
|
||
|
|
DDR_PHY_DATA,
|
||
|
|
WL_PHY_REG(effective_cs), wr_data);
|
||
|
|
}
|
||
|
|
} else if (step == 3) {
|
||
|
|
if (orig_phase <= 3) {
|
||
|
|
wr_data = (rd_data & ~0x1c0) | ((orig_phase + 4) << 6);
|
||
|
|
ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id,
|
||
|
|
ACCESS_TYPE_UNICAST, subphy_num,
|
||
|
|
DDR_PHY_DATA,
|
||
|
|
WL_PHY_REG(effective_cs), wr_data);
|
||
|
|
}
|
||
|
|
} else { /* error */
|
||
|
|
flag = 0;
|
||
|
|
compare_result = MV_DDR4_COMP_TEST_NO_RESULT;
|
||
|
|
training_result[training_stage][if_id] = TEST_FAILED;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if ((training_result[training_stage][if_id] == NO_TEST_DONE) ||
|
||
|
|
(training_result[training_stage][if_id] == TEST_SUCCESS))
|
||
|
|
training_result[training_stage][if_id] = TEST_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS) {
|
||
|
|
/* enable ecc write mux */
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_SW_2_REG, 0x100, 0x100);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
/* enable ecc mode*/
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
SDRAM_CFG_REG, 0x40000, 0x40000);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
} else if (ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4 ||
|
||
|
|
ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3 ||
|
||
|
|
ecc_mode == WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8) {
|
||
|
|
/* enable ecc write mux */
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_SW_2_REG, 0x100, 0x100);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
/* disable read data ecc mux */
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_SW_2_REG, 0x0, 0x3);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
/* unset training start bit */
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_REG, 0x0, 0x80000000);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
|
||
|
|
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
||
|
|
TRAINING_SW_1_REG, 0x1 << 16, 0x1 << 16);
|
||
|
|
if (status != MV_OK)
|
||
|
|
return status;
|
||
|
|
} else {
|
||
|
|
/* do nothing for WRITE_LEVELING_SUPP_REG_MODE */;
|
||
|
|
}
|
||
|
|
if (training_result[training_stage][0] == TEST_SUCCESS)
|
||
|
|
return MV_OK;
|
||
|
|
else
|
||
|
|
return MV_FAIL;
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_DDR4 */
|