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u-boot/arch/arm/lib/semihosting.S

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arm: semihosting: replace inline assembly with assembly file So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about one instruction, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembly file. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-02-07 15:21:04 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) 2022 Arm Ltd.
*/
#include <config.h>
#include <asm/macro.h>
#include <linux/linkage.h>
.pushsection .text.smh_trap, "ax"
/* long smh_trap(unsigned int sysnum, void *addr); */
ENTRY(smh_trap)
#if defined(CONFIG_ARM64)
hlt #0xf000
#elif defined(CONFIG_CPU_V7M)
bkpt #0xab
#elif defined(CONFIG_SYS_THUMB_BUILD)
svc #0xab
#else
arm: semihosting: Fix returning from traps on ARMv6 and lower U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts are taken in supervisor mode. When entering an interrupt, the link register is set to the address of the next instruction. However, if we are already in supervisor mode, this clobbers the link register. The debugger can't help us, since by the time it notices we've taken a software interrupt, the link register is already gone. Work around this by moving the return address to another register. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-10-27 20:40:14 +00:00
#if CONFIG_SYS_ARM_ARCH < 7
/* Before the ARMv7 exception model, svc (swi) clobbers lr */
mov r2, lr
#endif
arm: semihosting: replace inline assembly with assembly file So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about one instruction, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembly file. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-02-07 15:21:04 +00:00
svc #0x123456
#endif
#if defined(CONFIG_ARM64)
ret
arm: semihosting: Fix returning from traps on ARMv6 and lower U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts are taken in supervisor mode. When entering an interrupt, the link register is set to the address of the next instruction. However, if we are already in supervisor mode, this clobbers the link register. The debugger can't help us, since by the time it notices we've taken a software interrupt, the link register is already gone. Work around this by moving the return address to another register. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-10-27 20:40:14 +00:00
#elif CONFIG_SYS_ARM_ARCH < 7
bx r2
arm: semihosting: replace inline assembly with assembly file So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about one instruction, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembly file. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-02-07 15:21:04 +00:00
#else
bx lr
#endif
ENDPROC(smh_trap)
.popsection
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